INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Transcription

1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS Logic Family Specifications The IC6 74C/CT/CU/CMOS Logic Package Information The IC6 74C/CT/CU/CMOS Logic Package Outlines File under Integrated Circuits, IC6 December 199

2 FEATURES Output capability: standard I CC category: MSI GENERAL DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with the 494 of the 4B series. They are specified in compliance with JEDEC standard no. 7A. The are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input (D) to the parallel buffered -state outputs (QP to QP 7 ). The parallel outputs may be connected directly to common bus lines. Data is shifted on the positive-going clock (CP) transitions. The data in each shift register stage is transferred to the storage register when the strobe input (STR) is IG. Data in the storage register appears at the outputs whenever the output enable input (OE) signal is IG. Two serial outputs (QS 1 and QS 2 ) are available for cascading a number of 494 devices. Data is available at QS 1 on the positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at QS 2 on the next negative-going clock edge and is for cascading 494 devices when the clock rise time is slow. APPLICATIONS Serial-to-parallel data conversion Remote control holding register QUICK REFEREE DATA GND = V; T amb = 25 C; t r = t f = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS C CT UNIT t PL / t PL propagation delay C L = 15 pf; V CC = 5 V CP to QS ns CP to QS ns CP to QP n 2 21 ns STR to QP n ns f max maximum clock frequency Mz C I input capacitance.5.5 pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS Logic Package Information. December 199 2

3 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUTION 1 STR strobe input 2 D serial input CP clock input 4, 5, 6, 7,, 1, 12, 11 QP to QP 7 parallel outputs 8 GND ground ( V) 9, 1 QS 1,QS 2 serial outputs 15 OE output enable input 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig. IEC logic symbol. December 199

4 Fig.4 Functional diagram. Fig.5 Logic diagram. December 199 4

5 FUTION TABLE INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS CP OE STR D QP QP n QS 1 QS 2 L L X X L X X X L Notes 1. = IG voltage level L = LOW voltage level X = don t care Z = high impedance OFF-state = no change = LOW-to-IG CP transition = IG-to-LOW CP transition Q 6 = the information in the seventh register stage is transferred to the 8th register stage and QS n output at the positive clock edge Z Z L Z Z QP n - 1 QP n - 1 Q 6 Q 6 Q 6 Q 6 QP 7 QP 7 Fig.6 Timing diagram. December 199 5

6 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS Logic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 74C GND = V; t r = t f = 6 ns; C L = 5 pf SYMBOL t PL / t PL t PL / t PL t PL / t PL t PL / t PL t PZ / t PZL t PZ / t PLZ PARAMETER propagation delay 5 CP to QS 1 18 propagation delay 44 CP to QS propagation delay 6 CP to QP n 2 18 propagation delay 58 STR to QP n state output enable time 55 OE to QP n state output disable 41 time OE to QP n t TL / t TL output transition time t W t W t su t su clock pulse width IG or LOW strobe pulse width IG set-up time D to CP set-up time CP to STR T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) WAVEFORMS Fig.8 Fig.9 Fig.9 Fig.8 Fig.1 Fig.8 December 199 6

7 T amb ( C) TEST CONDITIONS SYMBOL PARAMETER 74C to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t h t h f max hold time D to CP hold time CP to STR maximum clock pulse frequency Mz 2. Fig.1 Fig.8 December 199 7

8 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS Logic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE, CP D STR UNIT LOAD COEFFICIENT December 199 8

9 AC CARACTERISTICS FOR 74CT GND = V; t r = t f = 6 ns; C L = 5 pf T amb ( C) TEST CONDITIONS ns ns ns ns Fig ns Fig ns Fig.9 74CT SYMBOL PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t PL / t PL propagation delay CP to QS 1 t PL / t PL propagation delay CP to QS 2 t PL / t PL propagation delay CP to QP n t PL / t PL propagation delay STR to QP n t PZ / t PZL -state output enable time OE to QP n t PZ / t PLZ -state output disable time OE to QP n t TL / t TL output transition time ns t W t W t su t su t h t h f max clock pulse width IG or LOW strobe pulse width IG set-up time D to CP set-up time CP to STR hold time D to CP hold time CP to STR maximum clock pulse frequency ns ns Fig ns Fig ns Fig ns Fig.1 4 ns Fig Mz December 199 9

10 AC WAVEFORMS (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1. V; V I = GND to V. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1. V; V I = GND to V. Waveforms showing the clock (CP) to output (QP n,qs 1,QS 2 ) propagation delays, the clock pulse width and the maximum clock frequency. Fig.8 Waveforms showing the strobe (STR) to output (QP n ) propagation delays and the strobe pulse width and the clock set-up and hold times for the strobe input. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1. V; V I = GND to V. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1. V; V I = GND to V. Fig.1 Waveforms showing the data set-up and hold times for the data input (D). Fig.9 Waveforms showing the -state enable and disable times for input OE. PACKAGE OUTLINES See 74C/CT/CU/CMOS Logic Package Outlines. December 199 1