Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms. SOI Consortium Conference Tokyo 2016

Transcription

1 Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms Christophe Maleville

2 Substrate readiness 3 lenses view SOI Consortium C1 - Restricted Conference Tokyo

3 SOI maturity curve 1992 Satellite 2005 PC 2015 Mobile NXP/Philips reliability thru thick isolation IBM and AMD leveraged Performance Boost of SOI RFSOI brings Performance/cost breakthru FDSOI enables low power devices ~2 millions wafer/year HVM 3

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5 Planar FDSOI: Undoped Channel Thin Silicon Channel 0.6 L G =25nm - multiple sources contributing to V T variation Source: J. Hartmann, GSA Apr FDSOI Substrate: Thin Si & Thin buried oxide Ultra thin BOX option Back bias control Silicon thickness variations contribution to VT variations - VT sensitivity ~ 25mV/nm All transistors should have Si thickness within ±5Å Threshold Voltage (mv) (V) V Tlin V Tsat Silicon Thickness (nm) Challenges and Opportunities of Extremely Thin SOI (ETSOI) CMOS Technology, A. Khakifirooz, VLSI-TSA

6 FD-SOI: long term collaboration Smart Cut & device experts 2005 Research Institute Donor substrate Advanced R&D Industrialisation Key achievements FDSOI Vt Yield BBias Advanced crystal for 6nm active layer Wafering quality for thin Box bonding ±5 Å Thickness uniformity All spatial frequency thickness control HVM ready 6

7 Smart-Cut 1.0 On-wafer uniformity Oxide uniformity Post-split Silicon uniformity Box WiW thickness post oxidation (Å) Post split WiW Si uniformity (Å)

8 FD-SOI Uniformity Bandwith for improvements Current ellipsometry accurately describes FD-SOI wafer 95% of wafer surface +/-4A 90% of wafer surface +/-3A 8

9 SmartCut 2.0 for FDSOI Start Material OxTop Implant Cleaning Bonding Splitting Finishing Adapted to Oxide Film Thickness Adapted to SOI Film Thickness Final sorting 9

10 Smart-Cut 2.0 Ultrathin Box Capability Uniformity vs roughness FDSOI PDSOI Bonding related defects 10

11 Thermal smoothing principle Silicon surface smoothing at high temperature (RTA, BA) Material transport mechanism Bulk diffusion Evaporation / Condensation Surface diffusion Gas Evaporation / condensation Reaction with contaminant Surface diffusion Silicon Bulk diffusion Simulation of silicon smoothing under high temp anneal F.De Crecy CEA/LETI 11

12 Conventional control plan Thickness + Roughness Layer Total Thickness Variation (Å) SOI Box Handle 0 WtW Ellipso WiW DRM 10-6 Ellipso AFM µm -1 Performance +/-5 Å 6-10 Å P-V 0.8Å RMS Evidence 12

13 Differential Reflective Microscopy (DRM) for complete SOI thickness monitoring Reflectivity of a FD-SOI stack (SOI + BOX) is function of wavelengths By filtering specific wavelength, reflectivity becomes only sensitive to SOI layer thickness variations Microscope calibration 135 HSEB Baldur tool Signal treatment Calibration wafers Ellipso thk, A Elipso Theory, 540nm 105 Spatial wavelength range: 0.5µm 80µm Grey scale map Grey scale Grey scale calibration curve Thickness profile 13

14 All included SOI thickness control (all wafers, all points, all frequencies) Layer Total Thickness Variation (Å) SOI Box Handle 0 WtW Ellipso WiW DRM 10-6 Ellipso AFM µm -1 Performance +/-5 Å 6-10 Å P-V 0.8Å RMS Evidence 14

15 FD28nm: Wafers: ±1 Atomic Layer! 12nm SOI (12nm) Box (25nm) Handle Wafer Si Stack Local Micro FDSOI PDSOI 1 sigma (Å) 15

16 Improved thickness control for 22nm node 20 nm Stack Wafer Si Local Micro Polished Bulk 20FD 28FD 1 sigma (Å) 16

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18 Soitec SOI adoption via Partnerships and Collaborations From technology development to manufacturing RF-SOI TR-SOI UCL & Soitec IP 1 st RF-SOI switch Soitec RFeSi substrate ramp >50% RF-SOI switch mainstream RF-SOI 300mm ramp FD-SOI Materials Research Advanced R&D Industrial Partner 28FD Foundry offer 22FD Foundry offer 18

19 RF-SOI value proposition Enabling best performance, integration and cost-efficiency Performance 4G/LTE-A & beyond performance enabler Integration High integration of RF Front-End module Cost efficient Cost effective technology SOI Bulk GaAs PA first stages Switch PA output stage x2 die size reduction Antenna Switch Module (SP9T ) Cost GaAS BSOS RFSOI in all 4G smartphones Integration on-going Cheaper process cost 19

20 More expensive Substrates for cheaper dies COST Source: GF, Semicon West 2013 Processed wafer cost, FDSOI vs bulk 1. FDSOI allows up to 6 mask levels reduction 2. From 28nm, FDSOI processed wafer is less expensive than equivalent HKMG on bulk silicon IBS,

21 FD-SOI value proposition Enabling best performance, power and cost-efficiency Unique Performance Energy Efficient Cost effective +60% Faster than 28 nm Bulk SLP 5x more battery life than current generation 50% lower mask cost than FinFET Cisco Used in Networking ASICs for datacenters Days of battery life Norrmalized Performance FD-SOI >20% Lower die cost 20 nm Bulk 28 nm Bulk SLP 28 nm Bulk HPP Norrmalized Cost/die (Mature Yields, Q1 19) 14 FinFET $$$$ Sources: GlobalFoundries FD-SOI technology webinar June EETimes article: Freescale, Cisco, Ciena Give Nod to FD- SOI EE Times, March 1, bulk 28 bulk FinFET FD-SOI Sources: GlobalFoundries FD-SOI technology webinar, June 2015 Source: GlobalFoundries FD-SOI technology webinar, June 2015 FD-SOI extends Moore s Law beyond 28 nm enabling cost sensitive applications 21

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23 Multi-sourcing in place for HVM SOI platforms 200mm 300mm 23

24 Take-aways FDSOI substrate is active part of the transistor SmartCut technology allows to meet FDSOI requirements Metrology defined to predict/protect variability on device Die cost reduction can be supported thru right balance between cost and simplification, delivering a pre-processed wafer. Substrate availability /maturity is ready to support FDSOI mass adoption. 24

25 SOI end customers in