Computer System Design. System-on-Chip

Transcription

1 Brochure More information from Computer System Design. System-on-Chip Description: The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses the issues mentioned above. It begins with a global introduction, from the high-level view to the lowest common denominator (the chip itself), then moves on to the three main building blocks of an SOC (processor, memory, and interconnect). Next is an overview of what makes SOC unique (its customization ability and the applications that drive it). The final chapter presents future challenges for system design and SOC possibilities. Contents: Preface xiii List of Abbreviations and Acronyms xvii 1 Introduction to the Systems Approach System Architecture: An Overview Components of the System: Processors, Memories, and Interconnects Hardware and Software: Programmability Versus Performance Processor Architectures Processor: A Functional View Processor: An Architectural View Memory and Addressing SOC Memory Examples Addressing: The Architecture of Memory Memory for SOC Operating System System-Level Interconnection Bus-Based Approach Network-on-Chip Approach An Approach for SOC Design Requirements and Specifi cations Design Iteration System Architecture and Complexity Product Economics and Implications for SOC Factors Affecting Product Costs 31

2 1.9.2 Modeling Product Economics and Technology Complexity: The Lesson for SOC Dealing with Design Complexity Buying IP Reconfi guration Conclusions Problem Set 38 2 Chip Basics: Time, Area, Power, Reliability, and Confi gurability Introduction Design Trade-Offs Requirements and Specifi cations Cycle Time Defi ning a Cycle Optimum Pipeline Performance Die Area and Cost Processor Area Processor Subunits Ideal and Practical Scaling Power Area Time Power Trade-Offs in Processor Design Workstation Processor Embedded Processor Reliability Dealing with Physical Faults Error Detection and Correction Dealing with Manufacturing Faults Memory and Function Scrubbing Confi gurability Why Reconfi gurable Design? Area Estimate of Reconfi gurable Devices Conclusion 71

3 2.10 Problem Set 71 3 Processors Introduction Processor Selection for SOC Overview Example: Soft Processors Examples: Processor Core Selection Basic Concepts in Processor Architecture Instruction Set Some Instruction Set Conventions Branches Interrupts and Exceptions Basic Concepts in Processor Microarchitecture Basic Elements in Instruction Handling The Instruction Decoder and Interlocks Bypassing Execution Unit Buffers: Minimizing Pipeline Delays Mean Request Rate Buffers Buffers Designed for a Fixed or Maximum Request Rate Branches: Reducing the Cost of Branches Branch Target Capture: Branch Target Buffers (BTBs) Branch Prediction More Robust Processors: Vector, Very Long Instruction Word (VLIW), and Superscalar Vector Processors and Vector Instruction Extensions Vector Functional Units VLIW Processors Superscalar Processors Data Dependencies Detecting Instruction Concurrency A Simple Implementation Preserving State with Out-of-Order Execution 116

4 3.12 Processor Evolution and Two Examples Soft and Firm Processor Designs: The Processor as IP High-Performance, Custom-Designed Processors Conclusions Problem Set Memory Design: System-on-Chip and Board-Based Systems Introduction Overview SOC External Memory: Flash SOC Internal Memory: Placement The Size of Memory Scratchpads and Cache Memory Basic Notions Cache Organization Cache Data Write Policies Strategies for Line Replacement at Miss Time Fetching a Line Line Replacement Cache Environment: Effects of System, Transactions, and Multiprogramming Other Types of Cache Split I- and D-Caches and the Effect of Code Density Multilevel Caches Limits on Cache Array Size Evaluating Multilevel Caches Logical Inclusion Virtual-to-Real Translation SOC (On-Die) Memory Systems Board-based (Off-Die) Memory Systems Simple DRAM and the Memory Array SDRAM and DDR SDRAM 152

5 Memory Buffers Models of Simple Processor Memory Interaction Models of Multiple Simple Processors and Memory The Strecker-Ravi Model Interleaved Caches Conclusions Problem Set Interconnect Introduction Overview: Interconnect Architectures Bus: Basic Architecture Arbitration and Protocols Bus Bridge Physical Bus Structure Bus Varieties SOC Standard Buses AMBA CoreConnect Bus Interface Units: Bus Sockets and Bus Wrappers Analytic Bus Models Contention and Shared Bus Simple Bus Model: Without Resubmission Bus Model with Request Resubmission Using the Bus Model: Computing the Offered Occupancy Effect of Bus Transactions and Contention Time Beyond the Bus: NOC with Switch Interconnects Static Networks Dynamic Networks Some NOC Switch Examples A 2-D Grid Example of Direct Networks Asynchronous Crossbar Interconnect for Synchronous SOC (Dynamic Network) Blocking versus Nonblocking 197

6 5.8 Layered Architecture and Network Interface Unit NOC Layered Architecture NOC and NIU Example Bus versus NOC Evaluating Interconnect Networks Static versus Dynamic Networks Comparing Networks: Example Conclusions Problem Set Customization and Confi gurability Introduction Estimating Effectiveness of Customization SOC Customization: An Overview Customizing Instruction Processors Processor Customization Approaches Architecture Description Identifying Custom Instructions Automatically Reconfi gurable Technologies Reconfi gurable Functional Units (FUs) Reconfi gurable Interconnects Software Confi gurable Processors Mapping Designs Onto Reconfi gurable Devices Instance-Specifi c Design Customizable Soft Processor: An Example Reconfi guration Reconfi guration Overhead Analysis Trade-Off Analysis: Reconfi gurable Parallelism Conclusions Problem Set Application Studies Introduction 246

7 7.2 SOC Design Approach Application Study: AES AES: Algorithm and Requirements AES: Design and Evaluation Application Study: 3-D Graphics Processors Analysis: Processing Analysis: Interconnection Prototyping Application Study: Image Compression JPEG Compression Example JPEG System for Digital Still Camera Application Study: Video Compression MPEG and H.26X Video Compression: Requirements H.264 Acceleration: Designs Further Application Studies MP3 Audio Decoding Software-Defi ned Radio with Conclusions Problem Set What's Next: Challenges Ahead Introduction Overview Technology Powering the ASOC The Shape of the ASOC Computer Module and Memory RF or Light Communications Lasers RF Potential for Laser/RF Communications Networked ASOC Sensing 296

8 8.8.1 Visual Audio Motion, Flight, and the Fruit Fly Motivation Overview Pre-Deployment Post-Deployment Situation-Specifi c Optimization Autonomous Optimization Control Roadmap and Challenges Summary 312 Appendix: Tools for Processor Evaluation 313 References 316 Index 329 Ordering: Order Online - Order by Fax - using the form below Order by Post - print the order form below and send to Research and Markets, Guinness Centre, Taylors Lane, Dublin 8, Ireland.

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