Architectures and Design Methodologies for Micro and Nanocomputing

Transcription

1 Architectures and Design Methodologies for Micro and Nanocomputing PhD Poster Day, December 4, 2014 Matteo Bollo 1 (ID: 24367, I PhD Year) Tutor: Maurizio Zamboni 1 Collaborators: Mariagrazia Graziano 1, Marco Vacca 1, Giovanna Turvani 1 1 VLSI Group

2 Attended Classes Class Date CFU Parallel and distributed computing 04/07/ Tecniche avanzate per il progetto di sistemi 18/07/ elettronici ad alta affidabilità Microelectronic systems 08/09/ Software and Routing Technologies in Future 26/09/ Networks (didattica di eccellenza) Data mining: concetti e algoritmi 07/10/ Un metodo alternativo per l insegnamento 17/10/ della fisica Fondi competitivi per la ricerca: dall idea alla 06/11/ scrittura del progetto Nanocomputing: dispositivi, circuiti e architetture following 8 Architectures for Nanocomputing 2 / 15

3 Research Context and Motivation Most of data elaboration circuits are implemented over CMOS. The high integration level rises many problems in terms of Power Consumption (Leakage and Switching activity currents). Current flowing from VDD to ground generates Side-Channel signals. Side-Channel contains sensible information on the data elaborated and it is an hard issue for cryptography applications. REDUCING POWER AND INCREASING SIDE-CHANNEL ENTROPY with a change of paradigm in technology: is it a solution? Architectures for Nanocomputing 3 / 15

4 Research Context and Motivation Magnetic Tunnel Junction Devices are: Created as Memory cell in MRAM and reused as Logic Device. Three possible states 0, 1 and RESET are representable, the state could be forced through: External magnetic field. Forcing current in Bit Line and Source Line Each MTJ could be isolated lowering the corresponding Word Line to 0. The power consumption does not depend on the data computed it is constant. Architectures for Nanocomputing 4 / 15

5 Magnetic Tunnel Junction use Magnetic Tunnel Junction are very suitable for crossbar (matrix) structure. Architectures for Nanocomputing 5 / 15

6 Is it possible to make a logic simulation of MTJ? Implementing this FSM model in VHDL we are able to simulate the Magnetic Tunnel Junction logic behaviour. Architectures for Nanocomputing 6 / 15

7 Addressed research questions/problems Starting from the single device model, is it possible to make a logic simulation of MTJ circuits? Architectures for Nanocomputing 7 / 15

8 Novel Contributions Development of a design tool and simulation environment with: The capability to integrate a very large number of Nano devices in short time: We have implemented the 4-bit ripple carry adder, the 4-bit multiplier and the Multiplier and Accumulator in two different layouts. We assembly thousands of MTJ in rapid and clever way. The capability to simulate circuits composed of very large number of Nano devices avoiding the use of Magnetic Simulators: We simulate the whole multiplier in a few minutes. We are able to change the simulation model in order to have different levels of accuracy. Architectures for Nanocomputing 8 / 15

9 Assembly MTJ circuit in automatic way NANOcom is a Perl module that generates a VHDL crossbar circuit at Physical Level, taking in input: The physical level layout of the circuit (represented as matrix structure). The libraries describing: The crossbar VHDL component. The Nanotechnology devices to map in the crossbar. Return in output one VHDL file containing: The VHDL representation of the Crossbar structure (called Matrix). The VHDL configuration that bind the library component to the Matrix Cell. Architectures for Nanocomputing 9 / 15

10 Adopted Methodology Starting from a RT or Gate level circuit description, we can derive the MTJ implementation as follows: 1 Circuit decomposition in simple structures: AND, OR, NOT, MV, WIRE. 2 Crossbar layout type definition (Bound or Free MTJ clock zone definition) 3 Architectural Layout definition (placing input, output and inteconnnection). 4 Definition of consequent clock zone (Coloring, if not possible go to 2). 5 Simulation parameters measurements (Number of MTJ, circuit area, Latency...) Architectures for Nanocomputing 10 / 15

11 MTJ Structures definition 1 Define the ternary operator of Majority Voting (Low Effort in this technology) 2 Implement the basic AND/OR gates on the MV structure. 3 Define the behaviour of interconnection structures (MTJ Wires are intrinsecally pipelined). 3 Define a syncronization model using wl, bl and sl (MTJ Clock) Figure: AND, OR, NOT and WIREs Architectures for Nanocomputing 11 / 15

12 4 bit Multiplier - Layout Definition AREA: 54 rows 157 columns MTJs Number: 2217 MTJ % Occupied Area: 26.15% LATENCY: 17 MTJ clock cycle Architectures for Nanocomputing 12 / 15

13 Simulation SetUp 1 Generate simulation files with NANOcom. 2 Bind with the MTJ clocks generators. 3 Join with the MTJ components library. 4 Generate the stimuli and run the simulation. Architectures for Nanocomputing 13 / 15

14 Papers Published: "Composite Fields against Side Channel Analysisfor the Advanced Encryption Standard", Bollo, M., Maistri, P. (2014, December) accepted at 21st IEEE International Conference on Electronics Circuits & Systems (ICECS), "Physical Design and Testing of Nano Magnetic Architectures", Turvani, G., Tohti, A., Bollo, M., Riente, F., Vacca, M., Graziano, M., Zamboni, M. (2014, May). Design & Technology of Integrated Systems In Nanoscale Era (DTIS), th IEEE International Conference On (pp. 1-6). IEEE. Architectures for Nanocomputing 14 / 15

15 Future Work Design and simulate a fully architectures for Advance Encryption Standard computation based on MTJ model. Study and design new nanoelectronic device models. Improve and generalize the NANOcom Module in order to obtain different technology layouts. Study and test the benefit of nanocomputing in Crypyographyc Accelerators. Architectures for Nanocomputing 15 / 15