The Designer's Guide to VHDL

Transcription

1 The Designer's Guide to VHDL Third Edition Peter J. Ashenden EDA CONSULTANT, ASHENDEN DESIGNS PTY. LTD. ADJUNCT ASSOCIATE PROFESSOR, ADELAIDE UNIVERSITY AMSTERDAM BOSTON HEIDELBERG LONDON m^^ yj 1 ' NEW YORK OXFORD PARIS SAN DIEGO I^fl K"% SAN FRANCISCO SINGAPORE SYDNEY TOKYO Morgan Kaufmann Publishers is an imprint of Elsevier MORGAN KAUFMANN PUBLISHERS

2 Contents Preface xvii 1 Fundamental Concepts Modeling Digital Systems Domains and Levels of Modeling Modeling Example Modeling Languages VHDL Modeling Concepts Elements of Behavior Elements of Structure Mixed Structural and Behavioral Models Test Benches Analysis, Elaboration and Execution Learning a New Language: Lexical Elements and Syntax Lexical Elements 17 Comments 17 Identifiers 19 Reserved Words 20 Special Symbols 22 Numbers 22 Characters 23 Strings 23 Bit Strings Syntax Descriptions 26 Exercises 29 2 Scalar Data Types and Operations Constants and Variables Constant and Variable Declarations Variable Assignment Scalar Types Type Declarations Integer Types Floating-Point Types Physical Types 39 Time Enumeration Types 43 Characters 44 Booleans 46 vii

3 vm Contents Bits 47 Standard Logic 48 Condition Conversion Type Classification Subtypes Type Qualification Type Conversion Attributes of Scalar Types Expressions and Predefined Operations 57 Exercises 62 Sequential Statements If Statements Conditional Variable Assignments Case Statements Selected Variable Assignments Null Statements Loop Statements Exit Statements Next Statements While Loops For Loops Summary of Loop Statements Assertion and Report Statements 87 Exercises 93 Composite Data Types and Operations Arrays Multidimensional Arrays Array Aggregates Array Attributes Unconstrained Array Types Predefined Array Types 106 Strings 106 Boolean Vectors, Integer Vectors, Real Vectors, and Time Vectors 106 Bit Vectors 107 Standard-Logic Arrays 108 String and Bit-String Literais Unconstrained Array Element Types Unconstrained Array Ports Array Operations and Referencing Logical Operators Shift Operators Relational Operators 117 Maximum and Minimum Operations The Concatenation Operator To_String Operations 120

4 Contents ix Array Slices Array Type Conversions Arrays in Case Statements Matching Case Statements 125 Matching Selected Variable Assignments Records Record Aggregates Unconstrained Record Element Types 131 Exercises 134 Basic Modeimg Constructs Entity Declarations and Architecture Bodies Concurrent Statements Signal Declarations Behavioral Descriptions Signal Assignment 143 Conditional Signal Assignments 146 Selected Signal Assignments Signal Attributes Wait Statements Delta Delays Transport and Inertial Delay Mechanisms Process Statements Concurrent Signal Assignment Statements 166 Concurrent Simple Signal Assignments 166 Concurrent Conditional Signal Assignment 167 Concurrent Selected Signal Assignments Concurrent Assertion Statements Entities and Passive Processes Structural Descriptions Design Processing Analysis Design Libraries and Contexts 188 Context Declarations Elaboration Execution 195 Exercises 197 Subprograms Procedures Return Statement in a Procedure Procedure Parameters Signal Parameters Default Values Unconstrained Array Parameters Summary of Procedure Parameters Concurrent Procedure Call Statements 225

5 X Contents 6.4 Functions Functional Modeling Pure and Impure Functions The Function now Overloading Overloading Operator Symbols Visibility of Declarations 236 Exercises Packages and Use Clauses Package Declarations Subprograms in Package Declarations Constants in Package Declarations Package Bodies Local Packages Use Clauses Visibility of Used Declarations 261 Exercises Resolved Signals Basic Resolved Signals Composite Resolved Subtypes Summary of Resolved Subtypes IEEE StdJogicJ 1 64 Resolved Subtypes Resolved Signals, Ports, and Parameters Resolved Ports Driving Value Attribute Resolved Signal Parameters 286 Exercises Predefined and Standard Packages The Predefined Packages Standard and env IEEE Standard Packages Standard VHDL Mathematical Packages 296 Real Number Mathematical Package 296 Complex Number Mathematical Package The StdJogicJ 1 64 Multivalue Logic System Standard Integer Numeric Packages Standard Fixed-Point Packages Standard Floating-Point Packages Package Summary 322 Operator Overloading Summary 323 Conversion Function Summary 326 Strength Reduction Function Summary 334 Exercises 335

6 Contents XI 10 Case Study: A Pipelined Multiplier Accumulator Algorithm Outline A Behavioral Model Testing the Behavioral Model A Register-Transfer-Level Model Testing the Register-Transfer-Level Model 350 Exercises Aliases Aliases for Data Objects Aliases for Non-Data Items 360 Exercises Generics Generic Constants Generic Types Generic Lists in Packages Local Packages Abstract Data Types Using Packages Generic Lists in Subprograms Generic Subprograms Generic Packages 407 Exercises Components and Conflgurations Components Component Declarations Component Instantiation Packaging Components Configuring Component Instances Basic Configuration Declarations Configuring Multiple Levels of Hierarchy Direct Instantiation of Configured Entities Generic and Port Maps in Configurations Deferred Component Binding Configuration Specifications Incremental Binding 438 Exercises Generate Statements Generating Iterative Structures Conditionally Generating Structures Recursive Structures Configuration of Generate Statements 465 Exercises 473

7 XU Contents 15 Access Types Access Types Access Type Declarations and Allocators Assignment and Equality of Access Values Access Types for Records and Arrays Linked Data Structures Deallocation and Storage Management An Ordered-Dictionary ADT Using Access Types 491 Exercises Files and Input/Output Files File Declarations Reading from Files Writing to Files Files Declared in Subprograms Explicit Open and Close Operations File Parameters in Subprograms Portability of Files The Package Textio Textio Read Operations Textio Write Operations Reading and Writing Other Types 527 Standard Package Read and Write Operations 528 Exercises Case Study: A Package for Memories The Memories Package Using the Memories Package Common Address and Data Conversions 551 Exercises Test Bench and Verification Features External Names Force and Release Assignments Embedded PSL in VHDL 575 Exercises Shared Variables and Protected Types Shared Variables and Mutual Exclusion Uninstantiated Methods in Protected Types 597 Exercises Attributes and Groups Predefined Attributes Attributes of Scalar Types 603

8 Attributes of Array Types and Objects Attributes Giving Types Attributes of Signals Attributes of Named Items User-Defined Attributes 6l Attribute Declarations 6l Attribute Specifications 6l Groups 628 Exercises 630 Design for Synthesis 21.1 Synthesizable Subsets Use of Data Types Scalar Types Composite and Other Types Interpretation of Standard Logic Values Modeling Combinational Logic Modeling Sequential Logic Modeling Edge-Triggered Logic Level-Sensitive Logic and Inferring Storage Modeling State Machines Modeling Memories Synthesis Attributes Metacomments 666 Exercises 667 Case Study: System Design Using the Gumnut Core 22.1 Overview of the Gumnut Instruction Set Architecture External Interface 674 The Gumnut Entity Declaration 676 Instruction and Data Memories A Behavioral Model The Gumnut Definitions Package The Gumnut Behavioral Architecture Body 687 Overview oftbe Interpreter 690 Resetting the Interpreter 691 Acknowledging an Interrupt 691 Fetching an Instruction 692 Performing an Arithmetic/Logical Operation 693 Performing a Shift Operation 694 Performing a Memory-I/O Instruction 695 Performing a Branch Instruction 697 Performing a Jump Instruction 697 Performing a Miscellaneous Instruction Verifying the Behavioral Model A Register-Transfer-Level Model 704

9 XIV Contents The Architecture Body Verifying the RTL Model A Digital Alarm Clock System Design Synthesizing and Implementing the Alarm Clock 729 Exercises Miscellaneous Topics Guards and Blocks Guarded Signals and Disconnection 733 The Driving Attribute 73 7 Guarded Ports 738 Guarded Signal Parameters Blocks and Guarded Signal Assignment 739 Explicit Guard Signals 742 Disconnection Specifications Using Blocks for Structural Modularity 744 External Names and Blocks 74 7 Generics and Ports in Blocks 748 Configuring Designs with Blocks IP Encryption Key Exchange VHDL Procedural Interface (VHPI) Direct Binding Tabular Registration and Indirect Binding Registration of Applications and Libraries Postponed Processes Conversion Functions in Association Lists Linkage Ports 785 Exercises 786 A Standard Packages 793 A.l The Predefined Package Standard 793 A.2 The Predefined Package env 797 A.3 The Predefined Package textio 797 A.4 Standard VHDL Mathematical Packages 799 A.4.1 The math_real Package 799 A.4.2 The math_complex Package 801 A.5 The stdjoqjcj 1 64 Multivalue Logic System Package 802 A.6 Standard Integer Numeric Packages 806 A.6.1 The numeric_bit Package 806 A.6.2 The numeric_std Package 812 A.6.3 The numeric_bit_unsigned Package 813 A.6.4 The numeric_std_unsigned Package 815 A.7 Standard Fixed-Point Packages 816 A.7.1 The fixed_float_types Package 816 A.7.2 The fixed_generic_pkg Package 816

10 Contents xv A.7.3 The fixed_pkg Package 829 A.8 Standard Floating-Point Packages 829 A.8.1 The float_generic_pkg Package 829 A.8.2 The float_pkg Package 840 B VHDL Syntax 841 B.l Design File 843 B.2 Library Unit Declarations 843 B.3 Declarations and Specifications 845 B.4 Type Definitions 848 B.5 Concurrent Statements 850 B.6 Sequential Statements 852 B.7 Interfaces and Associations 855 B.8 Expressions and Names 856 C Answers to Exercises 859 References 889 Index 891