The enable pin needs to be high for data to be fed to the outputs Q and Q bar.

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1 of 7 -Type flip-flop (Toggle switch) The -type flip-flops are used in prescalar/divider circuits and frequency phase detectors. Figure shows how the flip-flop (latch) can be made using -input logic circuits and Figure shows the input and output waveforms The enable pin needs to be high for data to be fed to the outputs and bar. The output will only change on the falling edge or trailing edge of the applied clk input. Enable Latch Figure Simple -type Flip-flop circuit The type flip-flop has only one input ( for ata) apart from the clock. The INETERMINTE state is avoided with this flip-flop. When the clock goes high, (a or a ) is transferred to. When the clock goes low, remains unchanged. stores the data until the clock goes high again, when new data may be available. Figure Output waveforms of the -type flip-flop. In this circuit the output changes state on the leading edge of the clock.

2 of 7 t, clock and data are high. goes high and stays high until. t, clock is high and data is low. goes low and stays low until C. t C, clock and data are both high. goes high and stays high until E. does not change during clock pulse, because clock and data are still both high. t E, data is low, so goes low. t F, data is high so goes high. s with the other flip-flop circuits the operation can be improved to eliminate indeterminate states by adding a master latch. The circuit of the master-slave -type flip-flop is shown in the S simulation setup shown in Figure. The inverter connected between the two CLK inputs ensures that the two sections will be enabled during opposite half-cycles of the clock signal. Each logic gate is made up of CMOS FETS (based on the.8um process) as described in the other tutorials on individual gates.

3 of 7 T tpulset SRC low= high= elay= usec Width= usec Period= usec Rout= Ohm T tpulset SRC low= high= elay= nsec Width= usec Period= usec Rout= Ohm _C SRC dc=. Num= Num= cc cc _ X8 _ X9 cc cc cc _ X7 _ X _ X cc cc _ X TRNSIENT cc _ X cc _ X Num= _bar _bar Num= IN X Tran Tran StopTime= usec MaxTimeStep= Figure S simulation setup of the master-slave -type flip-flop circuit. In this simaulation there are two square wave generators, the clock at KHz and the data (with a us delay) running at KHz. The simulation is a time-domain transient.

4 of 7 The resulting simulation of the circuit shown in Figure is shown in Figure. -type Flip-flop transitions occur on the falling of the input, 8, 8, 8 Figure Simulation of the Master-slave -type flip-flop. Note that the transitions occur on the falling edge of the applied clock signal+/ half clock cycle due to the slave action.

5 of 7 The -type flip-flop can be configured as a T-type or Toggle flip-flop. With this configuration the _bar output is connected to the input and the signal/clock is connected to the clk input. The output of this flip-flop will have a frequency half that of the input. The S simulation of Figure is shown below (Figure ) -type Flip-flop transitions occur on the falling of the input. This -type is configured as a T-type toggle flip-flop, 8, 8 Figure Simulation results of the -type flip-flop configured as a T-type (Toggle) flipflop by connecting the input to the _bar output. Such circuits are common in frequency prescalar circuits.

6 of 7 Num= _C SRC dc=. cc cc _ X8 _ X9 IN cc X _ X7 _ X cc cc _ X cc cc _ X TRNSIENT Tran Tran StopTime= usec MaxTimeStep= nsec cc _ X cc _ X T Num= tpulset SRC low= high= elay= nsec Width= usec Period= usec Rout= Ohm Figure Transient S simulation of a -type Flip-Flop configured as a T-type flip-flop by connecting the input to the _bar output.

7 7 of 7 RF pplication Phase detectors are part of a Phase Locked Loop (PLL) and can be either analogue eg mixer or digital eg -type flip-flop. When a mixer is used the output consists of the sum and difference frequencies. In an analogue mixer a number of different frequencies are generated within the mixer namely the sum of the frequencies and the difference frequency (otherwise known as the beatnote) when both input frequencies are the same is the phase difference is zero and the beatnote is C. Most PLL circuits now use digital phase detectors formed from two -type flip-flops as shown in Figure 7. high F type Flip-Flop high Clear F type Flip-Flop Figure 7 -type flip-flop application - Phase frequency phase detector

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