INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic Package Outlines 74C/CT bit bidirectional universal shift register; File under Integrated Circuits, IC06 December 1990

2 4-bit bidirectional universal shift register; 74C/CT40104 FEATURES Synchronous parallel or serial operating outputs Output capability: bus driver I CC category: MSI GENERA DESCRIPTION The 74C/CT40104 are high-speed Si-gate CMOS devices and are pin compatible with the of the 4000B series. They are specified in compliance with JEDEC standard no. 7A. The 74C/CT40104 are universal shift registers featuring parallel inputs, parallel outputs, shift-right and shift-left serial inputs and outputs allowing the devices to be used in bus-organized systems. QUICK REFERENCE DATA GND = 0 V; T amb =5 C; t r =t f = 6 ns In the parallel-load mode (S 0 and S 1 are IG), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During loading, serial data flow is inhibited. Shift-right and shift-left are accomplished synchronously on the positive clock edge with serial data entered at the shift-right (D SR ) and shift-left (D S ) serial inputs, respectively. Clearing the register is accomplished by setting both mode controls (S 0 and S 1 ) OW and clocking the register. When the output enable input (OE) is OW, all outputs assume the high-impedance OFF-state (Z). APPICATIONS Arithmetic unit bus registers Serial/parallel conversion General-purpose register for bus organized systems General-purpose registers TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P propagation delay CP to Q n C = 15 pf; V CC = 5 V ns f max maximum clock frequency 6 57 Mz C I input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V CC f i + (C V CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December 1990

3 74C/CT40104 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1 OE output enable input (active IG) D SR serial data shift-right input 3, 4, 5, 6 D 0 to D 3 parallel data inputs 7 D S serial data shift-left input 8 GND ground (0 V) 9, 10 S 0, S 1 mode control inputs 11 CP clock input (OW-to-IG, edge-triggered) 15, 14, 13, 1 Q 0 to Q 3 parallel outputs 16 V CC positive supply voltage Fig.1 Pin configuration. Fig. ogic symbol. Fig.3 IEC logic symbol. December

4 74C/CT40104 FUNCTION TABE OPE- RATING MODES INPUTS (OE = IG) OUTPUTS at t n+1 S 1 S 0 D SR D S D 0 to D 3 Q 0 Q 1 Q Q 3 reset shift left shift right parallel load Notes 1. = IG voltage level = OW voltage level = don t care t n+1 = state after next OW-to-IG transition of CP Q 1 Q Q 3 Q 1 Q Q 3 Q 0 Q 1 Q Q 0 Q 1 Q Fig.4 Functional diagram. Fig.5 ogic diagram. December

5 74C/CT40104 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI AC CARACTERISTICS FOR 74C GND = 0 V; t r =t f = 6 ns; C = 50 pf SYMBO t P / t P t PZ / t PZ t PZ / t PZ PARAMETER propagation delay 44 CP to Q n output enable time 33 OE to Q n 1 10 output disable time 50 OE to Q n t T / t T output transition time t W t su t su t h t h f max clock pulse width IG or OW set-up time D n, D SR, D S to CP set-up time S 0, S 1 to CP hold time D n, D SR, D S to CP hold time S 0, S 1 to CP maximum clock pulse frequency T amb ( C) 74C to to +15 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) ns.0 ns.0 ns.0 ns.0 ns.0 ns.0 ns.0 ns.0 ns.0 Mz.0 WAVEFORMS December

6 74C/CT40104 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D 0 to D 3 D SR, D S CP S 0, S 1 OE UNIT OAD COEFFICIENT AC CARACTERISTICS FOR 74CT GND = 0 V; t r =t f = 6 ns; C = 50 pf T amb ( C) TEST CONDITIONS ns ns ns 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +15 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay CP to Q n t PZ / t PZ output enable time OE to Q n t PZ / t PZ output disable time OE to Q n t T / t T output transition time ns t W t su t su t h t h f max clock pulse width IG or OW set-up time D n, D SR, D S to CP set-up time S 0, S 1 to CP hold time D n, D SR, D S to CP hold time S 0, S 1 to CP maximum clock pulse frequency ns ns ns ns 5 ns Mz December

7 74C/CT40104 AC WAVEFORMS (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Waveforms showing the clock (CP) to output (Q n ) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the enable and disable times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Waveforms showing the set-up and hold times from the D n, D SR, D S and S n inputs to the clock (CP). December

8 74C/CT40104 PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December

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