Software-Programmable FPGA IoT Platform. Kam Chuen Mak (Lattice Semiconductor) Andrew Canis (LegUp Computing) July 13, 2016
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1 Software-Programmable FPGA IoT Platform Kam Chuen Mak (Lattice Semiconductor) Andrew Canis (LegUp Computing) July 13, 2016
2 Agenda Introduction Who we are IoT Platform in FPGA Lattice s IoT Vision IoT Platform Overview Architecture Overview RISC-V Architecture RISC-V Processor Overview LegUp High-Level Synthesis Design Flow Benchmark Results Page: 2
3 Agenda Introduction Who we are IoT Platform in FPGA Lattice s IoT Vision IoT Platform Overview Architecture Overview RISC-V Architecture RISC-V Processor Overview LegUp High-Level Synthesis Design Flow Benchmark Results Page: 3
4 INTRODUCTION Who we are? Lattice Semiconductor (NASDAQ: LSCC) We provide smart connectivity solutions powered by our low power FPGA, video ASSP, 60 GHz millimeter wave, and IP products to the consumer, communications, industrial, computing, and automotive markets worldwide. Our unwavering commitment to our customers enables them to accelerate their innovation, creating an ever better and more connected world. Page: 4
5 INTRODUCTION Who we are? Lattice Semiconductor (NASDAQ: LSCC) We provide smart connectivity solutions powered by our low power FPGA, video ASSP, 60 GHz millimeter wave, and IP products to the consumer, communications, industrial, computing, and automotive markets worldwide. Our unwavering commitment to our customers enables them to accelerate their innovation, creating an ever better and more connected world. LegUp Computing (LegUpComputing.com) We are a startup spun out of 7 years of research at the University of Toronto. We provide high-level synthesis tools that compile software into hardware running on an FPGA. Our product enables software engineers to easily target FPGA hardware to achieve huge gains in computational throughput and energy efficiency. Page: 5
6 Agenda Introduction Who we are IoT Platform in FPGA Lattice s IoT Vision IoT Platform Overview Architecture Overview RISC-V Architecture RISC-V Processor Overview LegUp High-Level Synthesis Design Flow Benchmark Results Page: 6
7 IOT PLATFORM IN FPGA Lattice s Vision Lattice s vision for an FPGA IoT platform: Page: 7
8 IOT PLATFORM IN FPGA Lattice s Vision Lattice s vision for an FPGA IoT platform: 1) Ease of use Use C/C++ as our design entry for customers. Users can even create hardware accelerators using C No More Verilog or VHDL Page: 8
9 IOT PLATFORM IN FPGA Lattice s Vision Lattice s vision for an FPGA IoT platform: 1) Ease of use Use C/C++ as our design entry for customers. Users can even create hardware accelerators using C No More Verilog or VHDL We use a RISC-V with LegUp accelerators to fulfil this requirement Page: 9
10 IOT PLATFORM IN FPGA Lattice s Vision Lattice s vision for an FPGA IoT platform: 1) Ease of use Use C/C++ as our design entry for customers. Users can even create hardware accelerators using C No More Verilog or VHDL We use a RISC-V with LegUp accelerators to fulfil this requirement 2) Flexibility Support a wide range of sensors, actuators, and communication devices APIs Capability to generate custom instructions or acceleration libraries if they are required for the user application Page: 10
11 IOT PLATFORM IN FPGA Lattice s Vision Lattice s vision for an FPGA IoT platform: 1) Ease of use Use C/C++ as our design entry for customers. Users can even create hardware accelerators using C No More Verilog or VHDL We use a RISC-V with LegUp accelerators to fulfil this requirement 2) Flexibility Support a wide range of sensors, actuators, and communication devices APIs Capability to generate custom instructions or acceleration libraries if they are required for the user application We can use a FPGA to fulfil this requirement Page: 11
12 IOT PLATFORM IN FPGA Lattice s Vision Lattice s vision for an FPGA IoT platform: 1) Ease of use Use C/C++ as our design entry for customers. Users can even create hardware accelerators using C No More Verilog or VHDL We use a RISC-V with LegUp accelerators to fulfil this requirement 2) Flexibility Support a wide range of sensors, actuators, and communication devices APIs Capability to generate custom instructions or acceleration libraries if they are required for the user application We can use a FPGA to fulfil this requirement A hybrid computing solution: Combine the RISC-V Processor with FPGA hardware and utilize our low power and small footprint FPGA advantages for user customization. Page: 12
13 IOT PLATFORM IN FPGA Lattice s Vision A Hybrid (Processor + FPGA) platform Cost Performance Page: 13
14 IOT PLATFORM IN FPGA Lattice s Vision A Hybrid (Processor + FPGA) platform Cost Data center / Cloud Computing Page: 14 Performance
15 IOT PLATFORM IN FPGA Lattice s Vision A Hybrid (Processor + FPGA) platform Cost Embedded, mobile, Internet-of-Things Data center / Cloud Computing Performance Page: 15
16 IOT PLATFORM IN FPGA IoT Platform Overview Sensing Processing Communication Page: 16
17 IOT PLATFORM IN FPGA IoT Platform Overview Sensing Processing Communication The Internet of Things (IoT) refers to the ever-growing network of physical objects that feature an IP address for internet connectivity, and the communication that occurs between these objects and other Internetenabled devices and systems. (From Webopedia) Page: 17
18 IOT PLATFORM IN FPGA IoT Platform Overview Sensing Accelerometer Gyroscope Pressure Temperature Processing Encryption Digital signal processing Security Data filtering Communication Wi-Fi Bluetooth I2C SPI Page: 18
19 IOT PLATFORM IN FPGA IoT Platform Overview Sensing Accelerometer Gyroscope Pressure Temperature Software description of the sensor component Lattice IoT Platform provides APIs for sensors/actuators Processing Encryption Digital signal processing Security Data filtering FPGA RISCV Processor Hardware Accelerator Communication Wi-Fi Bluetooth I2C SPI Software description of the communication device Lattice IoT platform provides APIs for communication devices Page: 19
20 IOT PLATFORM IN FPGA Architecture Overview Processing Encryption Digital Signal Processing Security Data Filtering FPGA RISCV Processor Hardware Accelerator Page: 20
21 IOT PLATFORM IN FPGA Architecture Overview Processing Encryption Digital Signal Processing Security Data Filtering FPGA RISCV Processor Hardware Accelerator RISC-V processor plus LegUp-generated hardware accelerators to handle the processing part of the IoT Platform: Low-power and small footprint solution Identify the critical hotspots in C program, use LegUp to synthesize them into the FPGA and speed up the overall performance RISC-V processor executes the rest of the C program Maintain a low power and gain high throughput Page: 21
22 Agenda Introduction Who we are IoT Platform in FPGA Lattice s IoT Vision IoT Platform Overview Architecture Overview RISC-V Architecture RISC-V Processor Overview LegUp High-Level Synthesis Design Flow Benchmark Results Page: 22
23 IOT PLATFORM IN FPGA Architecture Overview RISC-V + LegUp-generated accelerators RISCV LegUp-generated Accelerator LegUp-generated Accelerator master master BUS INTERFACE...master slave slave slave slave Instruction Memory Processor Data Memory Share Data Memory Accelerator Memory Page: 23
24 RISC-V ARCHITECTURE RISC-V Processor Overview PC GEN INST MEM (R) Decoder REG FILE (R) ALU CSR FILE (R) DATA MEM CSR FILE (W) REG FILE (W) Page: 24
25 RISC-V ARCHITECTURE RISC-V Processor Overview PC GEN INST MEM (R) Decoder REG FILE (R) ALU CSR FILE (R) DATA MEM CSR FILE (W) REG FILE (W) Lattice RISC-V Processor: 4 stages pipeline CPU Core Page: 25
26 RISC-V ARCHITECTURE RISC-V Processor Overview PC GEN INST MEM (R) Decoder REG FILE (R) ALU CSR FILE (R) DATA MEM CSR FILE (W) REG FILE (W) Lattice RISC-V Processor: 4 stages pipeline CPU Core RISC-V RV32IMC Instruction Set RV32I v2.0 RV32M v2.0 with Multiplier Only RV32C v1.9 Page: 26
27 RISC-V ARCHITECTURE RISC-V Processor Overview PC GEN INST MEM (R) Decoder REG FILE (R) ALU CSR FILE (R) DATA MEM CSR FILE (W) REG FILE (W) Lattice RISC-V Processor: 4 stages pipeline CPU Core RISC-V RV32IMC Instruction Set RV32I v2.0 RV32M v2.0 with Multiplier Only RV32C v1.9 Other optional features which can be configured through the Verilog parameters, i.e. Enable external interrupt, allow external stalls from accelerators, and use custom instructions Page: 27
28 RISC-V ARCHITECTURE RISC-V Processor Overview RV32I RV32IM RV32IC LM32 LM32(M) NIOS 2e* NIOS 2f* EM4* 8051* DMIPS Area 1.3K LUTs 1.5K LUTs +DSP ~1.6K LUTs 2K LUTs 2.5K LUTs 1.4K LEs 3K LEs N/A N/A Code Density** *Data from the third party vendor datasheet **Benchmark using Lattice internal designs Page: 28
29 Agenda Introduction Who we are IoT Platform in FPGA Lattice s IoT Vision IoT Platform Overview Architecture Overview RISC-V Architecture RISC-V Processor Overview LegUp High-Level Synthesis Design Flow Benchmark Results Page: 29
30 LEGUP HIGH-LEVEL SYNTHESIS Software (C code) Hardware Description (Verilog) Page: 30
31 BENEFITS OF LEGUP Harness parallelism of hardware Design in C (#1 embedded language) Many engineers don t know Verilog Finish in weeks instead of months Faster time to market C testbench 100X faster than simulation Allows design space exploration Easier debugging in C IEEE Spectrum 2015 Page: 31
32 LEGUP DESIGN FLOW int FIR(int ntaps, int sum) { int i; for (i=0; i < ntaps; i++) sum += h[i] * z[i]; return (sum);... Program code C Compiler RISC-V Page: 32
33 LEGUP DESIGN FLOW int FIR(int ntaps, int sum) { int i; for (i=0; i < ntaps; i++) sum += h[i] * z[i]; return (sum);... Program code C Compiler Profiling RISC-V Page: 33
34 LEGUP DESIGN FLOW int FIR(int ntaps, int sum) { int i; for (i=0; i < ntaps; i++) sum += h[i] * z[i]; return (sum);... Program code C Compiler Profiling RISC-V Profiling Data: Execution Cycles Power Page: 34
35 LEGUP DESIGN FLOW int FIR(int ntaps, int sum) { int i; for (i=0; i < ntaps; i++) sum += h[i] * z[i]; return (sum);... Program code C Compiler Profiling RISC-V Profiling Data: Suggested program segments to target to HW Execution Cycles Power Page: 35
36 LEGUP DESIGN FLOW int FIR(int ntaps, int sum) { int i; for (i=0; i < ntaps; i++) sum += h[i] * z[i]; return (sum);... Program code C Compiler Profiling RISC-V Profiling Data: High-level synthesis Suggested program segments to target to HW Execution Cycles Power Page: 36
37 LEGUP DESIGN FLOW int FIR(int ntaps, int sum) { int i; for (i=0; i < ntaps; i++) sum += h[i] * z[i]; return (sum);... C Compiler Profiling RISC-V Program code Altered SW binary (calls HW accelerators) Profiling Data: µp Hardened program segments FPGA fabric High-level synthesis Suggested program segments to target to HW Execution Cycles Power Page: 37
![LEGUP DESIGN FLOW int FIR(int ntaps, int sum) { int i; for (i=0; i < ntaps; i++) sum += h[i] * z[i]; return (sum);.](/docs-images/40/21626688/images/38-0.png ".. C Compiler Profiling RISC-V Program code Altered SW binary (calls HW accelerators) Profiling Data: µp Hardened program segments FPGA fabric High-level synthesis Suggested")
38 LEGUP DESIGN FLOW int FIR(int ntaps, int sum) { int i; for (i=0; i < ntaps; i++) sum += h[i] * z[i]; return (sum);... C Compiler Profiling RISC-V Program code Altered SW binary (calls HW accelerators) Profiling Data: µp Hardened program segments FPGA fabric High-level synthesis Suggested program segments to target to HW Execution Cycles Power Page: 38
39 LEGUP DESIGN FLOW int main () { sum = dotproduct(a, b, n);... int dotproduct(int *A, int *B, int N) { for (i=0; i<n; i++) { sum += A[i] * B[i]; return sum; Page: 39
40 LEGUP DESIGN FLOW int main () { sum = dotproduct(a, b, n);... We want to accelerate this C function in hardware int dotproduct(int *A, int *B, int N) { for (i=0; i<n; i++) { sum += A[i] * B[i]; return sum; Page: 40
41 LEGUP DESIGN FLOW int main () { sum = dotproduct(a, b, n);... Specify We want LegUp to accelerate Tcl command: this C set_accelerator_function function in hardware dotproduct int dotproduct(int *A, int *B, int N) { for (i=0; i<n; i++) { sum += A[i] * B[i]; return sum; Page: 41
42 LEGUP DESIGN FLOW int main () { sum = dotproduct(a, b, n);... Specify We want LegUp to accelerate Tcl command: this C set_accelerator_function function in hardware dotproduct Now run LegUp! int dotproduct(int *A, int *B, int N) { for (i=0; i<n; i++) { sum += A[i] * B[i]; return sum; Page: 42
43 LEGUP DESIGN FLOW int main () { sum = dotproduct(a, b, n);... int dotproduct(int *A, int *B, int N) { for (i=0; i<n; i++) { sum += A[i] * B[i]; return sum; Page: 43
44 LEGUP DESIGN FLOW int main () { sum = dotproduct(a, b, n);... int dotproduct(int *A, int *B, int N) { for (i=0; i<n; i++) { sum LegUp += A[i] * B[i]; return sum; Page: 44
45 LEGUP DESIGN FLOW int main () { sum = dotproduct(a, b, n);... int dotproduct(int *A, int *B, int N) { for (i=0; i<n; i++) { sum LegUp += A[i] * B[i]; return sum; Verilog HW Accelerator Page: 45
46 LEGUP DESIGN FLOW int main () { sum = dotproduct(a, b, n);... #define dotproduct_ret (volatile int *) 0xf #define dotproduct_status (volatile int *) 0xf #define dotproduct_arg1 (volatile int *) 0xf000000C #define dotproduct_arg2 (volatile int *) 0xf #define dotproduct_arg3 (volatile int *) 0xf int legup_dotproduct(int *A, int *B, int N) { *dotproduct_arg1 = (volatile int) A; *dotproduct_arg2 = (volatile int) B; *dotproduct_arg3 = (volatile int) N; *dotproduct_status = 1; return *dotproduct_ret; Automatically created C wrapper to interface with hardware Page: 46
47 LEGUP DESIGN FLOW int main () { sum = dotproduct(a, b, n);... #define dotproduct_ret (volatile int *) 0xf #define dotproduct_status (volatile int *) 0xf #define dotproduct_arg1 (volatile int *) 0xf000000C #define dotproduct_arg2 (volatile int *) 0xf #define dotproduct_arg3 (volatile int *) 0xf int legup_dotproduct(int *A, int *B, int N) { *dotproduct_arg1 = (volatile int) A; *dotproduct_arg2 = (volatile int) B; *dotproduct_arg3 = (volatile int) N; *dotproduct_status = 1; return *dotproduct_ret; Page: 47
48 LEGUP DESIGN FLOW int main () {... sum = sum legup_dotproduct(a,b,n); = dotproduct(n);... Automatically replace function calls #define dotproduct_ret (volatile int *) 0xf #define dotproduct_status (volatile int *) 0xf #define dotproduct_arg1 (volatile int *) 0xf000000C #define dotproduct_arg2 (volatile int *) 0xf #define dotproduct_arg3 (volatile int *) 0xf int legup_dotproduct(int *A, int *B, int N) { *dotproduct_arg1 = (volatile int) A; *dotproduct_arg2 = (volatile int) B; *dotproduct_arg3 = (volatile int) N; *dotproduct_status = 1; return *dotproduct_ret; Page: 48
49 LEGUP DESIGN FLOW int main () {... sum = sum legup_dotproduct(a,b,n); = dotproduct(n);... Automatically replace function calls #define dotproduct_ret (volatile int *) 0xf #define dotproduct_status (volatile int *) 0xf #define dotproduct_arg1 (volatile int *) 0xf000000C #define dotproduct_arg2 (volatile int *) 0xf #define dotproduct_arg3 (volatile int *) 0xf int legup_dotproduct(int *A, int *B, int N) { *dotproduct_arg1 = (volatile int) A; *dotproduct_arg2 = (volatile int) B; *dotproduct_arg3 = (volatile int) N; *dotproduct_status = 1; return *dotproduct_ret; Page: 49
50 LEGUP DESIGN FLOW int main () { sum = legup_dotproduct(a,b,n); #define dotproduct_ret (volatile int *) 0xf #define dotproduct_status (volatile int *) 0xf #define dotproduct_arg1 (volatile int *) 0xf000000C #define dotproduct_arg2 (volatile int *) 0xf #define dotproduct_arg3 (volatile int *) 0xf int legup_dotproduct(int *A, int *B, int N) { *dotproduct_arg1 = (volatile int) A; *dotproduct_arg2 = (volatile int) B; *dotproduct_arg3 = (volatile int) N; *dotproduct_status = 1; return *dotproduct_ret; Page: 50
51 LEGUP DESIGN FLOW int main () { sum = legup_dotproduct(a,b,n);... Software Compiler #define dotproduct_ret (volatile int *) 0xf #define dotproduct_status (volatile int *) 0xf #define dotproduct_arg1 (volatile int *) 0xf000000C #define dotproduct_arg2 (volatile int *) 0xf #define dotproduct_arg3 (volatile int *) 0xf int legup_dotproduct(int *A, int *B, int N) { *dotproduct_arg1 = (volatile int) A; *dotproduct_arg2 = (volatile int) B; *dotproduct_arg3 = (volatile int) N; *dotproduct_status = 1; return *dotproduct_ret; Page: 51
52 LEGUP DESIGN FLOW int main () { sum = legup_dotproduct(a,b,n);... Software Compiler RISC-V Processor #define dotproduct_ret (volatile int *) 0xf #define dotproduct_status (volatile int *) 0xf #define dotproduct_arg1 (volatile int *) 0xf000000C #define dotproduct_arg2 (volatile int *) 0xf #define dotproduct_arg3 (volatile int *) 0xf int legup_dotproduct(int *A, int *B, int N) { *dotproduct_arg1 = (volatile int) A; *dotproduct_arg2 = (volatile int) B; *dotproduct_arg3 = (volatile int) N; *dotproduct_status = 1; return *dotproduct_ret; Page: 52
53 IOT PLATFORM IN FPGA Architecture Overview RISC-V + LegUp-generated accelerators RISCV master LegUp-generated dotproduct() master BUS INTERFACE slave Processor Data Memory slave Share Data Memory Page: 53
54 USER DESIGN FLOW C Input Program Profiling + Hardware/Software Partitioning User Tcl Configuration Iterative Design Process RISC-V Binary RISC-V Toolchain/LegUp RISC-V Processor Complete System Verilog Hardware Hardware Accelerator Hardware Accelerator Accelerator Lattice RTL Implementation Page: 54
55 CASE STUDY Energy is calculated as a sum of squares of speech samples: for (i = 0; i < 256; i++) energy += samples[i]*samples[i]; Running on RISC-V32IM (DMIPS 1.64): Each loop iteration takes about 6 cycles: load, increment address, multiply, add, branch Clock cycles to complete: 1550 LegUp synthesized accelerator: Generates a pipelined hardware circuit exploiting parallelism One iteration completes every clock cycle Clock cycles to complete: 288 Speedup: 5.4X Page: 55
56 Agenda Introduction Who we are IoT Platform in FPGA Lattice s IoT Vision IoT Platform Overview Architecture Overview RISC-V Architecture RISC-V Processor Overview LegUp High-Level Synthesis Design Flow Benchmark Results Page: 56
57 STREAMING BENCHMARKS Edge Detection: 4 image filters Bayer/deBayer Filter Beamforming FIR Filter Page: 57
58 STREAMING BENCHMARKS Aptina Image Sensor ECP3 FPGA Sensor In Controller Edge Detector Video Out Controller HDMI Input: 1 pixel/cycle Output: 1 pixel/cycle Verilog C Clock Frequency: 74 MHz 60 fps Page: 58
59 STREAMING BENCHMARKS Average across 9 benchmarks LegUp vs RTL: FMax within 30% and slices < 10% larger RTL LegUp/RTL Time (us) Cycles 38, FMax (MHz) Slices Registers LUT4s DSPs Metric: Time = cycles * clock period Time taken to complete the entire benchmark Page: 59
60 RISC-V+LEGUP BENCHMARKS Accelerate most-compute intensive function with LegUp Benchmark RISC-V clock cycles RISC-V + LegUp clock cycles Energy sum 1, OPUS function 48,947 16, FIR filter 44,610 13, Matrix multiply 67,823 28, ADPCM 88,288 20, AES 29,071 12, Blowfish 752, , GSM 17,092 6, Motion 13,193 4, SHA 726, , Geomean 48,542 16, Speedup Page: 60
61 IOT PLATFORM IN FPGA Architecture Overview RISC-V + LegUp-generated coprocessor connected to I/Os RISCV master LegUp-generated Accelerator master I/Os BUS INTERFACE slave Processor Data Memory slave Share Data Memory slave Accelerator Memory Page: 61
62 CUSTOM INSTRUCTIONS The current architecture assumes we want to accelerate a large chunk of code Instead the user may want to add a custom instruction i.e. multiply-accumulate for DSP applications LegUp can synthesize the hardware needed for the custom instruction Hardware accelerator is tightly coupled with RISC-V processor: can read/write registers Benefit: area efficient reuse of hardware many times Work in progress Page: 62
63 FPGA IOT PLATFORM THANK YOU ANY QUESTION? Page: 63
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