EE361: Digital Computer Organization Course Syllabus

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1 EE361: Digital Computer Organization Course Syllabus Dr. Mohammad H. Awedh Spring 2014 Course Objectives Simply, a computer is a set of components (Processor, Memory and Storage, Input/Output Devices) interconnected (by Bus) in such a way as to enable the execution of a program (set of instructions) stored in memory. This course introduces students to the basic concepts of computers, their design and how they work. It encompasses the denition of the machine's instruction set architecture, its use in creating a program, and its implementation in hardware. The course addresses the bridge between gate logic and executable software, and includes programming both in assembly language (representing software) and HDL (representing hardware). We will study modern computer principles using a typical processor and emphasize system-level issues, understanding process performance, and the use of abstraction as a tool to manage complexity. We then learn how ecient memory systems are designed to work closely with the processor. Next, we study input/output (I/O) systems which bring the processor and memory together with a wide range of devices. Finally, we introduce systems with many processors. Catalog Description Introduction to computer organization, machine instructions, addressing modes, assembly language programming, integer and oating-point arithmetic, CPU performance and metrics, non-pipelined and pipelined processor design, datapath and control unit, pipeline hazards, memory system and cache memory. Prerequisite: EE 305, EE 360, IE 331 ECE M. Awedh

2 Textbook Computer Organization & Design: The Hardware/Software Interface, Fourth Edition, Patterson and Hennessy, Morgan Kaufmann Publishers, Course Learning Outcomes Upon completion of the course, students should posses the following knowledge and skills: ˆ An understanding of a machine's instruction set architecture (ISA) including basic instruction fetch and execute cycles, instruction formats, control ow, and operand addressing modes. ˆ The ability to create, assemble, execute, and debug assembly language programs along with a basic understanding of the assembly, linker, and loader processes. ˆ An understanding of a hardware description language, HDL (e.g., either VHDL or verilog) including their uses, structural, and behavioral descriptions. ˆ The ability to create, simulate, and debug a VHDL or verilog program. ˆ An understanding of the design and functioning of a machines central processing unit (CPU) including the datapath components (ALU, register le) and the control unit. ˆ An understanding of basic input/output functioning including program controlled I/O and interrupt I/O. ˆ An understanding of organization of memory hierarchies including the basics of cache design and DRAM architectures. ˆ Analyze the performance of processors and caches ECE M. Awedh

3 Course Information Grading Instructor Dr. Mohammad H. Awedh King Abdulaziz University Oce Location Building 42B, Room 412 Oce Phone Oce Hours Sunday 12:30 to 1:30 or by Appointment Meeting Sunday, Tuesday 11:00 12:20 Building 79, Room 201A Tutorial Thursday 11:00 12:50 Building 79, Room 201A The course has two major exams and a nal exam, weekly homework assignments, labs and a project. Exams will be cumulative, but will focus on the most recent material. Your homework should reect your individual work. Grading will follow approximately the divisions shown below. Participation 5œ Assignments 10œ Lab work 15œ Project 15œ Major Exam I 15œ Major Exam II 15œ Final Exam 25œ ˆ Late assignments are accepted up to 2 days late, but will be penalized 5œfor each late day. ˆ No makeup will be made for missing labs or exams. ECE M. Awedh

4 Class Web Page We shall use Moodle for this class. Moodle is a Course Management System (CMS) which helps to communicate outside of the classroom. Students in this class should visit the site and create an account. This site contains information about the class - syllabus, homework list, due dates for assignments, links to other web sites, etc. In addition, we shall also use it for discussion and questions about the material covered in the course. For each course, students should register for that course on the moodle site. Registration is enabled by a key that will be given to students in class during the rst lecture. You have to notice that registration for the course does not automatically entail registration on the moodle site and vice versa. ECE M. Awedh

5 Lecture Breakdown Week Topics 1 Introduction to computer organization, high-level, assembly, and machine languages, components of a computer system, processor datapath, control, memory hierarchy, disk storage, technology improvements, chip manufacturing process 2 Review of signed/unsigned integers, binary addition and subtraction, carry and overow. Instruction set architecture, registers, instruction formats, arithmetic instructions, immediate operands, bit manipulation. 3 Load and store instructions, ow control instructions, pseudoinstructions, and addressing modes. Translating expressions, if-else statements, loops, array indexing and traversal 4 MIPS assembly language programming, tools, program template, directives, text, data, and stack segments, dening data, arrays, and strings, symbol table, memory alignment, byte ordering, and console input and output. 5 Dening procedures, procedure calls and return address, nested procedure calls, passing arguments in registers, runtime stack, stack frames, local variables, value and reference parameters, saving and restoring registers. 6 Integer multiplication, unsigned and signed multiplication, sequential multiplier hardware, faster (tree) hardware multiplier, integer division, sequential divide hardware, integer multiplication and division in MIPS. 7 Floating point representation, IEEE 754 standard, normalized and denormalized numbers, zero, innity, NaN, FP comparison, FP addition, FP multiplication, rounding and accurate arithmetic. Floating-point instructions. ECE M. Awedh

6 Week Topics 8 CPU performance and metrics, CPI, performance equation, MIPS as a metric, Amdahl?s law, benchmarks and performance of recent processors. 9 Designing a processor, register transfer level, datapath components, clocking methodology, single-cycle datapath, implementing a register le and multifunction ALU. 10 Control signals and control unit, ALU control, single-cycle delay analysis and clock cycle, multi-cycle instruction execution, CPI of a multi-cycle processor, Performance comparison of a single-cycle versus a multi-cycle processor. 11 Pipelining versus serial execution, MIPS 5-stage pipeline, pipelined datapath, pipelined control, pipeline performance. 12 Pipeline hazards: structural, data, and control hazards, load delay, hazard detection, stall and forwarding unit, and delayed branching. 13 Main memory organization and performance, SRAM, DRAM, latency and bandwidth, memory hierarchy, cache memory, locality of reference. 14 Cache memory organization: direct-mapped, fully-associative, and setassociative caches, handling cache miss, write policy, and replacement policy. 15 Cache performance, memory stall cycles, and average memory access time. Tips for Success in this Class ˆ Don't miss class. New material is covered each lecture. If you miss class, you are responsible for covering the missed material on your own. Repeat lectures will not be given during oce hours. ˆ Read in advance. The reading assignments are listed in the class website. Your textbook author has written many digital design and computer engineering texts, and your text in particular is considered one of the most "readable" in print. The ECE M. Awedh

7 argument "but the book is dicult to read" receives very little respect in any forum. ˆ Start homework early. Give yourself some time to consider the problems and determine whether or not you need instructor assistance. Last-minute questions are a bad idea. ˆ Don't ignore the homework. They comprise 10% of your grade! ˆ Ask questions. This includes during class, during discussions, and during oce hours. I don't like a silent class feel free to ask questions or make reasonable comments at will (but no distracting side conversations). ˆ Don't arrive late for class. If you know you'll be delayed (or absent) for some reason, just let me know ahead of time in person or via . It's the courteous and adult thing to do. Policies ˆ All assignments will be due at the beginning of the class on the due date. No late submissions will be accepted unless a valid excuse is given to the instructor by the day prior to the due date. ˆ You are expected to attend all classes. If you miss a class, you are responsible for nding out the material covered in that class. If you miss an exam, a grade of zero will be assigned, unless a valid excuse is given. ˆ All assignments are expected to be done by each student individually. Verbal and informal exchange of ideas is permitted, indeed encouraged. However, written solution should NOT be shown to another student or copied from another student. Any act of academic dishonesty will result in an F grade. The material covered in this course is not hard, but it does require signicant amounts of eort. Be prepared to work hard and come out of this course with a good knowledge of the fundamentals of digital systems. Just like with anything worthwhile in life, if you aren't willing to put in the time and eort, you won't ever become good at it. Be prepared to devote considerable time and eort to this class. ECE M. Awedh

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