LSN 2 Computer Processors
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1 LSN 2 Computer Processors Department of Engineering Technology
2 LSN 2 Computer Processors Microprocessors Design Instruction set Processor organization Processor performance Bandwidth Clock speed
3 LSN 2 Machine Instructions CPU instruction set is the collection of different instructions that the CPU can execute Elements of machine instruction Operation code Source operand reference Unary Binary Result operand reference Next instruction reference
4 LSN 2 Instruction Cycle 2-step instruction cycle Program Counter (PC) contains address of next instruction to execute
5 LSN 2 Programming Models Defines how instructions access their operands and how instructions are described in the processor s assembly language Instruction types Processor - memory Processor - I/O Data processing Control Combination of above
6 LSN 2 Stack Based Architectures System registers (register file) are invisible to running programs Instructions read their operands from and write their results to a stack Stack Comprised of contiguous block of locations, only one of which can be accessed at a time Stack operations PUSH (write) to stack POP (read) from stack
7 LSN 2 Stack Based Architectures Stack format Requires three address to operate Stack pointer Stack base Stack limit Stack grows from higher to lower address
8 LSN 2 Stack Based Architectures Slow operations Whole stack or part of stack typically stored in main memory Since all addresses are implicit, multiple operations are required Small footprint for program in memory since it does not need to specify source/destination addresses Programs running on stack based architectures require postfix (RPN) notation Operator follows its operands a + b ab+
9 LSN 2 Stack Based Architectures
10 LSN 2 General Purpose Register Archs. Instructions read their operands and write their results to a random-access register file Register selection is unordered Registers are accessed via a register ID Reading values from GPRs does not remove them from memory (not POPed) Programs are responsible for selecting which values remain in registers at any given time
11 LSN 2 Instruction Set Architecture Defines how a processor is programmed Directly linked to assembly language Code density Based on the number of operands in each instruction Complex Instruction Set Computers (CISC) Large instruction set to accommodate most high-level operations Small memory footprint for programs Reduced Instruction Set Computers (RISC) Simple and fast instructions Large memory footprint for programs Load-store architecture
12 LSN 2 Instruction Set Architecture CISC ISAs X86 (IA-32) IA-64 / AMD64 Motorola 68k RISC ISAs ARM PowerPC MIPS
13 LSN 2 Addressing Modes Set of syntaxes and methods that instructions use to specify a memory address Register addressing Load/store instructions (RISC) CISC instructions that reference memory Label addressing Branch instructions using a label for destination address Relative addressing Register plus immediate addressing Value of specified register is added to the constant value in instruction
14 LSN 2 Instruction Encoding Selecting the bits that represent the ISA Fixed length Simple to decode Easily predicts next instruction location Wasted memory potential Variable length Memory efficient More complex decoding logic Next instruction location unknown until current decode
15 LSN2 Processor Organization Arithmetic and Logic Unit (ALU) Control Unit (CU) Registers Internal CPU bus
16 LSN2 ALU All other components of the computer system exist mainly to bring data into the ALU for processing and to have the results sent back out All operations result in data stored to registers Comprised of digital logic to perform necessary arithmetic and logic operations
17 LSN2 Register Organization The memory internal to the CPU User visible registers Allow user programs to minimize main memory access General purpose registers Sometimes used to store the operand of an instruction Data registers Only hold data, not used during address calculation Address registers Used for general purpose addressing or devoted to a particular addressing mode Condition code registers Condition codes are bits set by the CPU hardware as the result of operation
18 LSN2 Register Organization Control and status registers PC IR MAR MBR
19 LSN2 Multiprocessor Design Flynn s classification of computer architectures Single Instruction stream, Single Data stream (SISD) Single Instruction stream, Multiple Data stream (SIMD)
20 LSN2 Multiprocessor Design Flynn s classification of computer architectures Single Instruction stream, Multiple Data stream (SIMD) Multiple Instruction stream, Multiple Data stream (MIMD)
21 LSN2 Multiprocessor Design Flynn s classification of computer architectures Multiple Instruction stream, Multiple Data stream (MIMD)
22 LSN2 Multiprocessor Design Speedup How much faster a program runs on a system with n processors than it does on a system with 1 processor of the same type
23 LSN2 Multiprocessor Design Speedup divergence Interprocessor communications Synchronization Load balancing Superlinear speedup Some programs are more efficient on multiprocessor machines than on uniprocessor machines
24 LSN2 Multiprocessor Systems Multiprocessor systems either contain a centralized or distributed memory architecture Centralized All data in memory is accessible to any process Latency r/w issues can arise Distributed Each processor has its own dedicated local memory system Lower latency Requires interprocessor communications
25 LSN2 Intel Multi-Core Processors Intel Core2 Duo Intel Core2 Quad
26 LSN 2 Homework Reading Chapter Chapter Chapter Assignment HMWRK1.pdf References Stallings, W, Computer Organization & Architecture, Prentice Hall, 7 th Ed., 2006
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