Architekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen. Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik

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1 Architekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik

2 Contents Überblick: Aufbau moderner FPGA Einblick: Eigenschaften und Architektur von SoC FPGA Nachbarblick: Unterschiede zwischen Hauptkonkurrenten Ausblick: SoC FPGA der 2ten Generation 2

3 Digital hardware of the past DRAM & Controller Program Memory Communications Controller Customer Specific Logic Processor Scratch SRAM

4 Not flexible Hardware 4

5 Classic FPGA FPGA Fabric Interconnection between Logic Cells Logic Cell Lookup Table Image courtesy of Clieve Maxfield 5

6 FPGA with Hard Silicon Blocks Logic Element Block RAM Multiplier DSP block PLL Clock Manager I/O Bank Transceiver 6

7 Example of DSP hard block FIR Filter Register Filter coefficient Accumulator Digital Signal Processing Slice Source: Altera DSP Users Guide Scalable Multiplier Accumulator Konfig. Altera Cyclone Xilinx Zync 1 9x9 25x x19 35x x27 42x18 Source: Xilinx Users Guide 7

8 SoC FPGA & Silicon Convergence Classic FPGA General Processor ASIC ASSP SOC FPGA + Great flexibility - No Hard Processors - Licensing costs for IP + Software programmable + Great flexibility - Few application specific features + Customer Specific + Great power efficiency - High development costs - High turnaround times - Poor flexibility + Power efficient + No licenses + Great power efficiency -Poor flexibility + Good power efficiency + Less board space + High interconnect speed 8

9 Architecture of SoC FPGA SoC FPGA MPU Portion FPGA Portion Flash Controllers SDRAM Controller Subsystem Control Block User I/O HSSI Transceivers Cortex-A9 MPU Subsystem On-Chip Memories Support Peripherals Processor- FPGA Bridges FPGA Fabric (LUTs, RAMs, Multipliers & Routing) PLLs Interface Peripherals Debug PLLs Hard PCIe Hard Memory Controllers 9

10 SoC FPGA Architecture Dedicated MPU Pins UART CAN I2C SPI SD/SDIO GPIO Timer GigEth USB OTG Static Memory Controller DMA Interconnect ARM Cortex-A9 Neon/FPU L1 Cache Debug and Trace Block Memory L2 Cache Processor FPGA Bridges FPGA Fabric ARM Cortex-A9 Neon/FPU L1 Cache Multiport DDR2/3 Controller DSP Blocks Dedicated DDR Pins 1) Only Altera 2) Only Xilinx Scratch SRAM Boot ROM Multiport DDR2/3 Controller 1) PCIe A/D Conv. 2) FPGA Pins Transceivers 10

11 Processor to FPGA Bridges Altera Master Slave Xilinx Dual ARM Cortex-A9 Dual ARM Cortex-A9 ACP L2 Cache ACP L2 Cache L3 Interconnect 32-bit Multiport DDR3 Controller Master/Slave Interconnect Scratch SRAM Multiport DDR3 Controller MPU/ FPGA Bridge 128-bit FPGA/ MPU Bridge 128-bit Lightweight Bridge 32-bit 32-bit Scratch SRAM 256-bit 64 General Purpose bit High Performance Memory Interconnect Ports 288 FPGA Fabric FPGA Fabric ~ 100 ~ 90 Gbps 11

12 SoC Processor Cores Altera Xilinx CPU-Core Dual ARM Cortex-A9 MPCore Dual ARM Cortex-A9 MPCore Debug CoreSight CoreSight Neon-SIMD Neon-SIMD CPU Clock frequency 1) MHz MHz L1-Cache (Data/Instruction) 32 KB/ 32KB parity protected 32 KB/ 32KB parity protected L2-Cache 512KB ECC protected 512KB no ECC parity protected Scratch SRAM 64KB ECC protected 256KB parity protected Boot ROM 64KB 128 KB 1) CPU Clock frequency depends on speed grade 12

13 Comparing Altera and Xilinx Low End Altera Cyclone V 5CSEA5 Xilinx Zync Z-7020 Package Variantes 3 2 FPGA I/O Pins FPGA Logik 85k Logikelemente 85k Logikzellen FPGA Block-RAM 3.9 Mbit 4.3 Mbit SDRAM Controller 32-bit DDR2/DDR bit DDR2/DDR DSP Slices 174 (18x19 config.) 220 (18x25 config.) DSP Performance 104 GMAC/s 158 GMAC/s A/D Converters None 2 x 12 bit MSPS 17 inputs Static Power/W Total Power/W

14 Comparing Altera and Xilinx Mid End Altera Arria V5ASTD3 Xilinx Zync Z-7045 Package Variants 3 3 FPGA I/O Pins FPGA Logik 350k Logikelemente 350k Logikzellen FPGA Block-RAM 17.2 Mbit 17.4 Mbit Serial Transceivers 1) 30 x Gbits/s 16 x 12.5 Gbps or 16 x 10.3 Gbit/s SDRAM Controller 32-bit DDR2/DDR bit DDR2/DDR DSP Slices 1618 (18x19 config.) x25 (config.) DSP Performance 1197 GMAC/s 1334 GMAC/s A/D Converters none 2 x 12 bit MSPS 17 inputs Static Power/W Total Power/W ) For largest package 14

15 2 nd Generation SoC FPGA What has the 2 nd Generation to offer? 15

16 Intended Altera 2nd Generation 1. Generation Altera Arria 5 2. Generation Largest Altera (Arria 10) Process 28nm 20 nm Low Power Prozessor Clock 800 MHz 1.5 GHz (overdrive) Logic Elements 504k 1150k Power Dissipation 1x 0.6x Max Transceivers speed Gbps Gbps Memory Devices DDR3 SDRAM 1333Mbps DDR3 SDRAM 2133Mbps DDR4 SDRAM 2666 Mbps Soc SRAM 64KB 256kKB FPGA-MPU Bridge Up to Up to 128-bit Code Encryption - Secure Boot DSP Blocks 27 x 27 Multipliers 54 x 54 Multipliers 16

17 Questions 17