NAND and NOR Implementation

Transcription

1 University of Wisconsin - Madison EE/omp ci 352 Digital ystems Fundamentals harles R. Kime ection 2 Fall 200 hapter 2 ombinational Logic ircuits Part 7 harles Kime & Thomas Kaminski NND and NOR Implementation We found that we could implement general oolean equations with these three primitives: ND OR NOT In this section we will find that either of two gates, the NND gate or the NOR gate can be used to implement arbitrary logic functions. We use the Positive Logic onvention (where all signals are active high) and a small circle to on a symbol to represent NOT or invert. hapter 2-Part 7 2

2 NND Gates The basic positive logic NND gate is denoted by the following symbol: ND-Invert (NND) X NND comes from NOT ND, I. e., the ND function with a NOT applied. We call this symbol for a NND gate an ND-Invert. The small circle represents the invert function. If we apply DeMorgan's Law we get: X = X + + F(X,, ) = X hapter 2-Part 7 3 NND Gates (ont.) pplying DeMorgan's Law gives: Invert-OR (NND) X We call this symbol for a NND gate the Invert - OR since all inputs are inverted, followed by the OR function. oth symbols represent the NND gate - it is sometimes more logically descriptive to use one form over the other. NND gate with one input degenerates to an inverter. F (X,, ) = X + + hapter 2-Part 7 4 2

3 NND Function Implementation NND gates can implement a simplified um-of- Products form. onstructing two level NND-NND gate circuit: D The first level is two 2-input NND gates using ND- Invert. The second level is one 2-input NND gate using Invert-OR. Using the NND relationship, we have: G(,,, D) = D = + D = + D G(,,, D) = + D hapter 2-Part 7 5 NND Implementation (ont.) In the implementation, note that the bubbles are on opposite ends of the same line. Thus, they can be combined and deleted: D G(,,,D) This form of the implementation is the um-of-products form. hapter 2-Part 7 6 3

4 NND Implementation (ont.) In the implementation, the bubbles are on opposite ends of the same line. y X = X, they can be combined and deleted: D G(,,,D) sum-of-products (OP) form results To implement an equation like: F(,,) = +, the NND for degenerates to a NOT since there is only one input hapter 2-Part 7 7 Degenerate ND Term The degenerate NND becomes an inverter: To implement the complement of F using NND gates, add an inverter to the output: F(,,) F'(,,) hapter 2-Part 7 8 4

5 NND-NND Example w Implement: y z F(w,x,y,z) F (w, x, y, z) = y z + w x + x y + w z x w y z F (w,x,y,z) x hapter 2-Part 7 9 ummary: Two-Level NND ircuits Find minimum literal OP form for F and F elect OP form with smallest literal count onvert selected form to NND circuit using ND-invert (inverters for single literal ND terms) and invert-or symbols If OP form for F used, add inverter to circuit output. hapter 2-Part 7 0 5

6 NOR Gates The basic positive logic NOR gate (Not-OR) is denoted by the following symbol: OR-Invert (NOR) X F (X,,) = X+ + This is called the OR-Invert, since it is logically an OR function followed by an invert. y DeMorgan's Law we have the following Invert-ND symbol for a NOR gate: Invert-ND X single-input NOR gate is an inverter, too. hapter 2-Part 7 NOR Gates The basic positive logic NOR gate is denoted by the following symbol: OR-Invert (NOR) X NOR comes from NOT OR, I. e., the OR function with a NOT applied. We call this symbol for a NOR gate an OR-Invert. The small circle represents the invert function. If we apply DeMorgan's Law we get: X + + = X F (X,,) = X+ + hapter 2-Part 7 2 6

7 NOR Gates (ont.) pplying DeMorgan's Law gives: Invert-ND (NOR) X We call this symbol for a NOR gate the Invert- ND since all inputs are inverted, followed by the ND function. oth symbols represent the NOR gate - it is sometimes more logically descriptive to use one form over the other. NOR gate with one input degenerates to an inverter. F (X,, ) = X hapter 2-Part 7 3 NOR Function Implementation NND gates can implement a simplified um-of- Products form. onstructing two-level NOR-NOR circuit: D The first level is two 2-input NOR gates using OR- Invert. The second level is one 2-input NOR gate using Invert-ND. Using the NOR relationship, we have: G (,,, D) = ( + ) + (+ D) = ( + ) (+ D) = ( + ) (+ D) ( + )( ) G (,,,D) = + D hapter 2-Part 7 4 7

8 Useful Transformations From Involution (i.e. (')' = ) and DeMorgan's Law, we get the following useful equivalences: ( ) = (( )')' ('+')' (+) = ((+)')' (' ')' ( )' ('+') (+)' (' ') These simple transformations can be used to manipulate a two level network. hapter 2-Part 7 5 Graphical Transformations The relations from the previous slide lead to the following transformations: ( ) = (( )')' (+) = ((+)')' ( )' (+)' ('+')' (' ')' ('+') (' ') Recall that two bubbles in series can be removed from the circuit hapter 2-Part 7 6 8

9 General Two-level Implementations We need to consider whether the form of a two-level implementation is to be:. OP (ND-OR) or 2. PO (OR-ND). omplemented output functions (i.e. ND-NOR or OR- NND) can be handled by complementing the function. Given a function F expressed as a Karnaugh Map, we can use the same general procedures we have used before to minimize the function and express it in OP or PO form. hapter 2-Part 7 7 General Implementations (ont.) Given a two level implementation desired, use the previous transfromations to get it into one of the below forms. Then follow the steps to transform the function to the desired form: For Type: Use: ND-OR ircle 's in the K-Map and minimize (OP Form) (lso use for NND-NND) ND-NOR ircle 0's in the K-Map and minimize (OP complemented) OR-ND (PO Form) OR-NND (PO complemented) ircle 0's in the K-Map and minimize OP. Use DeMorgan's to transform to PO. (lso use for NOR-NOR) ircle 's in the K-Map and minimize OP. Use DeMorgan's to transform to PO. hapter 2-Part 7 8 9

10 Implementation Example 0 Implement the function in NOR-OR. 0 0 We can remove the "Inverter" and replace it with the complement of the input variable hapter 2-Part 7 9 Implementation Example 2 0 Implement the function in ND-NOR. 0 0 hapter 2-Part

11 Multi-level NND Implementations dd inverters in two-level implementation into the cost picture ttempt to combine inverters to reduce the term count ttempt to reduce literal + term count by factoring expression into POOP or OPO hapter 2-Part 7 2 Multi-level NND Example F = inputs and 8 gates* = = ( + + ) + ( + + ) 7 inputs and 4 gates F * ounting inverters (NOT) as input and gate hapter 2-Part 7 22

12 Multilevel NND Example 2 F = + D + + D hapter 2-Part