AMS Verification at SoC Level: A practical approach for using VAMS vs SPICE views

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1 AMS Verification at SoC Level: A practical approach for using VAMS vs SPICE views Nitin Pant, Gautham Harinarayan, Manmohan Rana Accellera Systems Initiative 1

2 Agenda Need for SoC AMS Verification Mixed Signal SoC Overview VAMS vs SPICE Approach Power Management Data Converters Clocking, DDR & LCD Sub-systems Results Conclusion Accellera Systems Initiative 2

3 Need for SoC AMS Verification Emulate True behavior of SoC Analog blocks. Identify electrical problems due to integration of various analog & digital modules. Maximize electrical coverage during the verification. Identify weaknesses of SoC sub-systems containing Analog IPs using pre-silicon simulations Avoid Re-spins, substantially saving NRE costs Real time use case simulations with critical Analog blocks. Accellera Systems Initiative 3

4 Mixed Signal SoC + Testbench : Overview CPU SRAM TEST Crystal Model Analog sensor model with source impedance Crystal Osc RC Osc ADC Power DUT Management LCD Clock Generator Transceivers Display Monitor Clock profile Monitor A/D converter Monitor Analog DAC monitor with loading effect DAC VREG Power Domains DUT Power Management monitors Supply drivers with source impedance and package parasitic SPICE Model VAMS Monitor Verilog Model VAMS Driver

5 VAMS vs SPICE Approach Power Management Accellera Systems Initiative 5

6 Power Management (Voltage Regulator Startup) Sensitive circuits such as bandgap, comparators, amplifiers demand high accuracy for simulation. Chances to catch many potential weakness in voltage startup of regulator increase with SPICE. Simulation Run Time is significantly less compared to clocking related analog modules. Accellera Systems Initiative 6

7 Power Management (Low Power State Machine) State machine can purely be modeled in VAMS/Verilog. SPICE view is not needed here because the modelling is mostly event based. Electrical events can be used for power mode transitions in the state machine. Accellera Systems Initiative 7

8 Defect Power Management (Mode Transition) A co-relation was observed between the Regulator discharge level and wake-up event. In this case, the wake-up occurred when the regulator output had discharged to 600mV. The regulator initially responds slowly, only to later cause an abrupt and massive inrush condition. This causes the 1.5V input high voltage supply to fall as low as 1.17V. This severe inrush condition wasn t seen at other discharge levels. Needed PMC IP design fix. Accellera Systems Initiative 8

9 Defect Power Management (Loading Impact) This is a classic case of instability of regulated voltage during mode transition. Transient loads on regulated supply may cause system level impact especially in multi regulator SoC. The vulnerability of the system under such condition can be seen accurately with SPICE views. Accellera Systems Initiative 9

10 Power Management (Current Consumption Checks) Accellera Systems Initiative 10

11 VAMS vs SPICE Data Converters Accellera Systems Initiative 11

12 ADC Static Performance The Data converter generally has variety of multiplexed input channels. There s a possibility of contention if more than one channel is ON at a time. Slow changing or static input voltages can be converted using VAMS view of ADC. Accellera Systems Initiative 12

13 ADC Dynamic Performance Restructured Sine Wave from Digitized Data 2000 Series SoC AMS simulation data Parameters such as Signal to Noise Ratio (SNR) and Total Harmonic Distortion(THD) need high accuracy simulation environment. Degradation in such ADC Dynamic performance due to incorrect sampling of data, clock frequency or noise can be caught with SPICE netlist of ADC Analog. Frequency Plot for SNR/THD Measurement Accellera Systems Initiative 13

14 VAMS vs SPICE Clocking Accellera Systems Initiative 14

15 Clocking Crystal oscillator(xosc) Classic Issue Crystal oscillators are highly sensitive blocks and their sensitivity is very difficult to model in VAMS. The oscillator is mainly sensitive to loop gain and any change in gain settings may lead to wrong output clock behavior. SPICE netlist will show the true behavior of oscillator under such circumstances. Accellera Systems Initiative 15

16 Clocking - PLLs Phase Locked Loop s (PLL) generally have different input clock sources. We should adopt a hybrid approach here to avoid unnecessary huge simulation run time. For example, only XOSC & PLL1 can have SPICE view s in one simulation and rest of the blocks can have VAMS views. This can be repeated for PLL2 & PLL3 as well. Accellera Systems Initiative 16

17 DDR Sub-system Overview Accellera Systems Initiative 17

18 DDR Protocol in AMS Simulation Accellera Systems Initiative 18

19 LCD Controller Sub-system Overview Accellera Systems Initiative 19

20 LCD Controller Defect Caught Accellera Systems Initiative 20

21 Conclusion SoC AMS Verification should use hybrid approach. Critical sensitive blocks must have a SPICE view where as static non sensitive blocks can have VAMS. Clocking & high speed subsystems are ideal for mixed approach with more inclination towards VAMS. More sensitive blocks such as Bandgap, Regulators need SPICE over VAMS. Ideal balance must be maintained for effective electrical coverage over SoC. Accellera Systems Initiative 21

22 Questions Finalize slide set with questions slide Accellera Systems Initiative 22

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