Introduction to VLSI Testing

Transcription

1 Introduction to VLSI Testing 李 昆 忠 Kuen-Jong Lee Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan, R.O.C. Introduction to VLSI Testing.1

2 Problems to Think A 32 bit adder A 32 bit counter with RESET function A 1MB cache memory A transistor CPU Introduction to VLSI Testing.2

3 Introduction Fault modeling Fault simulation Test generation OUTLINE Automatic test pattern generation (ATPG) Design for testability Built-in self test Synthesis for testability An eample Introduction to VLSI Testing.3

4 Testing: To tell whether a system is good or bad Vdd /1 Related fields Verification: To verify the correctness of a design Diagnosis: To tell the faulty site Reliability: To tell whether a good system will work after some time. Introduction to VLSI Testing.4

5 Importance of testing N = # transistors in a chip p = prob. (a transistor is faulty) Pf = prob. (the chip is faulty) Pf = 1- (1- p) N If p = 10-6 N = 10 6 Pf = 63.2% Introduction to VLSI Testing.5

6 Difficulties in Testing Fault may occur anytime - Design - Process - Package - Field Fault may occur at any place Vdd Vss VLSI circuit are large - Most problems encountered in testing are NP-complete I/O access is limited Introduction to VLSI Testing.6

7 How to do testing from Designer s points of view Circuit modeling Fault modeling Logic simulation Fault simulation Test generation Design for test Built-in self test Modeling ATPG Testable design Synthesis for testability Introduction to VLSI Testing.7

8 Circuit Modeling Functional model--- logic function - f(1,2,...)=... - Truth table Behavioral model--- functional + timing - f(1,2,...)=..., Delay = 10 Structural model--- collection of interconnected components or elements A B E 1 0 G C D 1 0 F 0 Introduction to VLSI Testing.8

9 Levels of Description Circuit level C Switch level VDD VDD VDD C 4B C 3 C 1 C 2 E Gate level A E B G Higher/ System level C D F Introduction to VLSI Testing.9

10 Fault Modeling The effects of physical defects Most commonly used fault model: Single stuck-at fault A B C D E F G A s-a-1 A s-a-0 E s-a-1 E s-a-0 B s-a-1 B s-a-0 F s-a-1 F s-a-0 C s-a-1 C s-a-0 G s-a-1 G s-a-0 14 faults D s-a-1 D s-a-0 Other fault models: - Break faults, Bridging faults, Transistor stuck-open faults, Transistor stuck-on faults, Delay faults Introduction to VLSI Testing.10

11 Fault Coverage (FC) FC = # faults detected # faults in fault list Eample: a b c 10 6 stuck-at faults ( a 0,a 1,b 0,b 1,c 0,c 1 ) Test faults detected FC {(0,0)} {(0,1)} {(1,1)} {(0,0),(1,1)} {(1,0),(0,1),(1,1)} c 1 a 1,c 1 a 0,b 0,c 0 a 0,b 0,c 0,c 1 all 16.67% 33.33% 50.00% 66.67% % Introduction to VLSI Testing.11

12 Testing and Quality IC Fabrication Yield: Fraction of good parts Testing Rejects Shipped Parts Quality: Defective parts per million (DPM) Quality of shipped parts is a function of yield Y and the test (fault) coverage T Defect level (DL) : fraction of shipped parts that are defective Introduction to VLSI Testing.12

13 Yield (Y) 50% 75% 90% 95% 99% 90% 90% 90% 90% Defect Level, Yield and Fault Coverage DL= 1 - Y (1-T) Fault Coverage (T) 90% 90% 90% 90% 90% 90% 95% 99% 99.9% DL: defect level Y: yield T: fault coverage DPM (DL) 67,000 28,000 10,000 5,000 1,000 10,000 5,000 1, Introduction to VLSI Testing.13

14 Logic simulation To determine how a good circuit should work Given input vectors, determine the normal circuit response A I C A B D F B G C C C1 C C2 C E E F B R B I R I F C DE C JE D H E Introduction to VLSI Testing.14

15 Fault simulation To determine the behavior of faulty circuits A 1 E s.a.0 B 0 1/0 C 0 F D 0 1 1/0 G Given a test vector, determine all faults that are detected by this test vector. Eample: A B C Test vector (1 1) detects { a 0, b 0, c 1 } Introduction to VLSI Testing.15

16 Test generation Given a fault, identify a test to detect this fault Eample: A 0 D B F C E To detect D s-a-0, D must be set to 1. Thus A=B=1. To propagate fault effect to the primary output E must be 1. Thus C must be 0. Test vector: A=1, B=1, C=0 Introduction to VLSI Testing.16

17 Automatic Test Pattern Generation (ATPG) Given a circuit, identify a set of test vectors to detect all faults under consideration. Input circuit Form fault list More faults? Yes No Eit Fault dropping Select a fault Test generation Fault simulation Introduction to VLSI Testing.17

18 Difficulties in test generation 1. Reconvergent fanout A B s-a-1 D F C E Introduction to VLSI Testing.18

19 Difficulties in test generation (cont.) 2. Sequential test generation PIs Combinational part PIs Y Y J K CK clk Introduction to VLSI Testing.19

20 Testable Design Design for testability (DFT) ad hoc techniques Scan design Boundary Scan Built-In Self Test (BIST) Random number generator (RNG) Signature Analyzer (SA) Synthesis for Testability Introduction to VLSI Testing.20

21 Eample of ad hoc techniques Insert test point MUX T/N Introduction to VLSI Testing.21

22 Scan System Original design Modified design PI C PO PI C PO SO R T/N R' SI Introduction to VLSI Testing.22

23 Scan Cell Design DI D CK Q Q DI SI N/T (SE) MUX D CK Q Q,SO DI Q DI Q,SO Φ Φ SI Φ Φ T Φ + Φ T Introduction to VLSI Testing.23

24 Scan Register Combinational Circuits Q D Q D Q D Q D SO SI SI SI SI CLK SE Introduction to VLSI Testing.24

25 Boundary Scan I/O Pad Boundary scan cell Boundary scan path TRST* TDI Sout APPLICATION LOGIC TMS Misc. registers TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register TRST*:Test rest (Optional) TDI: Test data input TD0: Test data output TCK: Test clock TMS: Test mode select Introduction to VLSI Testing.25

26 Boundary Scan (Cont.) TRST* TRST* TDI Sout APPLICATION LOGIC TDI Sout APPLICATION LOGIC Misc. registers Misc. registers TMS TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register TMS TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register TRST* TRST* TDI Misc. registers Sout APPLICATION LOGIC TDI Misc. registers Sout APPLICATION LOGIC TMS TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register TMS TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register Introduction to VLSI Testing.26

27 Built-In-Self Test (BIST) Places the job of device testing inside the device itself Generates its own stimulus and analyzes its own response from system mu circuit under test to system pattern generator BIST Controller Response Analyzer good/fail biston bistdone Introduction to VLSI Testing.27

28 Built-In-Self Test (BIST) (Cont.) Two major tasks - Test pattern generation - Test result compaction Usually implemented by linear feedback shift register F/F F/F F/F Introduction to VLSI Testing.28

29 Random Number Generator (RNG) F/F F/F F/F F/F (repeat) 1. Generate pseudo random patterns 2. Period is 2 n -1 Introduction to VLSI Testing.29

30 Signature Analyzer (SA) Input sequence (8 bits) G ( ) = Z P ( ) = Time Input stream Register contents Output stream Initial state Remainder R() = Quotient 1+ 2 Introduction to VLSI Testing.30

31 Introduction to VLSI Testing.31 Signature Analyzer (SA) (Cont.) ) ( 1 ) ( ) ( ) ( G R Q P = = + 1 : ) ( P + 1 : ) ( 2 Q = Prob. of aliasing error = 1/2 n where n is # of FFs

32 Memory BIST Architecture with a Compressor Before After di addr wen Memory Module data sys_di sys_addr sys_wen clk hold_l rst_l test_h si se Memory Module data q so Introduction to VLSI Testing.32

33 Memory BIST Architecture with a Compressor (Cont.) sys_addr sys_d isys_wen rst_l clk hold_l test_h Algorithm-Based Pattern Generator di addr wen Memory Module compress_hclk rst si se data Compressor q so BIST Circuitry Introduction to VLSI Testing.33

34 sys_addr1 sys_addr2 sys_di2 sys_wen2 sys_addr3 sys_di3 sys_wen3 rst_ l clk hold_l test_h Three Memories and One Compressor Algorithm-Based Pattern Generator se si addr1 di2 addr2 wen2 di3 addr3 wen3 compress_h ROM4KX4 Module RAM8KX8 Module RAM8KX8 Module Compressor q so data data data BIST Circuitry Introduction to VLSI Testing.34

35 Synthesis for Testability Automatic v.s Semi-automatic Commercial products - Testability analysis tools - Full / partial scan insertion - BIST insertion - Boundary scan insertion Research - RTL synthesis - FSM synthesis - Gate level synthesis - Boolean equation synthesis Introduction to VLSI Testing.35

36 CPU Test Control Architecture Scan_i Scan_en Scan path Scan_o logic rst_l clk hold_l test_h Bist control Memory TDI bist decoder bist_se bist_si compressor scan decoder bist_so int_scan mbist decoder MUX TDO TCK TMS TAP Controller IR Introduction to VLSI Testing.36

37 Testable Design Flow Prepare Initial Design RTL Code Integrate all DFT Methodologies Verify Functionality Generate/Verify Test Patterns by FastScan Identify Blocks for BIST/Scan Insert/Verify Internal Scan Circuitry by DFTADvisor Insert/Verify BIST Circuitry by MBISTArchitect P/F Synthesis to Gate Level Modify/Verify Original Design Reserve Dummy Ports for Internal Scan Insert/Verify Boundary Scan Circuitry by BSDArchitect Introduction to VLSI Testing.37

38 Problems re-thinking A 32-bit adder --- ATPG A 32-bit counter --- Design for testability + ATPG A 1MB Cache memory --- BIST A transistor CPU --- All test techniques Introduction to VLSI Testing.38

39 Conclusions Two major fields in testing ATPG --- Fault simulation --- Test generation Testable design --- Design for testability --- Built-in self-test --- Synthesis for testability Introduction to VLSI Testing.39