1 Introduction. 5 Nontechnical Issues. 6 Summary. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2011/ / 64

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1 Introduction Introduction SSTEM WBUDOWAE Design Methodology c Dr inż. Ignacy Pardyka UIWERSTET JAA KOCHAOWSKIEGO w Kielcach Rok akad. 2/22 2 Synthesis 3 4 Design for Test 5 ontechnical Issues 6 Summary c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 2 / 64 Design Methodology Introduction Design Methodology A simple design methodology Introduction Designing a digital system of any significant complexity is a large undertaking, requiring a systematic approach Design teams can range in size from a handful of engineers for a relatively simple product, to several hundred people for a complex IC or packaged system We use the term design methodology to refer to the systematic process of design, verification and preparation for manufacture of a product A design methodology specifies: tasks undertaken information required and produced by each task relationships between the tasks including dependencies and sequencing CAD tools used. Simple methodology: requirements and constraints include function requirements (what the product is to do) performance requirements (how fast it is to do it) constraints: power consumption, cost, packaging tasks: design, synthesis, physical implementation each followed by a verification the design task: understanding the requirements and constraints and developing a specification of a digital circuit that meets the requirements and constraints the information produced by this task is a collection of models that describe the design If verification fails at any stage, we must revisit a previous task to correct the error. Requirements and Constraints Design Functional Synthesize Post-Syn Verifica OK Physi Implemen Physi Verifica OK c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 3 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 4 / 64

2 Introduction Introduction Design Methodology A simple design methodology Design Methodology Hardware/software codesign Hierarchical composition involves developing a subcircuit that performs some relatively simple function, then treating it as a black box We can first verify each of the most primitive subcircuits as independent units ext, we can verify a subsystem that uses the subcircuits by treating the subsystem as a collection of black boxes This approach is often called top-down design. Architecture Design Unit Design Unit Integration We can choose which aspects of functionality can be implemented by embedded software on a processor core, and which parts can be implemented as digital subcircuits, that is, by hardware Designing the hardware and software for a system together is called hardware/software codesign Deciding which parts to put in hardware and which in software is called partitioning There are numerous trade-offs to consider many conditions and alternative actions can be hard to implement in hardware, but is relatively straightforward in software rapid computations on large amounts of data or data that arrives at a high rate may need a very high performance (and hence costly and power hungry) processor core, and so may more readily be performed by customized hardware. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 5 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 6 / 64 Introduction Design Methodology Hardware/software codesign Hardware Requirements and Constraints Hardware Design Requirements and Constraints Partitioning Software Requirements and Constraints Software Design Introduction 2 Synthesis 3 Hardware Manufacture Test Software 4 Design for Test 5 ontechnical Issues 6 Summary c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 7 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 8 / 64

3 Hierarchical hardware/software codesign Software Requirements and Constraints S/W Unit Design S/W Unit S/W Integration S/W Integration Requirements and Constraints and Partitioning Hardware Requirements and Constraints H/W Unit Design H/W Unit H/W Integration H/W Integration A Synthesize Post-synthesis Physical Implementation Physical Manufacture B For many complex systems, the hardware is simply the platform upon which to deliver the software, with most of the functionality of the system implemented in the software. in such systems, developing the software is a major proportion of the system development effort. A key part of a design methodology is the set of electronic design automation (EDA) tools used to support it. For nearly all designs, it is not feasible to make physical prototypes to ensure that the design is correct and meets constraints. Instead, we design models as virtual prototypes in forms that EDA tools can analyze and refine. Test FIGURE. A prototypical A B design flow, including hardware/ software codesign. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 9 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 / 64 We use the term architecture exploration, alternatively, design space exploration, to refer to the task of abstract modeling and analysis of candidate designs choice is typically guided by one or more objective functions, such as cost, performance, power consumption, or reliability Partitioning: application of a divide-and-conquer problem-solving strategy Components need not be physical parts of the system. Instead, we can think of logical partitioning: identifying parts of the system that will implement the various processing steps This form of partitioning is also called functional decomposition. We can also think about the kinds of physical components that we might include in the system and how the logical partitions can be mapped to the physical partitions Physical partitions: can include processor cores, accelerators, memories and I/O controllers Also important is hardware/software partitioning: logical component may be mapped to a specialized hardware component whose only task is to implement that logical component logical component may be mapped to a software task run on a processor core under control of a real-time operating system c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 2 / 64

4 Example of logical partitioning: Video Input Video Filter Edge Detect Shape Detect System Control Plate Detect And physical partitioning of the same system: Video Input Video Filter Edge Detect Processor Bus Shape Detect Bus Bridge Processor Core Diag/ Maint Plate Recog Memory Log etwork Interface etwork Interface Decisions made in this early stage of the design flow have a major impact on the rest of the design The most valuable asset in this stage is the experience of the system designer The result is known as a high-level specification of the system specification might be expressed in a language that can be executed or simulated, such as certain forms of the Unified Modeling Language (UML). Video Memory Video Bus c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 3 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 4 / 64 Common UML diagrams class use cases component communication state chart timing sequence activity object package composite structure interaction deployment UML uses diagrams and models as a first step towords expressing static and dynamic relationships among objects UML provides a very good mechanism for quickly exchanging ideas with other designers and for capturing the critical elements of the design. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 5 / 64 We can decompose each component into subcomponents, which we then design and verify as units. That might also involve further decomposition, until we reach a level of complexity that is manageable We can develop a behavioral model of the component, expressing its functionality at an intermediate level of abstraction between system level and register-transfer level the purpose of the behavioral model is to allow function verification of the component before proceeding to detailed implementation To implement a given component, we can take several approaches design a new implementation by refining the higher-level model reuse a component from a previous system, from a library of components, or from a component vendor term intellectual property, or IP, refers to such reusable components if an IP block does not exactly meet the requirements for our system, we may be able to adapt it with less effort than would be required for a fresh start. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 6 / 64

5 Core Generators If the IP performs the required function, but does not have quite the right interface connections or timing, we might be able to embed it in a wrapper, circuitry that deals with the differences. If the IP has almost the required function and the source code is available to us, we might be able to make minor changes to adapt its functionality to our needs Alternative for implementing a component may be to use a core generator Core Generator: an EDA tool that generates a model of a component based on parameters that describe its function Core generators are available for common kinds of functions, such as memories, arithmetic units, bus interfaces, digital signal processing, and finite-state machines the Xilinx Core Generator is included as part of the Xilinx ISE tool suite linked from the companion website for each function, parameters controlling operation of the generated core can be specified the tool then automatically generates a suite of design files for the specified function, including HDL source code for behavioral simulation and net-list files for inclusion in the physical design. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 7 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 8 / 64 Verifying each subsystem can be considered to be a prerequisite for verifying the entire system Components can then be integrated into the next-level subsystem, which is then verified. The process is repeated, up to the top level of the system. At higher levels of the design hierarchy, the functionality of subsystems and the complete system gets much more complex. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 9 / 64 There are a number of techniques that we can apply directed testing: involves identifying particular test cases to apply to the DUV and checking the output for each test case: develop a testbench model that provides input values to the design under verification (DUV) and checks that the output values are correct. The DUV is also frequently called a device under test (DUT), or unit under test (UUT) very effective for simpler components where there are only a small number of categories of stimulus constrained random testing: involves a test case generator randomly generating input data, subject to constraints on the ranges of values allowed for the inputs formal verification: allows complete verification that a component meets a specification (embodied in one or more asserted properties, expressed in a property specification language (PSL)). SystemVerilog extension of Verilog includes features similar to those of PSL for expressing properties. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 2 / 64

6 Hardware/Software Co- A property can be as simple as a Boolean expression relating the values of signals in the design A property might involve temporal expressions relating sequences of values over time: specify that activation of a select signal followed by an enable signal on the next clock cycle is followed by activation of an acknowledge signal within three clock cycles and deactivation of all three signals on the subsequent cycle A formal verification tool performs state-space exploration to verify the asserted properties. In an embedded system, much of the system s functionality may be implemented in software that interacts with hardware We need to verify the software and its interaction with the hardware If we had hardware models of the processor and the instruction and data memories, we could verify the software by simulating its execution on the hardware models this approach is very slow, since simulation of each processor instruction involves simulation of much of the detail of hardware operation c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 2 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 22 / 64 Hardware/Software Co- Hardware/Software Co- We can take to make hardware/software co-verification much faster: divide the software into two layers: a lower layer that depends on the hardware, and an application layer that is insulated from the hardware by the lower layer: hardware abstraction layer (HAL) it provides an abstract interface that can be called by the application layer a software verification tool can emulate the operations provided by the hardware abstraction layer The software developer can write the software in a programming language, making calls to the emulated abstraction layer, and run the software on their host computer. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 23 / 64 For more detailed verification of embedded software, we can use an instruction set simulator (ISS) ISS uses code compiled into the instructions of the target embedded processor it then simulates execution of those instructions, but without simulating the detailed hardware operations of the target processor. Once the hardware design team has developed models of the hardware that interacts with the embedded software, we can perform cosimulation of the hardware and software the two simulators run concurrently, communicating when the processor performs bus read and write operations as more detailed implementation models of the hardware become available, they can be substituted for the bus functional models cosimulation is much slower than executing the software on a real processor, so we would typically run only small sections of the embedded software. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 24 / 64

7 Synthesis Synthesis Synthesis: refinement of the functional design to a gate-level net list can be performed automatically using an RTL synthesis tool starts with models of the design refined to the register-transfer level The tool then infers hardware constructs for the model for each of inferred hardware elements, the synthesis tool determines an implementation using primitive circuit elements from a technology library translating is guided by synthesis constraints Synthesis of a design is followed by a further verification step to ensure that it meets timing constraints and functional requirements. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 25 / 64 Physical design: the final stage in the design flow to refine the gate-level design into an arrangement of circuit elements build the programming file that configures each element in an FPGA consists of floorplanning, placement, and routing Floorplanning blocks that have a large number of connections between them should be placed near each other blocks that are connected to external pins should be placed near the edge of the chip Mapping: involves identifying the FPGA-specific resources to be used for each of the library components instantiated instances of gates and multiplexers would be mapped to look-up tables components representing specific FPGA resources, such as RAM blocks, DSP The final result of the placement and routing step for an FPGA is a bit file specifying how the FPGA is to be configured. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 26 / 64 FPGA FPGA Internals: Programming an FPGA All configuration memory bits are connected as one big shift register Known as scan chain Shift in "bit file" of desired circuit Digital Design Copyright 26 Frank Vahid a Pin Pclk (a) (b) Pin Pclk a b d c CLB 8x2 Mem. 2 3 a2 4 a a D D FPGA o m o m m2 m3 Switch matrix CLB 8x2 Mem. 2 3 a2 4 a a D D 2x 2x 2x 2x Conceptual view of configuration bit scan chain is that of a 4-bit shift register (c) Bit file contents for desired circuit: This isn't wrong. Although the bits appear as "" above, note that the scan chain passes through those bits from right to left so "" is correct here. z y x w 27/4 LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB RAM RAM RAM LB LB LB LB LB LB LB LB LB LB LB LB c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 27 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 28 / 64

8 FPGA FPGA CLB CLB LUT FF LUT FF Slice Slice LUT FF LUT FF LUT FF LUT FF Slice Slice LUT FF LUT FF CLB CLB Bs c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 29 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 3 / 64 FPGA Platform FPGA c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 3 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 32 / 64

9 Power PC 44 Block Diagram of PowerPC 44 Embedded Processor In Virtex 5 FX series FPGAs include one or two PowerPC 44 processors embedded within the FPGA fabric The PowerPC 44 is a superscalar 32-bit RISC processor with an operating frequency up to 55 MHz It contains a 7-stage pipeline with out-of-order execution capabilities Includes primary caches (32KB data, 32KB instructions) Includes Memory Management Unit (MMU) Includes multiple embedded processor interfaces defined by the IBM CoreConnect on-chip system architecture. 28-bit PLB I-Cache Controller Complex Integer Pipe Instruction Unit Issue Issue MAC Instruction Cache (32 KB) GPR File ITLB Branch Unit Target Address Cache Simple Integer Pipe MMU 64-entry 4KB BHT GPR File Data Cache (32 KB) DTLB Load Store Pipe Load/Store Queues D-Cache Controller DCR Bus JTAG Debug Trace 28-bit PLB Interrupt and Timers Clocks and Pwr Mgmt c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 33 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 34 / 64 Embedded Processor Block in Virtex-5 FPGAs FCM Interface Virtex-5 FXT Platform Embedded Processor Block APU Control PowerPC 44 Processor ICURD DCURD DCUWR DMA DMA LocalLink LocalLink SPLB Memory Controller Interface MPLB Introduction 2 Synthesis 3 Control Interface CPM/ Control SPLB 4 Design for Test DCR DCR Interface DMA DMA LocalLink2 LocalLink3 UG2_c ontechnical Issues 6 Summary c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 35 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 36 / 64

10 Computing system MOSFET: metal-oxide semiconductor field-effect transistor Fabricated on the surface of a crystalline silicon wafer Energy Heat gate drain source drain n gate gate oxide p substrate n source Inputs Computing machine Outputs n regions are areas that have been doped (infused) with atoms of an element from Group V of the periodic table n-type material has a surplus of electrons p substrate is an area that has been doped with atoms of an element from Group III of the periodic table p-type material has holes corresponding to missing lattice bonds Environment If the gate voltage is greater than a threshold, electrons are attracted to form an n-type channel immediately under the gate oxide this channel can conduct current between the source and drain. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 37 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 38 / 64 CMOS CMOS gates The CMOS Transistor 2.3 CMOS Inverter +V CMOS transistor Basic switch in modern ICs input output a A positive voltage here......attracts electrons here, turning the channel between source and drain into aconductor. nmos gate CMOS AD source gate oxide drain IC package conducts does not conduct pmos gate Digital Design Copyright 26 Frank Vahid (a) Silicon -- not quite a conductor or insulator: Semiconductor IC does not conduct 6/48 conducts c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 39 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 4 / 64

11 Threshold voltage Logic level thresholds with noise margin signal with added noise.5v.v.5v receiver threshold nominal.4v threshold 2.5V 2.V.5V.V.5V V OH noise margin V IH driven signal V IL V OL noise margin 2.5V 2.V.5V.V.5V signal with added noise logic high threshold driven signal logic low threshold VOL: output low voltage a component must drive a signal with a voltage below this threshold for a logic low VOH: output high voltage a component must drive a signal with a voltage above this threshold for a logic high VIL: input low voltage a component receiving a signal with a voltage below this threshold will interpret it as a logic low VIH: input high voltage a component receiving a signal with a voltage above this threshold will interpret it as a logic high. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 4 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 42 / 64 Power consumption Power consumption c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 43 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 44 / 64

12 Power consumption Static power consumption Transistors, when turned off, are not perfect insulators there are relatively small leakage currents between the two terminals and from the terminals to ground Static power consumption occurs continuously, independent of circuit operation. +V R SW SW R output c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 45 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 46 / 64 Power consumption Power consumption c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 47 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 48 / 64

13 Dynamic power consumption Arises from the charging and discharging of load capacitance when outputs switch between logic levels Power consumption depends on how frequently signals switch between logic levels The total capacitive load is the sum of the individual capacitive loads output +V R SW input Power consumption has become a more significant constraint Recent processor cores include power management features, allowing the processor to operate at various power levels, including powering down completely, and to control power levels of other system components Common way of reducing power in CMOS systems is clock gating: turning off the clock to parts of a circuit whose stored values do not need to change For CMOS components, this effect is much more significant than the static load of component inputs SW R C in clk D since we want circuits to consume less power and to operate as fast as possible, we are constrained to minimize the fanout of outputs to reduce capacitive loading. Q during that interval, the component consumes no dynamic power. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 49 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 5 / 64 Introduction 2 Synthesis 3 Design for Test 4 Design for Test 5 ontechnical Issues 6 Summary Design for Test Design for Test We can reduce the time and cost involved in testing a system by including additional circuitry to improve the system s testability including elements that make internal nodes observable Design for test (DFT): design techniques that seek to improve testability fault models: are abstractions of the effects produced by faults. We use a fault simulator that simulates the operation of the circuit with a given fault injected at a given location scan design techniques D scan_in mode CE clk D CE clk Q Q c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 5 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 52 / 64

14 Design for Test Design for Test Scan Design Boundary Scan Test vectors can be shifted into the registers in the chain, under control of the test mode input data_in scan_in test_mode clk D Q D scan_in scan_in scan_in mode mode mode clk clk clk Q D Q data_out scan_out Stored values can also be shifted out of the registers, thus making them observable The chain of registers allows us to control and observe the combinational blocks between registers The test equipment controlling the process compares the output values with the expected results to detect any faults. Boundary scan: testing the connections between chips on a PCB The idea is to include scan-chain flip-flops on the external pins of each chip when the chain is loaded, the vector is driven onto the external outputs of the chips the scan-chain flip-flops then sample the external inputs, and the sampled values are shifted out to the test equipment Manipulating the scan chain s external interface (inputs and outputs to other chips) it is possible to test for certain faults, caused perhaps by bad soldering Manipulating its internal interface (to on-chip registers), the combinational logic can be tested Testing is done with the IC after it is mounted on the circuit card and possibly while in a functioning system. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 53 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 54 / 64 Design for Test Design for Test Boundary Scan Boundary Scan TAP Connector Joint Test Action Group (JTAG) is the common name for what was later standardized as the IEEE 49. (99) Standard Test Access Port and Boundary-Scan Architecture Device Device 2 Device 3 Standard specifies that each component have a test access port (TAP), consisting of the following connections: Test Clock (): provides the clock signal for the test logic Test Mode Select Input (): controls test operation Test Data Input (): serial input for test data and instructions Test Data Output (): serial output for test data and instructions Test Reset (TRST): optional Test probe need only connect to a single JTAG port to have access to all chips on a circuit board. TAP Connector ntrst ntrst ntrst ntrst c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 55 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 56 / 64

15 Design for Test Boundary Scan Architecture of a component with JTAG boundary scan Boundary Scan Design for Test Boundary scan cell for an input or output pin Boundary scan cells are inserted between external pins and the component core Test access port (TAP) controller governs operation of the test logic JTAG boundary scan cells have been designed to allow testing of the component core also. Input Pins Component Core Bypass Register Design-specific Registers Instruction Decoder Instruction Register TAP Controller Output Pins Tristate Output Bidirectional Output data_in scan_in ShiftDR ClockDR UpdateDR Mode D Q D Q clk clk scan_out data_out Typical connection of automatic test equipment (ATE) to a system with multiple JTAG TAPs ATE c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 57 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 58 / 64 Design for Test Design for Test Boundary Scan TAP Controller State Machine Boundary Scan XChecker Connections to JTAG Boundary-scan TAP Test Logic Reset Run Test/Idle Select DR Scan Select IR Scan Capture DR Capture IR VCC GD RD () Shift DR Exit DR Pause DR Shift IR Exit IR Pause IR VCC GD RD Exit2 DR Exit2 IR Update DR Update IR or are values of at each transition XCHECKER Flying Lead Connector Target System c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 59 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 6 / 64

16 ontechnical Issues ontechnical Issues Introduction 2 Synthesis 3 4 Design for Test 5 ontechnical Issues 6 Summary ontechnical Issues In some cases, the best technical choices may not be the best choices when all things are considered Electronics products, like most products, go through life cycles market research and financial modeling (RE costs, time-to-market) product design manufacturing facilities supply channels sales and distribution channels maintenance and repair, customer service finally, the product becomes obsolete and is retired from production and support When we start a design project, we must be aware of technology trends and make projections to determine the appropriate technology for the future manufacture of our product. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 6 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 62 / 64 Introduction 2 Synthesis 3 Summary 4 Design for Test 5 ontechnical Issues 6 Summary Summary Summary A design methodology codifies the process of design, verification and preparation for manufacture of a product Architecture exploration is the process of modeling and evaluating candidate designs at a high level of abstraction Components may be implemented through IP reuse or by core generators Software and hardware can be tested together using cosimulation A design can be optimized at various stages in the design flow Testability of a circuit can be enhanced by adding test hardware Various nontechnical issues affect the design process, including business and life-cycle considerations. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 63 / 64 c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2/22 64 / 64

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