Architetture di bus per. on-chip motivations

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1 Architetture di bus per System-On On-Chip Massimo Bocchi Corso di Architettura dei Sistemi Integrati A.A. 2002/2003 System-on on-chip motivations Transistors (Millions)/Chip Technology (nm) Growing transistor count on a single chip Implementation of a greater number of functionalities Logic SRAM Flash E-DRAM CMOS RF FPGA FRAM MEMS Chemical sensors Electro-optical Electro-biological New technologies integrated on the same chip

2 Intellectual property reuse Design complexity High number of components Integration of different technologies Critical Time-to to-market Low cost design Intellectual-property (IP) Reuse, among other design technologies, has generated the higher productivity increase. Semiconductor intellectual-property designers strive to ensure their IP can be used by the widest possible range of applications to ensure maximum return on their engineering investment. Ed Smith (Sonics Inc.), 2002 IP-Reuse evolution Small blocks reuse (registers, multiplexer, adders, multipliers, shifters, ) Large blocks reuse (embedded processors, memory controllers, I/O interfaces, DMA controllers, ) System reuse (suitable for multiprocessor systems development, networks-on on-chip, )

3 IP vs. IC IP-based design The basic components are described using a hardware description language (HDL) The components are collected into IP-libraries The whole system is implemented on a single chip IC-based design The basic components consist of several integrated circuits The components are collected into IC-libraries All the components are placed on a board Bus architectures A bus architecture specification provides: interfaces for the components placed on the bus protocols for on-chip communication and signals transmission architectural description of the hardware connections between the peripherals included into the system

4 Bus architectures How bus architectures can improve SoC design: Standard interfaces support IP-Reuse methodology allowing the creation of Plug and Play cores SoC designs are more reliable if based on a standard bus architecture Test methodologies can be improved and supported by standard test interfaces Cost reduction for verification tasks Bus architectures comparison WISHBONE AMBA CoreConnect System and peripheral bus Power consumption reduction Performance increase De facto standard for on-chip bus

5 AMBA specification AMBA is an open standard developed by ARM Ltd. (www.arm.com) A typical AMBA-based SoC consists of a high performance system bus (AHB) and peripheral bus (APB) A standard test methodology is included in the AMBA specification The full AHB specification is contained in the AMBA 2.0 documentation AHB-Lite is a subset to the full AHB specification Multi-layer layer AHB is an extension to the AHB protocol, providing parallel communication paths between masters and slaves A typical AMBA-based SoC Test Interface Controller DMA bus master High performance processor Parallel Port Display controllers Arbiter AHB bus B R I D G E APB bus High Bandwidth On-chip Memory interface High Bandwidth On-chip Memory interface Timer UART Massimo Bocchi, 07/02/2003 Massimo Bocchi ARCES - University of Bologna

6 AMBA AHB main features Pipelined operation Multiple bus masters Burst s Split transactions Non-tristate implementation Wide data bus configurations (up to 128 bits) AMBA APB main features Low power consumption Simple interface Latched address and control Suitable for many peripherals

7 AHB single HCLK HADDR & Control A HREADY HRDATA Data (A) HWDATA Data (A) The addressed slave can insert one or more wait cycles if the data phase has to be delayed AHB masters states no s or busy bus IDLE new burst or single no s NONSEQ single no s single burst BUSY ready for not ready for SEQ burst

8 AHB slaves responses OKAY: : the has been completed successfully ERROR: there was an error during the ; the master should reinitiate the RETRY: the slave has not yet completed the ; the master should retry a new SPLIT: the slave cannot complete the immediately; another higher-priority master can get access to the bus and the current will be completed later Burst s Type SINGLE INCR WRAP4 INCR4 WRAP8 INCR8 WRAP16 INCR16 Description Single Incrementing burst of unspecified length 4-beat wrapping burst 4-beat incrementing burst 8-beat wrapping burst 8-beat incrementing burst 16-beat wrapping burst 16-beat incrementing burst

9 AHB bus interconnection APB s The BRIDGE operates signal conversions from the AHB protocol to the APB one APB features a very simple communication protocol APB slaves cannot insert any wait cycle; the duration of s is fixed

10 APB state diagram no IDLE SETUP no ENABLE AHB-Lite specification Only one bus master is supported The resulting system can be: a simple system containing only one bus master a Multi-layer layer AHB system containing only one bus master per layer AHB-Lite simplifies the full AHB specification: no arbitration is required, since the Request/Grant protocol is not used the AHB slaves don t have to support Split/Retry responses

11 Multi-layer layer AHB specification Parallel paths connecting more than one master/slave Each layer can use a simplified architecture based on the AHB-Lite protocol Arbitration is distributed in each slave that can be accessed by more than one master simultaneously An interconnect matrix is implemented using several multiplexer to select only one master input for each slave Multi-layer layer AHB specification Master 1 Interconnect Matrix Slave 1 Master 2 Slave 2 Slave 3 Master 3 Slave 4

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