Contents. System Development Models and Methods. Design Abstraction and Views. Synthesis. Control/Data-Flow Models. System Synthesis Models

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1 System Development Models and Methods Dipl.-Inf. Mirko Caspar Version: L.r Contents HW/SW Codesign Process Design Abstraction and Views Synthesis Control/Data-Flow Models System Synthesis Models CO mplex ncurrent rrect ordinated DESIGN

2 Designing Embedded Systems design structuring representation of requirements necessary for automation of design process chip - chip board board hardware software design steps scheduling allocation binding objects algorithms for HW and SW 02-3 HW/SW Codesign Process Specification System Synthesis SW Synthesis Interface- Synthesis HW Synthesis machine code netlist

3 Contents HW/SW Codesign Process Design Abstraction and Views Synthesis Control/Data-Flow Models System-Synthesis Models CO mplex ncurrent rrect ordinated DESIGN 02-5 Y-Chart Behavioural View Structural View Test View X-Chart Physical View

4 Example device: MP3 decoder ASIC (HW) system Behavioural View decode files with kBit, 32 Bit output quality, Structural View components for sample detection, configurable decoder, output registers algorithm description for each part, e.g. in C / Java detailed structure for different parts of system registertransfer complex modules and their data flow / communication register-transfer components and connections gate transistor differential equations transistors, resistors, wires, 02-7 Double-Roof-Model abstraction of Y/X-chart software hardware system module architecture block logic HW and SW design processes are equally structured

5 P-Chart dimension SW-Synthesis level system level algorithm level RT level view behaviour structure test geometry 02-9 Contents HW/SW Codesign Process Design Abstraction and Views Synthesis Control/Data-Flow Models System Synthesis Models CO mplex ncurrent rrect ordinated DESIGN

6 Synthesis software hardware behaviour system module architecture block logic structure synthesis = tasks for synthesis: allocation: select components binding: map functions to components scheduling: plan execution order Example behaviour: Boolean equation synthesis f ab cd structure: netlist a b c d & & 1 f

7 Specification on System Level constraints task graph A B D C execution time < 200ms E Allocation on System Level processor, dedicated hardware memory, I/O connection structures

8 Binding on System Level map tasks to resources A B C D E Scheduling on System Level

9 Rating of Design Alternatives : criteria can not be improved without worsen another 1, 2, 4, 6 are Contents HW/SW Codesign Process Design Abstraction and Views Synthesis Control/Data-Flow Models System Synthesis Models CO mplex ncurrent rrect ordinated DESIGN

10 Data Structures for algorithms (calculation l of optimisations) i are dedicated di d and formal models necessary data structures granularity detailing for optimisation parameters abstraction for manageability extendibility annotation by optimisation method output generation, if necessary for common optimisation Graph modelling by graphs graph G = (V,E), E V x V set of vertices (nodes) V: operation, tasks, communication set of arcs (edges) E: dependencies between nodes example: G = (V,E) V = (A, B, C, D, E) E = ((A,B), (A,C), (B,E), (C,D), (D,E)) directed graph (A,B) (B,A) B A E D C

11 Control and Data Flow Models possible dependencies d to model by data structure t data dependency control dependency (caused by implementation) important models data flow graph (DFG) control flow graph (CFG) system modelling graphs (later) Data Flow Graph (DFG) shows data dependencies between calculation or memory units (functions, variables, ALUs, ) directed edge, if a producer-consumer consumer relation between two nodes x = 3*a + b*b c; y = a + b*x; z = b c*(a + b);

12 Control Flow Graph (CFG) models control paths of algorithms directed graph with one start and one end node read(a,b) done = FALSE start instructions foo { read(a,b); done = false; repeat { if (a > b) a = a b; else if (b > a) b = b a; else done = true; } until done; write(a); } a = a-b a > b b > a b = b-a done!= TRUE write(a) done = TRUE true false branch end Contents HW/SW Codesign Process Design Abstraction and Views Synthesis Control/Data-Flow Models System Synthesis Models CO mplex ncurrent rrect ordinated DESIGN

13 Models for System Synthesis problem graph nodes: functional and communication objects edges: dependencies architecture graph nodes: functional and communication resources edges: directed communication paths specification graph problem graph + architecture graph Problem Graph communication nodes 4 DFG problem graph

14 Architecture Graph architecture architecture graph RISC RISC bus bus FPGA1 FPGA2 FPGA1 point-to-point link P2P communication resources FPGA Specification Graph weighting (different scenarios) RISC bus FPGA1 7 P2P 4 problem graph possible mapping FPGA2 architecture graph specification graph

15 Example HW/SW partitioning ( ) HW HW bus bus processor processor architecture architecture graph only two blocks (HW and SW)

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