System-on. on-chip Design Flow. Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems.

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1 System-on on-chip Design Flow Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems Jouni Tomberg / TUT 1

2 SoC - How and with whom? SoC Players Markets Flows Bottlenecks IP and platform metrics Jouni Tomberg / TUT 2

3 Definitions Frontend design Design from system level to cell library level netlist Backend design Design from netlist level to Placed & Routed production ready database ASIC flow Netlist handoff to ASIC vendor (takes care of the backend) COT (Customer Owned Tooling) flow P&R database handoff to foundry (takes care of the production) Jouni Tomberg / TUT 3

4 SoC Players IP provider Standard function blocks Customer (end user) IC's Requirement specification Production requirements ASIC vendor or Foundry Netlist or P&R database Design Service provider Physical backannotation Jouni Tomberg / TUT 4

5 Need for System Level Design Jouni Tomberg / TUT 5

6 Market Segments Jouni Tomberg / TUT 6

7 Design Productivity Gap Jouni Tomberg / TUT 7

8 Typical Design Flow Tasks System/ Algorithm Behavioral RTL Gate-level Transistor/ Physical Implement Define System Create/select Algorithms Filter design Protocol Development Create behavioral description Code generation Wordlength optimizatiuon Architectural Tradeoffs Partitioning Create RTL description Behavioral Synthesis Code generation Design Planning Create Netlist Optimize Netlist Logic Synthesis Datapath Synthesis Test Synthesis Power Optimization Retiming Create physical representation Place & Route Clock-tree synthesis Power Routing Transistor Optimization Verify Verify system function Verify Algorithm performance System Simulation HW/SW Coverification Verify behavioral description (function and performance) Simulation Testbench Generation HW/SW Coverifiication Verify RTL description (function and performance) Simulation Power Analysis RTL quality analysis Emulation Verify Netlist (function and performance) Simulation Equivalence Checking Static Timing Analysis Power Analysis Test Analysis/ATPG Verify physical design DRC, LVS Power analysis Rail analysis Static Timing analysis Parasitic Extraction Models/IP System model components System environments Reference Kits Behavioral models RAM Models Part models Bus Models Cores RTL models RAM models Part models Bus Models Cores (functional & timing Models) Gate models Bus Models Synthesis/simulation libraries Physical/transistor models Std Cell libraries Gate Array libraries Jouni Tomberg / TUT 8

9 Design Flows Design Flows Source: T. Moxon / EEDesign, Jouni Tomberg / TUT 9

10 ASIC design flow interfaces DESIGN TEAM CUSTOMER ASIC VENDOR Requirement spec Technical info for quotation ASIC quotation Data sheet for acceptance Library & tools Verification for acceptance (modeler/testbench/simul.results) Netlist, test vectors, arch.plan Backannotation from P&R Acceptance for prototype production (sign off) Prototype ASICs (/risk production) Prototype acceptance Mass production ASICs Jouni Tomberg / TUT 10

11 Importance of Specification Jouni Tomberg / TUT 11

12 Design Bottlenecks * Source EETIMES EDA 2000 Survey Simulation/Design Verification 51% Design Creation Place & Route 32% 32% Post Layout Optimization 26% Parasitic Extraction System or System-on-Chip Layout Versus Schematic(LVS) Design Rule Check (DRC) 17% 17% 17% Static Timing Analysis 16% Synthesis 15% Delay Calculation 13% Base = 545 0% 10% 20% 30% 40% 50% 60% % of project effort devoted to design verification! Jouni Tomberg / TUT 12

13 Verification Importance Jouni Tomberg / TUT 13

14 Project Scheduling External constraints Targeted market entry ASIC vendor Layout generation (P&R) Mask producing Prototype processing Prototype acceptance Volume production starting delay Design constraints Design team experience Design tools / flows, vendor libraries, IP provider quality System specification iterations Design complexity Verification complexity Production test complexity Jouni Tomberg / TUT 14

15 Differencies between SoC and SoPC design flows SoPC is a FPGA technology based user programmable solution P&R and programming done by the user (vs. backend flow in SoC) No delay on prototype production No delay on mass production start No NRE (production start) costs Production tests done by the IC vendor Design resource and time savings in the design flow Quick and cheap modifications On the other hand certain limitations on performance, integration capacity and mass production costs exists compared to SoC Jouni Tomberg / TUT 15

16 Platform Based Design A platform should consist of a basic set of integrated technologies that defines how the system should function. Design platform / Verification platform Generic platform CPU, memory and standard peripheral fucntions Application specific platform Generic platform plus pre-integrated IP blocks for the given application Jouni Tomberg / TUT 16

17 Platform drivers Source: B. Altizer, L. Cooke, and G. Martin / EEDesign Jouni Tomberg / TUT 17

18 Platform Advantages Reduce integration risk by insuring that all IP works together Reduce licensing and contractual negotiation time per project Reduce cost by allowing efficient reuse in multiple designs It is estimated that in the near future each SoC design will consist of 10 to 15 different IP blocks from 6 to 8 IP vendors Suppose 6 to 8 weeks per IP vendor for evaluation, negotiation and integration of IP into the system => with 8 different IP vendors this means 64 weeks of hidden cost Jouni Tomberg / TUT 18

19 IP Market Dynamics Design dynamics (Dataquest 2002) 30% of a designs are composed of reused circuitry 12% of reused circuit is from outside sources => 3.6% of circuitry is from third parties Contractual and legal issues Legal issues remain a huge bottleneck in the IP purchase process rights, responsibility, guarantee, business model VCX trying to address this bottleneck (with standard Ts &Cs) Evaluation of IP Deciding if a core is viable is biggest technical challenge in IP acquisition process. Opportunities in IP evaluation services Perceived instability of vendors.. Most IP vendors are small and vulnerable Partnerships and alliance can help to resolve perceived volatility ty Software replacing hardware Proliferation of processors in ICs Resulting in more functions being implemented in software SW/HW co-design! Jouni Tomberg / TUT 19

20 IP Market Metrics 46%CAGR 75% License Revenue 25% Royalty Revenue Jouni Tomberg / TUT 20

21 Conclusions The main players in the SoC design flow are Design team, IP provider, IC vendor (or Backend team + Foundry) Efficient SoC design flow is based on IP reuse and platform based design The major bottlenecks are in the test and verification area The system level (specification, HW/SW co-design) and layout level links to RTL design play also an important role in a fluent design flow Jouni Tomberg / TUT 21

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