Assuming all values are initially zero, what are the values of A and B after executing this Verilog code inside an always block? C=1; A <= C; B = C;

Transcription

1 B-26 Appendix B The Bsics of Logic Design Check Yourself ALU n [Arthritic Logic Unit or (rre) Arithmetic Logic Unit] A rndom-numer genertor supplied s stndrd with ll computer systems Stn Kelly-Bootle, The Devil s DP Dictionry, 98 Assuming ll vlues re initilly zero, wht re the vlues of A nd B fter executing this Verilog code inside n lwys lock? B5 C=; A <= C; B = C; Constructing Bsic Arithmetic Logic Unit B5 The rithmetic logic unit (ALU) is the rwn of the computer, the device tht performs the rithmetic opertions like ddition nd sutrction or logicl opertions like AND nd OR This section constructs n ALU from four hrdwre uilding locks (AND nd OR gtes, inverters, nd multiplexors) nd illustrtes how comintionl logic works In the next section, we will see how ddition cn e sped up through more clever designs Becuse the MIPS word is 32 its wide, we need 32-it-wide ALU Let s ssume tht we will connect 32 -it ALUs to crete the desired ALU We ll therefore strt y constructing -it ALU A -Bit ALU The logicl opertions re esiest, ecuse they mp directly onto the hrdwre components in Figure B2 The -it logicl unit for AND nd OR looks like Figure B5 The multiplexor on the right then selects AND or OR, depending on whether the vlue of Opertion is or The line tht controls the multiplexor is shown in color to distinguish it from the lines contining dt Notice tht we hve renmed the control nd output lines of the multiplexor to give them nmes tht reflect the function of the ALU The next function to include is ddition An dder must hve two inputs for the opernds nd single-it output for the sum There must e second output to pss on the crry, clled Since the from the neighor dder must e included s n input, we need third input This input is clled Figure B52 shows the inputs nd the outputs of -it dder Since we know Opertion Result FIGURE B5 The -it logicl unit for AND nd OR

2 B5 Constructing Bsic Arithmetic Logic Unit B-27 + Sum FIGURE B52 A -it dder This dder is clled full dder; it is lso clled (3,2) dder ecuse it hs 3 inputs nd 2 outputs An dder with only the nd inputs is clled (2,2) dder or hlf dder Inputs Outputs Sum Comments + + = two + + = two + + = two + + = two + + = two + + = two + + = two + + = two FIGURE B53 Input nd output specifiction for -it dder wht ddition is supposed to do, we cn specify the outputs of this lck ox sed on its inputs, s Figure B53 demonstrtes We cn express the output functions nd Sum s logicl equtions, nd these equtions cn in turn e implemented with logic gtes Let s do Crry- Out Figure B54 shows the vlues of the inputs when is We cn turn this truth tle into logicl eqution: = ( ) + ( ) + ( ) +( ) If is true, then ll of the other three terms must lso e true, so we cn leve out this lst term corresponding to the fourth line of the tle We cn thus simplify the eqution to = ( ) + ( ) +( ) Figure B55 shows tht the hrdwre within the dder lck ox for consists of three AND gtes nd one OR gte The three AND gtes correspond

3 B-28 Appendix B The Bsics of Logic Design Inputs FIGURE B54 Vlues of the inputs when is FIGURE B55 Adder hrdwre for the crry out signl The rest of the dder hrdwre is the logic for the Sum output given in the eqution on pge B-28 exctly to the three prenthesized terms of the formul ove for, nd the OR gte sums the three terms The Sum it is set when exctly one input is or when ll three inputs re The Sum results in complex Boolen eqution (recll tht mens NOT ): Sum = ( ) + ( ) + ( ) +( ) The drwing of the logic for the Sum it in the dder lck ox is left s n exercise Figure B56 shows -it ALU derived y comining the dder with the erlier components Sometimes designers lso wnt the ALU to perform few more simple opertions, such s generting The esiest wy to dd n opertion is to expnd the multiplexor controlled y the Opertion line nd, for this exmple, to connect directly to the new input of tht expnded multiplexor

4 B5 Constructing Bsic Arithmetic Logic Unit B-29 Opertion Result + 2 FIGURE B56 A -it ALU tht performs AND, OR, nd ddition (see Figure B55) A 32-Bit ALU Now tht we hve completed the -it ALU, the full 32-it ALU is creted y connecting djcent lck oxes Using xi to men the ith it of x, Figure B57 shows 32-it ALU Just s single stone cn cuse ripples to rdite to the shores of quiet lke, single crry out of the lest significnt it (Result) cn ripple ll the wy through the dder, cusing crry out of the most significnt it (Result3) Hence, the dder creted y directly linking the crries of -it dders is clled ripple crry dder We ll see fster wy to connect the -it dders strting on pge B-38 Sutrction is the sme s dding the negtive version of n opernd, nd this is how dders perform sutrction Recll tht the shortcut for negting two s complement numer is to invert ech it (sometimes clled the one s complement) nd then dd To invert ech it, we simply dd 2: multiplexor tht chooses etween nd, s Figure B58 shows Suppose we connect 32 of these -it ALUs, s we did in Figure B57 The dded multiplexor gives the option of or its inverted vlue, depending on Binvert, ut this is only one step in negting two s complement numer Notice tht the lest significnt it still hs signl, even though it s unnecessry for ddition Wht hppens if we set this to insted of? The dder will then clculte + + By selecting the inverted version of, we get exctly wht we wnt: + + = + ( + ) = + ( ) =

5 B-3 Appendix B The Bsics of Logic Design Opertion ALU Result ALU Result 2 2 ALU2 Result2 3 3 ALU3 Result3 FIGURE B57 A 32-it ALU constructed from 32 -it ALUs of the less significnt it is connected to the of the more significnt it This orgniztion is clled ripple crry The simplicity of the hrdwre design of two s complement dder helps explin why two s complement representtion hs ecome the universl stndrd for integer computer rithmetic A MIPS ALU lso needs NOR function Insted of dding seprte gte for NOR, we cn reuse much of the hrdwre lredy in the ALU, like we did for sutrct The insight comes from the following truth out NOR: ( + ) = Tht is, NOT ( OR ) is equivlent to NOT AND NOT This fct is clled DeMorgn s theorem nd is explored in the exercises in more depth Since we hve AND nd NOT, we only need to dd NOT to the ALU Figure B59 shows tht chnge

6 B5 Constructing Bsic Arithmetic Logic Unit B-3 Binvert Opertion Result + 2 FIGURE B58 A -it ALU tht performs AND, OR, nd ddition on nd or nd By selecting (Binvert = ) nd setting to in the lest significnt it of the ALU, we get two s complement sutrction of from insted of ddition of to Ainvert Binvert Opertion Result + 2 FIGURE B59 A -it ALU tht performs AND, OR, nd ddition on nd or nd By selecting (Ainvert = ) nd (Binvert = ), we get NOR insted of AND

7 B-32 Appendix B The Bsics of Logic Design Tiloring the 32-Bit ALU to MIPS These four opertions dd, sutrct, AND, OR re found in the ALU of lmost every computer, nd the opertions of most MIPS instructions cn e performed y this ALU But the design of the ALU is incomplete One instruction tht still needs support is the set on less thn instruction (slt) Recll tht the opertion produces if rs < rt, nd otherwise Consequently, slt will set ll ut the lest significnt it to, with the lest significnt it set ccording to the comprison For the ALU to perform slt, we first need to expnd the three-input multiplexor in Figure B58 to dd n input for the slt result We cll tht new input nd use it only for slt The top drwing of Figure B5 shows the new -it ALU with the expnded multiplexor From the description of slt ove, we must connect to the input for the upper 3 its of the ALU, since those its re lwys set to Wht remins to consider is how to compre nd set the lest significnt it for set on less thn instructions Wht hppens if we sutrct from? If the difference is negtive, then < since ( ) < (( ) + ) < ( + ) < We wnt the lest significnt it of set on less thn opertion to e if < ; tht is, if is negtive nd if it s positive This desired result corresponds exctly to the sign it vlues: mens negtive nd mens positive Following this line of rgument, we need only connect the sign it from the dder output to the lest significnt it to get set on less thn Unfortuntely, the Result output from the most significnt ALU it in the top of Figure B5 for the slt opertion is not the output of the dder; the ALU output for the slt opertion is oviously the input vlue Thus, we need new -it ALU for the most significnt it tht hs n extr output it: the dder output The ottom drwing of Figure B5 shows the design, with this new dder output line clled Set, nd used only for slt As long s we need specil ALU for the most significnt it, we dded the overflow detection logic since it is lso ssocited with tht it Als, the test of less thn is little more complicted thn just descried ecuse of overflow, s we explore in the exercises Figure B5 shows the 32-it ALU Notice tht every time we wnt the ALU to sutrct, we set oth nd Binvert to For dds or logicl opertions, we wnt oth control lines to e We cn therefore simplify control of the ALU y comining the nd Binvert to single control line clled Bnegte

8

9 B5 Constructing Bsic Arithmetic Logic Unit B-33 Ainvert Binvert Opertion Result Ainvert Binvert Opertion Result Set Overflow detection Overflow FIGURE B5 (Top) A -it ALU tht performs AND, OR, nd ddition on nd or, nd (ottom) -it ALU for the most significnt it The top drwing includes direct input tht is connected to perform the set on less thn opertion (see Figure B5); the ottom hs direct output from the dder for the less thn comprison clled Set (See Exercise 324 to see how to clculte overflow with fewer inputs)

10 B-34 Appendix B The Bsics of Logic Design Binvert Ainvert Opertion ALU Result ALU Result 2 2 ALU2 Result2 3 Result3 3 ALU3 Set Overflow FIGURE B5 A 32-it ALU constructed from the 3 copies of the -it ALU in the top of Figure B5 nd one -it ALU in the ottom of tht figure The inputs re connected to except for the lest significnt it, which is connected to the Set output of the most significnt it If the ALU performs nd we select the input 3 in the multiplexor in Figure B5, then Result = if <, nd Result = otherwise To further tilor the ALU to the MIPS instruction set, we must support conditionl rnch instructions These instructions rnch either if two registers re equl or if they re unequl The esiest wy to test equlity with the ALU is to sutrct from nd then test to see if the result is since ( = ) =

11 B5 Constructing Bsic Arithmetic Logic Unit B-35 Thus, if we dd hrdwre to test if the result is, we cn test for equlity The simplest wy is to OR ll the outputs together nd then send tht signl through n inverter: Zero = ( Result3 + Result3 + + Result2 + Result + Result) Figure B52 shows the revised 32-it ALU We cn think of the comintion of the -it Ainvert line, the -it Binvert line, nd the 2-it Opertion lines s 4- it control lines for the ALU, telling it to perform dd, sutrct, AND, OR, or set on less thn Figure B53 shows the ALU control lines nd the corresponding ALU opertion Ainvert Bnegte Opertion ALU Result ALU Result Zero 2 2 ALU2 Result2 Result3 3 3 ALU3 Set Overflow FIGURE B52 The finl 32-it ALU This dds Zero detector to Figure B5

12 B-36 Appendix B The Bsics of Logic Design ALU control lines Function AND OR dd sutrct set on less thn NOR FIGURE B53 The vlues of the three ALU control lines Bnegte nd Opertion nd the corresponding ALU opertions ALU opertion Zero ALU Result Overflow FIGURE B54 The symol commonly used to represent n ALU, s shown in Figure B52 This symol is lso used to represent n dder, so it is normlly leled either with ALU or Adder Finlly, now tht we hve seen wht is inside 32-it ALU, we will use the universl symol for complete ALU, s shown in Figure B54

13

14 324 [5] < B5> The ALU supported set on less thn (slt) using just the sign it of the dder Let s try set on less thn opertion using the vlues 7 ten nd 6 ten To mke it simpler to follow the exmple, let s limit the inry representtions to 4 its: two nd two two two = two + two = two This result would suggest tht 7 > 6, which is clerly wrong Hence, we must fctor in overflow in the decision Modify the -it ALU in Figure B5 on pge B- 33 to hndle slt correctly Mke your chnges on photocopy of this figure to sve time