RTL Power Optimization with Gate-level Accuracy

Transcription

1 RTL Power Optimiztion with Gte-level Accurcy Qi Wng Cdence Design Systems, Inc Sumit Roy Clypto Design Systems, Inc 555 River Oks Prkwy, Sn Jose Bunker Hill Lne, Suite 208, SntClr ABSTRACT Trditionl RTL power optimiztion techniques commit trnsformtions t the RTL sed on the estimtion of re, dely nd power. However, ecuse of indequte power nd dely informtion, the power optimiztion trnsformtions pplied t the RTL my cuse unexpected results fter synthesis, such s worsened dely or incresed power dissiption. Our solution to this prolem is to divide RTL power optimiztion into two steps, nmely RTL explortion nd gte-level commitment. During RTL explortion phse potentil cndidtes for pplying some specific RTL trnsformtion re identified where high level informtion permits fster nd more effective nlysis. These cndidtes re simply mrked on the netlist. Then during the gte-level commitment phse when ccurte power nd dely informtion is ville, the finl decision of whether ccepting or rejecting the cndidte is mde to chieve the est power nd dely trde-offs. 1. INTRODUCTION Power consumption hs ecome n incresingly importnt optimiztion metric in the design of microelectronic systems. Power optimiztion cn e chieved t different levels within design cycle, though it is well known tht the higher the level of strction where power optimiztion techniques re pplied, the higher the potentil power svings[1,2]. Clock-gte trnsformtion is proly y fr the most commonly used RTL power optimiztion technique[3]. In mny design situtions, dt is loded into registers infrequently, ut the clock signl continues to switch t every clock cycle, driving lrge cpcitive lod. This mkes the clock signl mjor source of dynmic power dissiption. Identifying periods of inctivity in the registers nd disling the clock during those periods cn sve significnt mounts of power [1,3]. However, clock gting is restricted to sving power on sequentil elements only. Figure 1.1 shows design where register nk tkes the result of the multiplier only s its input. The power dissipted y the multiplier is wsted during the cycle when the register nk is not loding the dt. Clock gting cnnot e used for this prolem since it only reduces the power of the register nk. One solution is to shut down the multiplier when its outputs re not used, s shown y the two nks of shded AND gtes in the Figure 1.2. This technique is known s opernd isoltion [5] or sleep-mode optimiztion. In Figure 1.2, the multiplier is clled sleep-mode cndidte; the signl e is clled the enle signl for the sleep-mode cndidte; nd the dded logic of AND gtes for turning off the multiplier re clled the sleep-mode logic. Sleep-mode trnsformtion of given design involves the tsks of identifying the set of sleepmode cndidtes nd the corresponding enles, nd mking decision on whether inserting the sleep-mode logic or not so tht e (1) (2) Figure 1. A design (1) without sleep-mode (2) with sleepmode trnsformtion. power cn e optimized under some constrints such s dely or re. 2. Relted Work In [4], control-signl gting technique is proposed to reduce the switching ctivities on dtpth uses. The ide is to use oservility don t cre conditions of uses to gte control signls going to the us driver modules so tht the switching ctivity on the module inputs does not propgte to the us. Unlike the sleepmode trnsformtion, the proposed method does not work for dtpth uses or modules which re not driven y registers. The other prolem of the method is tht it computes oservility don t cre sed on the structurl netlist of design, which my e very expensive or even prohiitive on rel designs with intensive dtpth elements. To the est of our knowledge, work of [5] presents the first comprehensive pproch tht utomtes sleep-mode (opernd isoltion) on RTL netlist. Unlike the work in [4], this pper presents complicted RTL power model to estimte the power svings y introducing the sleep-mode logic. Additionlly, rther thn using n existing signl for the enle signl for the sleepmode logic, new function is used nd computed y structurl nlysis of the trnsitive fnout of module. The work of [6] is different from ove introduced techniques in tht it chieves power sving y redesigning control logic to reconfigure the existing dtpth components under idle conditions. The drwck of this technique is tht it works well on control-flow intensive designs ut not on dt-flow intensive designs. Additionlly, the technique my significntly chnge the finl netlist to reduce power. This my not e fvored in rel industril designs when power is secondry optimiztion trget s compred to dely in most design situtions. All ove solutions suffer from common prolem: committing n optimiztion move t the RTL in hopes of sving power fter logic nd physicl optimiztion. It is well known tht power estimtions t RTL cn significntly differ from the rel chip power or even gte level power estimtions [2,3]. Since there is no ccurte power nd timing informtion ville t RTL to perform the correct trde-off, these solutions my end up e Permission to mke digitl or hrd copies of ll or prt of this work for personl or clssroom use is grnted without fee provided tht copies re not mde or distriuted for profit or commercil dvntge nd tht copies er this notice nd the full cittion on the first pge. To copy otherwise, to repulish, to post on servers or to redistriute to lists, requires prior specific permission nd/or fee. ICCAD 03, Novemer 11-13, 2003, Sn Jose, Cliforni, USA. Copyright 2003 ACM /03/ $

2 incresing the ctul power or dely of the synthesized netlist. Even if some provides cpility to undo the trnsformtions t the end of the synthesis run[5], the optimizer hs lredy spent lot of effort optimizing the wrong criticl pths which re mostly not reversile. This my cuse extr long run time or, design with worse power nd timing compred to the one without pplying the RTL trnsformtion. In this pper, we present novel solution to solve the ove prolem. This unique pproch consists of two steps, nmely RTL explortion nd gte-level commitment. First, during RTL explortion, we use the Control Dt Flow Grph (CDFG) generted from the RTL description of design to identify ll the sleep mode trnsformtion cndidtes, including the enle signls for ech cndidte. The enle signl is computed y performing ehviorl level oservility nlysis (BLOA) on CDFG, s to e descried in Section 3. Since CDFG contins ll high-level informtion (control nd dt flow), we re le to identify ll possile sleep-mode trnsformtion opportunities presented in design. More importntly, since the enle signls re computed directly from the control flow, it elimintes the concern tht some enle signls my e synthesized into some other logic during synthesis, thus losing the opportunity of ny possile trnsformtions ssocited with the signl. After identifying ll the cndidtes, we mrk the gte level netlist to "rememer" these potentil trnsformtions without ltering the dt pth or the control pth of the design. Noticely, ecuse the originl dt nd control pths of the design re mintined, the logic nd timing optimiztion pplied lter will work on the true criticl pth nd no effort is wsted. After logic nd timing optimiztion hs een completed, ech "mrk" of the potentil sleep mode trnsformtion will e evluted nd committed or removed to mke sure it sves power without violting timing or re constrints. This is referred s gte-level commitment in the pper. It needs to e pointed out tht ecuse of the vilility of ccurte power nd timing informtion t this stge ny decision mde t this point reflects the rel sttus of the design. In ddition to the improved ccurcy, the complexity of the lgorithm is significntly reduced since no complicted nd error-prone RTL power nd dely models re required. It needs to e noted tht we re not proposing new RTL power trnsformtion. Insted, we re proposing new pproch on how to pply the RTL power trnsformtion known s opernd isoltion or sleep-mode trnsformtion. With the seprtion of RTL explortion nd gte-level commitment, the proposed pproch tkes the dvntge of oth rich control-dt-flow informtion t the RTL nd the ccurte power nd dely informtion t the gte-level so tht the est possile power dely trdeoff cn e chieved. Our technique gurntees tht design with sleep-mode trnsformtions inserted hs less power nd sme or etter timing compred to design without the trnsformtions without significnt run time overhed on the existing timing optimiztion flow. 3. Behviorl Oservility Anlysis Oservility nlysis in logic circuits hs een widely used in logic synthesis, test genertion, nd mny other ECAD prolems [8]. In this section, we extend the ide of oservility nlysis to the ehviorl level description of digitl system, i.e. CDFG. It is referred s ehviorl level oservility nlysis (BLOA) for the rest of the pper Introduction of CDFG A CDFG is grphicl representtion of the ehviors of digitl hrdwre. The grph is generted from hrdwre ehviorl description lnguges, such s Verilog or VHDL, nd serves s n interfce to different RTL nd rchitecturl synthesis pckges. More detils out CDFG cn e found in [7]. A CDFG consists of nodes nd directed edges. The nodes represent opertions in the ehviorl description. The edges model the trnsfer of vlues etween the nodes, i.e. the result of one opertion (node) is pssed to the rgument of nother one. Every rgument of n opertion cn e seen s n input port of the corresponding node of the CDFG. Every result of n opertion cn e seen s n output port of the corresponding node of the CDFG. A token is defined s single dt vlue instnce. There re four mjor types of nodes. i 0 i 1 i k-1 n op c i n rnch i 0 i 1 i k-1 n merge n cons o 0 o 1 o j-1 o 0 o 1 o j-1 o o 0 o 1 o j-1 () () (c) (d) Figure 2. CDFG nodes. () Opertion node () rnch node (c) merge node (d) construct node. ) Opertion nodes: Opertions cn e rithmetic, like +,-,,, or Boolen, like,, or cn e more complex functions or n instntition of nother grph, which models the procedures nd functions in the ehviorl specifiction. The grphicl representtion of n opertion node n op with input edges i 0 to i k-1 nd output edges o 0 to o j-1 is shown in Figure 2.. The node performs the opertion defined y n op on the dt vlues of the input edges nd trnsfer the result to ll output edges. ) Brnch nodes: A rnch node hs two input ports, control port nd dt port, nd t lest one output dt port. Bsed on the vlue of token on the control port, one nd only one output port is selected nd the token on the input dt port is pssed to the selected output port. The grphicl representtion of rnch node n rnch with input dt edge i nd input control edge c nd output edge o 0 to o j-1 is shown in Figure 2.. For exmple, if the dt vlue on the control edge c is 0, then the dt vlue on the input edge i is trnsferred to the output edge o 0. c) Merge nodes: Merge nodes re dul to rnch nodes. A merge node hs one output dt port, one input control port nd severl input dt ports. It psses the token on one input dt port, selected y the vlue of the token on the control port, to the output port. The grphicl representtion of merge node n merge with input dt edges i 0 to i k-1 nd input control edge c nd output edge o which is shown in Figure 2.c. For exmple, if the dt vlue on the control edge c is 0, then the dt vlue on the input edge i 0 is trnsferred to the output edge o. d) Construct nodes: These re specil nodes, which only serve the purpose to generte tokens to control the rnch nd merge nodes. It hs one input dt port nd t lest one output control ports. Only one output port is selected to pss the token from the input port ccording to the vlue of the token. The grphicl representtion of merge node is shown in Figure 2.d. c i

3 Other types of nodes include input, output, register nd constnt nodes. Every grph requires t lest one input node nd one output node. Constnt nodes re nodes which generte constnt dt vlue t their single output port. Input, output nd register nodes correspond to input, output ports nd registers of the design represented y the CDFG respectively. 3.2 Oservility of CDFG Nodes nd Edges A token in CDFG is the counterprt of signl in logic circuit. In the rest we refer to the ehviorl level oservility nlysis s the token oservility nlysis on CDFG. Definition 1: token oservle condition (TOC) of n edge e ij, denoted y TOC(e ij ), is the condition under which the token on tht edge cn e oserved t one or more output nodes of CDFG. Definition 2: node oservle condition (NOC) of node n i, denoted y NOC(n i ), is the condition under which the token on ny output edge of the node cn e oserved t one or more output nodes of CDFG. Given CDFG, the TOC nd NOC for ll edges nd nodes cn e computed y trversing the grph from the output nodes to the input nodes nd pplying pproprite Boolen opertions. Let,, nd denote the Boolen AND, OR, inversion opertions respectively. For ech different type of node, the TOCs of ll edges nd NOCs of ll nodes re computed s follows. 1) Output nodes: By definition, for n output node n out with input edge i, NOC(n out ) = 1, TOC(i) = 1 2) Opertion nodes: For n opertion node n op such s the one in Figure 2. with input edges of i 0,, i k-1 nd output edges of o 0,, o j-1, we hve NOC(n op ) = TOC(o 0 ) TOC(o 1 ) TOC(o j-1 ) TOC(i p ) = NOC(n op ), p {0, 1,, k-1} For the ske of TOC/NOC nlysis, input nd construct nodes re treted the sme s opertion nodes. 3) Brnch nodes: For rnch node n rnch s shown in Figure 2., with input dt edge of i nd input control edge of c nd output edges of o 0,, o j-1, we hve NOC(n rnch ) = TOC(o 0 ) TOC(o 1 ) TOC(o j-1 ) TOC(c) = NOC(n rnch ) TOC(i) = ( c 0 TOC(o 0 )) (c 1 TOC(o 1 )) (c j-1 TOC(o j-1 )) where c p, p [0,j-1] is Boolen encoding of the vriles for the vlue of the token t the control port to select output port p. For exmple, if the token on c is two it wide (c= c 1 c 0 ) nd output port 2 is selected, i.e. c is (10) in inry, then the condition to select port is c 1 c 0. 4) Merge nodes: For merge node n merge s shown in Figure 2.c, with input dt edges of i 0,, i k-1 nd input control edge of c nd output edge of o, we hve NOC(n merge ) = TOC(o) TOC(c) = TOC(o) TOC(i p ) = c p TOC(o), p [0,k-1] The definition of c p is the dul to tht descried for rnch nodes, i.e. the condition under which the input port p is selected y n merge to pss the token to the output port. As in [5], to void the computtionl complexity we ssume the NOC of register node to e 1. In other words, we do not nlysis oservilities cross register oundry Computtion of TOC/NOC Computing TOC/NOC requires Boolen opertions. A common wy to perform Boolen opertions is to use BDD (Binry Decision Digrm [9]). The prolem of this pproch is tht BDD is not roust enough to hndle lrge Boolen functions. In this section, n efficient nd yet simple pproch to compute TOC/NOC of CDFG is proposed. The ide of the pproch is the seprtion of trversing CDFG nd computing TOC/NOC. Insted of uilding BDD for the TOC/NOC of ech edge nd node, logic network is constructed whenever Boolen opertion is required to compute the TOC/NOC. The logic network is then optimized using trditionl logic optimiztion techniques such s lgeric trnsformtions [8], to otin the optimized Boolen function of the TOC/NOC. The trnsformtions used in the optimiztion process re chosen to e simple enough so tht computing TOC/NOC will e lmost invisile to the overll optimiztion flow. This method is idel for the front-end RTL synthesis tool where CDFG is trnslted into gte level netlist nd there exists one-to-one correspondence etween the ojects of CDFG nd the ojects of the logic network. The method is est explined y n exmple. clk register output in1 in2 cmp en N2 N3 N4 N1 construct E1 E2 N8 2 N5 N9 == N11 E3 E4 + N12 E5 N13 E6 N14 E7 N15 E8 N16 N10 construct Figure 3. An exmple CDFG In Figure 3, the CDFG of simple digitl system is shown. As stted ove, fter gte level netlist is generted from this CDFG, there is n one-to-one correspondence etween the ojects of CDFG nd the ojects of the generted logic network. For exmple, let e the corresponding signl for node N1 nd e the corresponding signl for node N10 in the netlist. We will explin the computtion of TOC for edges E1 nd E2 in Figure 4. The computtion strts from the output nodes using the formuls in the Section 3 depended on the type of the node visited. It is esy to see the TOC of edges E8 nd E7 is simply logic 1, s highlighted in Figure 4. For edge E6, the TOC is the Boolen AND of the TOC of E7 nd the vrile of the control port of the

4 E8,E7 1 c E6 d E5,E4 e E3,E2,E1 in1 SleepControlModule_0 Figure 4. Compute TOC for edges of CDFG in Figure 3. node N14 which is the sme s the vrile t the output port of construct node N1. Therefore in Figure 4 the AND gte c is constructed whose output represents the TOC of E6. Similrly, the TOC of edge E5 is the AND of TOC of edge E6 nd the vrile of the control port of node N13. The AND gte d is creted for the TOC of edge E5. The process continues until the edges E1 nd E2 re reched. As shown in Figure 4, the output of the AND gte e represents the TOC of edges E2 nd E1. After pplying simple logic optimiztions, the TOC of edges E1, E2 nd E3 is simply the AND of nd. Note tht only single trversl from the output nodes to the inputs is required to compute the TOCs of these edges. The complexity of the lgorithm is O( V + E ) where V nd E re the numer of nodes nd edges of CDFG respectively. In our experience, the numer of nodes nd edges of CDFG is much less thn those of the corresponding structurl netlist. As result, the proposed technique for TOC/NOC computtion is extremely fst even for very ig stte-of-rt digitl designs. 4. Proposed Sleep-mode Trnsformtions As descried erlier, the proposed sleep-mode trnsformtion consists of two steps, nmely RTL explortion nd gte-level commitment. 4.1 RTL Explortion The ppliction of BLOA techniques introduced in Section 3 to sleep-mode trnsformtion is strightforwrd. The corresponding logic of n opertion node is perfect cndidte for sleep-mode trnsformtion where the computed TOC/NOC cn e used to generte the corresponding enle signl. Nodes with TOC equl to 1 cn not e cndidtes for sleep mode trnsformtion ecuse the outputs of the corresponding logic lock re lwys oservle. During the explortion phse, complete BLOA is performed on the CDFG. Opertion nodes with NOC not equl to 1 re selected s cndidtes. These cndidtes re then mrked on the gte-level netlist. No ctul implementtion is performed in this phse. Commitment of these trnsformtions is delyed fter gte-level optimiztion hs een done where ccurte power nd timing informtion is ville. For exmple, BLOA nlysis of the design shown in Figure 3 finds tht under the condition of & the outputs of the multiplier (node N5) re not used, where nd re the signls in the netlist corresponding to the condition represented y construct node N1 nd N10 respectively. The netlist of the design fter RTL explortion is shown in Figure 5. Compred to the norml netlist fter RTL synthesis, the RTL sleep-mode explored netlist hs two new inserted modules clled SleepModeModule, one in front of ech multiplier input. The inserted modules hve following chrcteristics. First the dt us is feed-through within the module. Second, within the SleepModeModule,, there is nother module clled SleepModeControlModule. It contins the complex in2 SleepControlModule_1 SleepModeModule_1 Figure 5. Netlist fter RTL sleep-mode explortion for the multiplier of the exmple in Figure 3. enle function for the sleep-mode cndidte. In this cse, it is the AND function of nd. There exists one-to-one correspondence etween the input pins of the SleepModeControlModule nd the input ports of the SleepModeModule, ut they re not connected. The SleepModeModule serves s the mrk for the cndidte of sleep-mode trnsformtion, which is the multiplier in this cse. Note tht even though the multiplier hierrchy my e dissolved during synthesis, the mrk for the sleep-mode cndidte will e preserved, ecuse the SleepModeModule is not dissolved, which could e esily done. The SleepModeControlModule serves s the vehicle to rememer the enle logic for this cndidte. The oneto-one correspondence imposed y pin nmes etween the input ports of the SleepModeModule nd inputs of the SleepModeControlModule is required during the committing phse where the enle logic is ctully connected. Becuse no extr lod is dded to the control nd the dt pth, the criticl pth of the originl design will e preserved. As result, the lter logic nd timing optimiztion will e le to focus on the rel criticl pth nd optimize the netlist s if no sleep-mode trnsformtions re performed. Therefore, s long s the sleepmode cndidtes re not committed, there is no concern tht the they my cuse new timing violtions when the originl design meets timing fter logic nd timing optimiztion. Another dvntge of the technique is tht it llows only portion of the enle function to e used s the enle logic for the sleep-mode cndidte during the gte-level commitment phse, known s prtil sleep-mode committing. 4.2 Gte-level Commitment After logic nd timing optimiztion, decision to commit ech individul cndidte is mde sed on whether or not the power is reduced without violting the timing constrints. The lgorithm is shown in Figure 6. First, we sort ll sleep mode cndidtes sed on the potentil power svings. The commitment strts from the sleep-mode cndidte which hs the iggest potentil power svings. Then for ech selected cndidte, the input ports of SleepModeModule nd the input pins of SleepModeControlModule tht hve the sme nme re connected. The ctul gting logic is inserted nd n incrementl power nd timing nlysis is performed. If the gte level 42

5 Prtilly committing 1. Connect Inside of SleepModeModule 2. Insert AND gtes 3. Power sved nd timing met? N 4. Is enle logic reducile? Y 5.Reduce enle logic to improve timing Fully committing N Y 7. Stop 6. Remove ll inserted logic nd hierrchies enle logic y executing steps 3 through 5 (in Figure 6). In this exmple, we know tht the enle logic for this cndidte is &. This mens tht either or cn lso e used s the enle logic. Since we do not wnt to e prt of the enle function ecuse of timing violtion, we cn use s the enle logic for input us in2. In other words, y removing the input of from the originl enle function, the new enle function is reduced from & to. Note tht prtil commitment is possile ecuse the enle logic nd the inputs for ech sleep mode cndidte re seprtely derived during RTL synthesis nd preserved fter logic nd timing optimiztion. As shown in Figure 6, the prtil committing loop stops when the enle logic cnnot e reduced further. The prtil commitment cpility of the proposed pproch differs significntly from the trditionl pproch where, if sleep mode trnsformtion violtes timing constrints, it is completely removed. Our pproch provides much lrger scope to perform power dely trde-offs. Finlly, if committing sleep-mode cndidte cuses power increse or timing violtion even fter prtil committing, we cn simply un-commit the sleep-mode cndidte y removing ll inserted logic on the control nd dt pth, nd then dissolve the inserted hierrchicl modules. Figure 6. Gte level sleep-mode commit lgorithm. commitment succeeds t step 3, then it is clled fully committed. Tht is, whtever cndidtes nd enle logic identified t RTL is fully committed to sve power without violting timing constrints. For exmple, to fully commit the sleep-mode modules inserted in Figure 5, we cn simply connect the control portion of the circuit within the SleepModeModule nd insert AND gtes on the dt signls, s shown in Figure Gte-level Prtilly Committing However, the full commit my cuse new timing violtions. For exmple, let s ssume tht fter fully committing ll sleep-mode modules, the pth from to the second input of multiplier violtes timing constrints, s highlighted in Figure 7. To void the newly introduced timing violtion, one solution is to completely remove the sleep-mode logic t input in2 of the multiplier, ut doing this will significntly limit the power reduction tht cn e chieved. A much etter solution is to prtilly commit the sleep-mode SleepModeModule_0 5. Flow Integrtion nd Implementtion The proposed RTL power optimiztion technique cn e semlessly integrted into ny existing design flow. The RTL explortion cn e dded t the end of norml RTL synthesis, nd the gte-level commitment cn e dded fter timing optimiztion completes. Existing flow needs no modifiction to pply the technique. More importntly, the seprtion of RTL explortion from gte-level elimintes possile itertions etween the RTL nd the gte level tht cn occur in trditionl pproches. In trditionl pproches, it is possile tht timing constrints cn not e met even y undoing ll the sleep-mode trnsformtions fter gte level optimiztion, ecuse they my hve shifted the criticl pths. This is not prolem for the proposed technique ecuse the decision for commitment of cndidte is delyed until the circuit hs een optimized for timing. At this stge, the ccurte power nd dely estimtion cn e esily otined from the gte level power nd timing nlysis engine. As result, ech commitment mkes sure tht it sves power without violting timing constrints. The dely of the circuit fter gte-level committing is gurnteed to e no worse thn the dely of the RTL elortion sleep-mode explortion in1 in2 SleepModeModule_1 Figure 7. Netlist fter gte-level sleep-mode full commitment for the exmple in Figure pre-plcement gte level optimiztion sleep-mode commitment physicl synthesis plce & route Figure 8. Flow integrtion

6 # Inst. Slck Tot. Pow. DP Power (ns) (mw) (mw) (%) circuit efore committing. Finlly, since the decision of sleepmode commitment is delyed to gte-level, it elimintes the need for complicted nd generlly inccurte RTL power nd dely models [5]. The proposed lgorithm is implemented in Cdence PKS/LPS 5.0 relese [10]. As shown in Figure 8, the stndrd flow consists of locks with no shdes nd the sleep-mode flow includes the two shded oxes. The flow strts from the RTL of design. During RTL explortion, sleep-mode logic is inserted ut not fully connected. After norml flow of pre-plcement timing nd dtpth optimiztion, including resource shring nd opertor merging [10], it then strts the gte-level commitment phse of the sleep-mode trnsformtion. This is done efore the physicl plcement of the design. The reson we do not perform the commitment phse fter plcement ecuse the commitment phse my introduce significnt mount of new logic which could cuse the incrementl plcement filure. The sign-off qulity power nd timing nlysis engine provided y PKS re used to compute the power nd dely (Step 3 of Figure 6) ccurtely in the commitment phse. More specificlly, fter insertion of the gting logic (Step 2 of Figure 6), the PKS/LPS incrementl power nd timing nlysis engine is used to otin the ccurte power nd dely informtion to compre it with the power nd dely informtion efore the trnsformtion. If power is reduced nd dely is not worsened, the sleep-mode trnsformtion will then e ccepted nd committed into the netlist. Otherwise, the sleepmode logic is removed. In other words, the dely nd power penlty due to the inserted gting logic is considered during the commitment phse. 6. Experiment Results Six industril circuits were chosen for experiments. Design 4 is microprocessor, Design 5 nd 6 re communiction chips. The types of the rest circuits re unknown. All designs except Design 6 hve customer provided test enches, which were used to simulte the circuit to get the switching ctivities for power nlysis. For Design 6, rndom input ptterns were used to simulte to otin the switching ctivities for power nlysis. Tle 1 shows the chrcteristics of ech design. The column Inst shows the numer of instnces of the design. The columns Slck nd Tot. Pow re the slck nd power dissiption of the design fter norml synthesis nd optimiztion. The lst column DP Power shows the totl dt-pth component power nd its percentge of the totl power in column Tot. Pow. Since sleepmode trnsformtions trget only for power optimiztion on these RTL Explortion SM cnd. CPU SM Comm Gte-level commitment Slck Pow. (ns) Sved D % D % % 16.3% D % D % % 6.4% D % D % % 20.0% D % D % % 4.1% D % D % % 14.7% D % D % % 23.5% Tle 1. Designs used for experiments Tle 2. Experimentl results with proposed method 44 CPU locks, in the experiment, we only use the power of these locks to show the power svings of the proposed technique. The experimentl results re shown in Tle 2. Column SM cnd. shows the numer of sleep-mode cndidtes identified during RTL explortion. The second column CPU shows the run time increse in percentge of sleep-mode RTL explortion compred to tht of norml RTL elortion. The results show tht the RTL explortion is very efficient nd introduces lmost no dditionl computtion time. Column SM comm. shows the numer of sleep-mode cndidtes committed in the gte-level commitment phse. Column Slck shows the slck fter gte level optimiztion. Column Pow. Sved shows the totl power sved s percentge of the dtpth power, s shown in Column 5 in Tle 1. The lst column shows the CPU run time of the gtelevel commitment s percentge of the totl run time of the norml gte level optimiztion. The re increse due to the finl inserted sleep-mode modules re not shown ecuse the mximum re overhed mong ll designs is less thn 1%. Since the proposed method will not modify the originl timing pth fter RTL explortion nd the commitment of ech sleep-mode logic is delyed fter timing optimiztion, the timing optimiztion will work s if there is no sleep mode logic inserted. The trget slck of gte level optimiztion for ech design is 0. For designs with negtive slck in Tle 1, the finl slck fter gte level commitment is not worse thn tht in Tle 1. For designs with positive slck in Tle 1, the finl slck is smller ut not less thn 0 fter the gte level commitment. The power svings cn e chieved strongly depend on the timing constrints, the switching ctivities of the enle function, nd the power dissiption of the dt pth locks. For exmple, in Design 2, most of the sleep-mode cndidtes re not committed t the gte level ecuse the proilities of enle signls re close to 1 which leves little room for power svings. For Design 6, most of the sleep-mode cndidtes re not committed due to the tight dely constrint. As comprison we did nother set of experiments. In these experiments, fter RTL explortion, we simply mp the netlist without ny other optimiztion nd commit the sleep-mode cndidtes sed on the power nd dely informtion otined t this level. This is similr to the trditionl pproch [5] where the sleep-mode trnsformtions re committed sed on RTL power nd dely estimtion. The results re shown in Tle 3. The column SM inserted shows the numer of sleep mode logic inserted. The column slck shows the slck fter timing optimiztion. The column power sved shows the dtpth power sved in percentge compred to the netlist without ny sleep-

7 SM Inserted Slck (ns) power sved CPU overhed D % 0.98 D % 1.01 D % 1.63 D % 0.96 D % 1.57 D % 2.10 Tle 3. Results of committing cndidtes t RTL mode inserted, column 5 of Tle 1. The column of CPU overhed is the rtio of the totl CPU time of this experiment to the CPU time using the proposed technique. Compre the Tle 2 nd 3 we cn see tht for Design 1, 2 nd 4, the results re very similr. However, the results of Design 3, 5 nd 6 from Tle 2 re much etter thn those from Tle 3. For exmple, for Design 6 in Tle 3, lot of sleep mode cndidtes re committed sed on the inccurte power nd dely informtion. Unfortuntely, it ws found during timing optimiztion tht most of the inserted sleep-mode logic ecome prt of the timing criticl pths nd significntly worsen the performnce of the design. Therefore the timing optimiztion spends significntly more run time nd gte resources to improve the slck. As result, the finl design consumes more power thn the one without the sleep-mode trnsformtions nd misses the timing trget. Overll, for Design 6, the proposed method chieved 4.3% power svings with no degrdtion of circuit dely nd the trditionl method produced finl netlist with more power, worst dely nd rn twice slower. To show the roustness of the proposed technique in terms of chieving est power delys trde-offs, we select Design 6 to run gte-level commitment with different nd relxed timing constrints. The result is shown in Tle 4. Ech row shows the experimentl results with different set of timing constrints. Row 1 shows the results with the originl timing constrints. Rows 2 to 4 show the results with the relxed timing constrints. The column Relxed constr. shows the degree of the relxtion of timing constrints in percentge. It cn e seen tht, for Design 6 when the timing constrint is relxed, more sleep-mode cndidtes cn e committed t the gte level nd significnt more power svings, s much s 45%, cn e chieved. The results show tht the chievle power svings of the proposed technique re mostly ounded y the timing constrints nd the switching ctivities of the enle signls. The lower the ctivities of the enle signls nd the looser the timing constrints, the more power reduction cn e chieved. Given the specified timing constrints, the proposed technique will pply the sleep-mode trnsformtions to sve the most power without worsening the timing. Relxed constr. SM Inserted power sved not relxed 0% % relxed 1 25% % relxed 2 50% % relxed 3 100% % Tle 4. Results of Design 6 with relxed timing constrints 7. Conclusion nd Future Work In this pper we propose new pproch to pply known RTL power optimiztion technique to chieve the est possile power dely trde-offs. The concept of reking the optimiztion into two steps, i.e. RTL explortion nd gte-level commitment, hs lot of dvntges over trditionl techniques s shown in the experimentl results. First, it hs little impct on the norml logic nd timing optimiztion ecuse ll sleep-mode modules inserted fter RTL explortion preserve the originl connectivity nd lods of the dt nd control pths of the design. Therefore the run time nd finl slck of timing optimiztion re the sme s if there is no sleep-mode logic inserted. This mkes the proposed technique very prcticl for current min strem design methodology where the first design trget is timing nd power is normlly secondry concern. Secondly, since the committing of the sleep-mode is delyed until the design is timing optimized, ccurte power dely trde-off cn e chieved given the exct timing nd power informtion ville t tht point. Finlly it hs the cpility of prtil committing of the sleep-mode modules which leds to much lrger solution spce eing explored to chieve the optiml power nd dely trde-off. Overll, no itertion etween RTL nd gte-level optimiztion required to chieve timing closure nd sve power when using the proposed technique. The experimentl results show tht the proposed method cn chieve meningful power svings with no impct on existing norml timing optimiztion t ll where the trditionl methods my produce design with worse timing nd power nd longer run time. Currently we re working on pply the sme concept to other RTL power trnsformtions such s clock gting. 8. REFERENCES [1] A.P. Chndrksn nd R. W. Brodersen, Low Power Digitl CMOS Design, Kluwer Acdemic Pulishers, [2] K. Keutzer nd P. Vnekergen, The Impct of CAD on the Design of Low Power Digitl Circuits [3] M. Pedrm, Power Minimiztion in IC Design: Principles nd Applictions, ACM Trnsctions on Design Automtion of Electronics Systems, Jnury 1996, Vol 1-1, pp [4] H. Kpdi, L. Benini, nd G. De Micheli, Reducing Switching Activity on Dtpth Buses with Control-Signl Gting, IEEE Journl of Solid-Stte Circuits, Vol. 34, No. 3, Mrch 1999, pp [5] M. Munch, nd et. l., Automting RT-Level Opernd Isoltion to Minimize Power Consumption in Dtpths, Proceedings of Design nd Test Automtion Conference in Europe. [6] S. Dey nd et. l., Controller-Bsed Power Mngement for Control-Flow Intensive Designs, IEEE Trns. on Computer-Aided Design of Integrted Circuits nd Systems, Vol. 18, No. 10, Octoer 1999, pp [7] J. vn Eijndhoven, G. de Jong, nd L. Stok. The ASCIS dt flow grph: semntics nd textul formt. Technicl Report EUT-Report 91-E-251, Eindhoven University of Technology, Eindhoven, Netherlnds, June [8] De Micheli. Synthesis nd Optimiztion of Digitl Circuits. McGrw-hill, Inc., [9] R. Brynt. Grph-sed lgorithms for oolen function mnipultion. IEEE Trnsctions on Computers, C-35(8): , Aug [10] Cdence Low Power Synthesis (LPS) User s Guide for Cdence PKS. 45