RTL Power Optimization with Gatelevel Accuracy


 Ellen Short
 1 years ago
 Views:
Transcription
1 RTL Power Optimiztion with Gtelevel Accurcy Qi Wng Cdence Design Systems, Inc Sumit Roy Clypto Design Systems, Inc 555 River Oks Prkwy, Sn Jose Bunker Hill Lne, Suite 208, SntClr ABSTRACT Trditionl RTL power optimiztion techniques commit trnsformtions t the RTL sed on the estimtion of re, dely nd power. However, ecuse of indequte power nd dely informtion, the power optimiztion trnsformtions pplied t the RTL my cuse unexpected results fter synthesis, such s worsened dely or incresed power dissiption. Our solution to this prolem is to divide RTL power optimiztion into two steps, nmely RTL explortion nd gtelevel commitment. During RTL explortion phse potentil cndidtes for pplying some specific RTL trnsformtion re identified where high level informtion permits fster nd more effective nlysis. These cndidtes re simply mrked on the netlist. Then during the gtelevel commitment phse when ccurte power nd dely informtion is ville, the finl decision of whether ccepting or rejecting the cndidte is mde to chieve the est power nd dely trdeoffs. 1. INTRODUCTION Power consumption hs ecome n incresingly importnt optimiztion metric in the design of microelectronic systems. Power optimiztion cn e chieved t different levels within design cycle, though it is well known tht the higher the level of strction where power optimiztion techniques re pplied, the higher the potentil power svings[1,2]. Clockgte trnsformtion is proly y fr the most commonly used RTL power optimiztion technique[3]. In mny design situtions, dt is loded into registers infrequently, ut the clock signl continues to switch t every clock cycle, driving lrge cpcitive lod. This mkes the clock signl mjor source of dynmic power dissiption. Identifying periods of inctivity in the registers nd disling the clock during those periods cn sve significnt mounts of power [1,3]. However, clock gting is restricted to sving power on sequentil elements only. Figure 1.1 shows design where register nk tkes the result of the multiplier only s its input. The power dissipted y the multiplier is wsted during the cycle when the register nk is not loding the dt. Clock gting cnnot e used for this prolem since it only reduces the power of the register nk. One solution is to shut down the multiplier when its outputs re not used, s shown y the two nks of shded AND gtes in the Figure 1.2. This technique is known s opernd isoltion [5] or sleepmode optimiztion. In Figure 1.2, the multiplier is clled sleepmode cndidte; the signl e is clled the enle signl for the sleepmode cndidte; nd the dded logic of AND gtes for turning off the multiplier re clled the sleepmode logic. Sleepmode trnsformtion of given design involves the tsks of identifying the set of sleepmode cndidtes nd the corresponding enles, nd mking decision on whether inserting the sleepmode logic or not so tht e (1) (2) Figure 1. A design (1) without sleepmode (2) with sleepmode trnsformtion. power cn e optimized under some constrints such s dely or re. 2. Relted Work In [4], controlsignl gting technique is proposed to reduce the switching ctivities on dtpth uses. The ide is to use oservility don t cre conditions of uses to gte control signls going to the us driver modules so tht the switching ctivity on the module inputs does not propgte to the us. Unlike the sleepmode trnsformtion, the proposed method does not work for dtpth uses or modules which re not driven y registers. The other prolem of the method is tht it computes oservility don t cre sed on the structurl netlist of design, which my e very expensive or even prohiitive on rel designs with intensive dtpth elements. To the est of our knowledge, work of [5] presents the first comprehensive pproch tht utomtes sleepmode (opernd isoltion) on RTL netlist. Unlike the work in [4], this pper presents complicted RTL power model to estimte the power svings y introducing the sleepmode logic. Additionlly, rther thn using n existing signl for the enle signl for the sleepmode logic, new function is used nd computed y structurl nlysis of the trnsitive fnout of module. The work of [6] is different from ove introduced techniques in tht it chieves power sving y redesigning control logic to reconfigure the existing dtpth components under idle conditions. The drwck of this technique is tht it works well on controlflow intensive designs ut not on dtflow intensive designs. Additionlly, the technique my significntly chnge the finl netlist to reduce power. This my not e fvored in rel industril designs when power is secondry optimiztion trget s compred to dely in most design situtions. All ove solutions suffer from common prolem: committing n optimiztion move t the RTL in hopes of sving power fter logic nd physicl optimiztion. It is well known tht power estimtions t RTL cn significntly differ from the rel chip power or even gte level power estimtions [2,3]. Since there is no ccurte power nd timing informtion ville t RTL to perform the correct trdeoff, these solutions my end up e Permission to mke digitl or hrd copies of ll or prt of this work for personl or clssroom use is grnted without fee provided tht copies re not mde or distriuted for profit or commercil dvntge nd tht copies er this notice nd the full cittion on the first pge. To copy otherwise, to repulish, to post on servers or to redistriute to lists, requires prior specific permission nd/or fee. ICCAD 03, Novemer 1113, 2003, Sn Jose, Cliforni, USA. Copyright 2003 ACM /03/ $
2 incresing the ctul power or dely of the synthesized netlist. Even if some provides cpility to undo the trnsformtions t the end of the synthesis run[5], the optimizer hs lredy spent lot of effort optimizing the wrong criticl pths which re mostly not reversile. This my cuse extr long run time or, design with worse power nd timing compred to the one without pplying the RTL trnsformtion. In this pper, we present novel solution to solve the ove prolem. This unique pproch consists of two steps, nmely RTL explortion nd gtelevel commitment. First, during RTL explortion, we use the Control Dt Flow Grph (CDFG) generted from the RTL description of design to identify ll the sleep mode trnsformtion cndidtes, including the enle signls for ech cndidte. The enle signl is computed y performing ehviorl level oservility nlysis (BLOA) on CDFG, s to e descried in Section 3. Since CDFG contins ll highlevel informtion (control nd dt flow), we re le to identify ll possile sleepmode trnsformtion opportunities presented in design. More importntly, since the enle signls re computed directly from the control flow, it elimintes the concern tht some enle signls my e synthesized into some other logic during synthesis, thus losing the opportunity of ny possile trnsformtions ssocited with the signl. After identifying ll the cndidtes, we mrk the gte level netlist to "rememer" these potentil trnsformtions without ltering the dt pth or the control pth of the design. Noticely, ecuse the originl dt nd control pths of the design re mintined, the logic nd timing optimiztion pplied lter will work on the true criticl pth nd no effort is wsted. After logic nd timing optimiztion hs een completed, ech "mrk" of the potentil sleep mode trnsformtion will e evluted nd committed or removed to mke sure it sves power without violting timing or re constrints. This is referred s gtelevel commitment in the pper. It needs to e pointed out tht ecuse of the vilility of ccurte power nd timing informtion t this stge ny decision mde t this point reflects the rel sttus of the design. In ddition to the improved ccurcy, the complexity of the lgorithm is significntly reduced since no complicted nd errorprone RTL power nd dely models re required. It needs to e noted tht we re not proposing new RTL power trnsformtion. Insted, we re proposing new pproch on how to pply the RTL power trnsformtion known s opernd isoltion or sleepmode trnsformtion. With the seprtion of RTL explortion nd gtelevel commitment, the proposed pproch tkes the dvntge of oth rich controldtflow informtion t the RTL nd the ccurte power nd dely informtion t the gtelevel so tht the est possile power dely trdeoff cn e chieved. Our technique gurntees tht design with sleepmode trnsformtions inserted hs less power nd sme or etter timing compred to design without the trnsformtions without significnt run time overhed on the existing timing optimiztion flow. 3. Behviorl Oservility Anlysis Oservility nlysis in logic circuits hs een widely used in logic synthesis, test genertion, nd mny other ECAD prolems [8]. In this section, we extend the ide of oservility nlysis to the ehviorl level description of digitl system, i.e. CDFG. It is referred s ehviorl level oservility nlysis (BLOA) for the rest of the pper Introduction of CDFG A CDFG is grphicl representtion of the ehviors of digitl hrdwre. The grph is generted from hrdwre ehviorl description lnguges, such s Verilog or VHDL, nd serves s n interfce to different RTL nd rchitecturl synthesis pckges. More detils out CDFG cn e found in [7]. A CDFG consists of nodes nd directed edges. The nodes represent opertions in the ehviorl description. The edges model the trnsfer of vlues etween the nodes, i.e. the result of one opertion (node) is pssed to the rgument of nother one. Every rgument of n opertion cn e seen s n input port of the corresponding node of the CDFG. Every result of n opertion cn e seen s n output port of the corresponding node of the CDFG. A token is defined s single dt vlue instnce. There re four mjor types of nodes. i 0 i 1 i k1 n op c i n rnch i 0 i 1 i k1 n merge n cons o 0 o 1 o j1 o 0 o 1 o j1 o o 0 o 1 o j1 () () (c) (d) Figure 2. CDFG nodes. () Opertion node () rnch node (c) merge node (d) construct node. ) Opertion nodes: Opertions cn e rithmetic, like +,,,, or Boolen, like,, or cn e more complex functions or n instntition of nother grph, which models the procedures nd functions in the ehviorl specifiction. The grphicl representtion of n opertion node n op with input edges i 0 to i k1 nd output edges o 0 to o j1 is shown in Figure 2.. The node performs the opertion defined y n op on the dt vlues of the input edges nd trnsfer the result to ll output edges. ) Brnch nodes: A rnch node hs two input ports, control port nd dt port, nd t lest one output dt port. Bsed on the vlue of token on the control port, one nd only one output port is selected nd the token on the input dt port is pssed to the selected output port. The grphicl representtion of rnch node n rnch with input dt edge i nd input control edge c nd output edge o 0 to o j1 is shown in Figure 2.. For exmple, if the dt vlue on the control edge c is 0, then the dt vlue on the input edge i is trnsferred to the output edge o 0. c) Merge nodes: Merge nodes re dul to rnch nodes. A merge node hs one output dt port, one input control port nd severl input dt ports. It psses the token on one input dt port, selected y the vlue of the token on the control port, to the output port. The grphicl representtion of merge node n merge with input dt edges i 0 to i k1 nd input control edge c nd output edge o which is shown in Figure 2.c. For exmple, if the dt vlue on the control edge c is 0, then the dt vlue on the input edge i 0 is trnsferred to the output edge o. d) Construct nodes: These re specil nodes, which only serve the purpose to generte tokens to control the rnch nd merge nodes. It hs one input dt port nd t lest one output control ports. Only one output port is selected to pss the token from the input port ccording to the vlue of the token. The grphicl representtion of merge node is shown in Figure 2.d. c i
3 Other types of nodes include input, output, register nd constnt nodes. Every grph requires t lest one input node nd one output node. Constnt nodes re nodes which generte constnt dt vlue t their single output port. Input, output nd register nodes correspond to input, output ports nd registers of the design represented y the CDFG respectively. 3.2 Oservility of CDFG Nodes nd Edges A token in CDFG is the counterprt of signl in logic circuit. In the rest we refer to the ehviorl level oservility nlysis s the token oservility nlysis on CDFG. Definition 1: token oservle condition (TOC) of n edge e ij, denoted y TOC(e ij ), is the condition under which the token on tht edge cn e oserved t one or more output nodes of CDFG. Definition 2: node oservle condition (NOC) of node n i, denoted y NOC(n i ), is the condition under which the token on ny output edge of the node cn e oserved t one or more output nodes of CDFG. Given CDFG, the TOC nd NOC for ll edges nd nodes cn e computed y trversing the grph from the output nodes to the input nodes nd pplying pproprite Boolen opertions. Let,, nd denote the Boolen AND, OR, inversion opertions respectively. For ech different type of node, the TOCs of ll edges nd NOCs of ll nodes re computed s follows. 1) Output nodes: By definition, for n output node n out with input edge i, NOC(n out ) = 1, TOC(i) = 1 2) Opertion nodes: For n opertion node n op such s the one in Figure 2. with input edges of i 0,, i k1 nd output edges of o 0,, o j1, we hve NOC(n op ) = TOC(o 0 ) TOC(o 1 ) TOC(o j1 ) TOC(i p ) = NOC(n op ), p {0, 1,, k1} For the ske of TOC/NOC nlysis, input nd construct nodes re treted the sme s opertion nodes. 3) Brnch nodes: For rnch node n rnch s shown in Figure 2., with input dt edge of i nd input control edge of c nd output edges of o 0,, o j1, we hve NOC(n rnch ) = TOC(o 0 ) TOC(o 1 ) TOC(o j1 ) TOC(c) = NOC(n rnch ) TOC(i) = ( c 0 TOC(o 0 )) (c 1 TOC(o 1 )) (c j1 TOC(o j1 )) where c p, p [0,j1] is Boolen encoding of the vriles for the vlue of the token t the control port to select output port p. For exmple, if the token on c is two it wide (c= c 1 c 0 ) nd output port 2 is selected, i.e. c is (10) in inry, then the condition to select port is c 1 c 0. 4) Merge nodes: For merge node n merge s shown in Figure 2.c, with input dt edges of i 0,, i k1 nd input control edge of c nd output edge of o, we hve NOC(n merge ) = TOC(o) TOC(c) = TOC(o) TOC(i p ) = c p TOC(o), p [0,k1] The definition of c p is the dul to tht descried for rnch nodes, i.e. the condition under which the input port p is selected y n merge to pss the token to the output port. As in [5], to void the computtionl complexity we ssume the NOC of register node to e 1. In other words, we do not nlysis oservilities cross register oundry Computtion of TOC/NOC Computing TOC/NOC requires Boolen opertions. A common wy to perform Boolen opertions is to use BDD (Binry Decision Digrm [9]). The prolem of this pproch is tht BDD is not roust enough to hndle lrge Boolen functions. In this section, n efficient nd yet simple pproch to compute TOC/NOC of CDFG is proposed. The ide of the pproch is the seprtion of trversing CDFG nd computing TOC/NOC. Insted of uilding BDD for the TOC/NOC of ech edge nd node, logic network is constructed whenever Boolen opertion is required to compute the TOC/NOC. The logic network is then optimized using trditionl logic optimiztion techniques such s lgeric trnsformtions [8], to otin the optimized Boolen function of the TOC/NOC. The trnsformtions used in the optimiztion process re chosen to e simple enough so tht computing TOC/NOC will e lmost invisile to the overll optimiztion flow. This method is idel for the frontend RTL synthesis tool where CDFG is trnslted into gte level netlist nd there exists onetoone correspondence etween the ojects of CDFG nd the ojects of the logic network. The method is est explined y n exmple. clk register output in1 in2 cmp en N2 N3 N4 N1 construct E1 E2 N8 2 N5 N9 == N11 E3 E4 + N12 E5 N13 E6 N14 E7 N15 E8 N16 N10 construct Figure 3. An exmple CDFG In Figure 3, the CDFG of simple digitl system is shown. As stted ove, fter gte level netlist is generted from this CDFG, there is n onetoone correspondence etween the ojects of CDFG nd the ojects of the generted logic network. For exmple, let e the corresponding signl for node N1 nd e the corresponding signl for node N10 in the netlist. We will explin the computtion of TOC for edges E1 nd E2 in Figure 4. The computtion strts from the output nodes using the formuls in the Section 3 depended on the type of the node visited. It is esy to see the TOC of edges E8 nd E7 is simply logic 1, s highlighted in Figure 4. For edge E6, the TOC is the Boolen AND of the TOC of E7 nd the vrile of the control port of the
4 E8,E7 1 c E6 d E5,E4 e E3,E2,E1 in1 SleepControlModule_0 Figure 4. Compute TOC for edges of CDFG in Figure 3. node N14 which is the sme s the vrile t the output port of construct node N1. Therefore in Figure 4 the AND gte c is constructed whose output represents the TOC of E6. Similrly, the TOC of edge E5 is the AND of TOC of edge E6 nd the vrile of the control port of node N13. The AND gte d is creted for the TOC of edge E5. The process continues until the edges E1 nd E2 re reched. As shown in Figure 4, the output of the AND gte e represents the TOC of edges E2 nd E1. After pplying simple logic optimiztions, the TOC of edges E1, E2 nd E3 is simply the AND of nd. Note tht only single trversl from the output nodes to the inputs is required to compute the TOCs of these edges. The complexity of the lgorithm is O( V + E ) where V nd E re the numer of nodes nd edges of CDFG respectively. In our experience, the numer of nodes nd edges of CDFG is much less thn those of the corresponding structurl netlist. As result, the proposed technique for TOC/NOC computtion is extremely fst even for very ig stteofrt digitl designs. 4. Proposed Sleepmode Trnsformtions As descried erlier, the proposed sleepmode trnsformtion consists of two steps, nmely RTL explortion nd gtelevel commitment. 4.1 RTL Explortion The ppliction of BLOA techniques introduced in Section 3 to sleepmode trnsformtion is strightforwrd. The corresponding logic of n opertion node is perfect cndidte for sleepmode trnsformtion where the computed TOC/NOC cn e used to generte the corresponding enle signl. Nodes with TOC equl to 1 cn not e cndidtes for sleep mode trnsformtion ecuse the outputs of the corresponding logic lock re lwys oservle. During the explortion phse, complete BLOA is performed on the CDFG. Opertion nodes with NOC not equl to 1 re selected s cndidtes. These cndidtes re then mrked on the gtelevel netlist. No ctul implementtion is performed in this phse. Commitment of these trnsformtions is delyed fter gtelevel optimiztion hs een done where ccurte power nd timing informtion is ville. For exmple, BLOA nlysis of the design shown in Figure 3 finds tht under the condition of & the outputs of the multiplier (node N5) re not used, where nd re the signls in the netlist corresponding to the condition represented y construct node N1 nd N10 respectively. The netlist of the design fter RTL explortion is shown in Figure 5. Compred to the norml netlist fter RTL synthesis, the RTL sleepmode explored netlist hs two new inserted modules clled SleepModeModule, one in front of ech multiplier input. The inserted modules hve following chrcteristics. First the dt us is feedthrough within the module. Second, within the SleepModeModule,, there is nother module clled SleepModeControlModule. It contins the complex in2 SleepControlModule_1 SleepModeModule_1 Figure 5. Netlist fter RTL sleepmode explortion for the multiplier of the exmple in Figure 3. enle function for the sleepmode cndidte. In this cse, it is the AND function of nd. There exists onetoone correspondence etween the input pins of the SleepModeControlModule nd the input ports of the SleepModeModule, ut they re not connected. The SleepModeModule serves s the mrk for the cndidte of sleepmode trnsformtion, which is the multiplier in this cse. Note tht even though the multiplier hierrchy my e dissolved during synthesis, the mrk for the sleepmode cndidte will e preserved, ecuse the SleepModeModule is not dissolved, which could e esily done. The SleepModeControlModule serves s the vehicle to rememer the enle logic for this cndidte. The onetoone correspondence imposed y pin nmes etween the input ports of the SleepModeModule nd inputs of the SleepModeControlModule is required during the committing phse where the enle logic is ctully connected. Becuse no extr lod is dded to the control nd the dt pth, the criticl pth of the originl design will e preserved. As result, the lter logic nd timing optimiztion will e le to focus on the rel criticl pth nd optimize the netlist s if no sleepmode trnsformtions re performed. Therefore, s long s the sleepmode cndidtes re not committed, there is no concern tht the they my cuse new timing violtions when the originl design meets timing fter logic nd timing optimiztion. Another dvntge of the technique is tht it llows only portion of the enle function to e used s the enle logic for the sleepmode cndidte during the gtelevel commitment phse, known s prtil sleepmode committing. 4.2 Gtelevel Commitment After logic nd timing optimiztion, decision to commit ech individul cndidte is mde sed on whether or not the power is reduced without violting the timing constrints. The lgorithm is shown in Figure 6. First, we sort ll sleep mode cndidtes sed on the potentil power svings. The commitment strts from the sleepmode cndidte which hs the iggest potentil power svings. Then for ech selected cndidte, the input ports of SleepModeModule nd the input pins of SleepModeControlModule tht hve the sme nme re connected. The ctul gting logic is inserted nd n incrementl power nd timing nlysis is performed. If the gte level 42
5 Prtilly committing 1. Connect Inside of SleepModeModule 2. Insert AND gtes 3. Power sved nd timing met? N 4. Is enle logic reducile? Y 5.Reduce enle logic to improve timing Fully committing N Y 7. Stop 6. Remove ll inserted logic nd hierrchies enle logic y executing steps 3 through 5 (in Figure 6). In this exmple, we know tht the enle logic for this cndidte is &. This mens tht either or cn lso e used s the enle logic. Since we do not wnt to e prt of the enle function ecuse of timing violtion, we cn use s the enle logic for input us in2. In other words, y removing the input of from the originl enle function, the new enle function is reduced from & to. Note tht prtil commitment is possile ecuse the enle logic nd the inputs for ech sleep mode cndidte re seprtely derived during RTL synthesis nd preserved fter logic nd timing optimiztion. As shown in Figure 6, the prtil committing loop stops when the enle logic cnnot e reduced further. The prtil commitment cpility of the proposed pproch differs significntly from the trditionl pproch where, if sleep mode trnsformtion violtes timing constrints, it is completely removed. Our pproch provides much lrger scope to perform power dely trdeoffs. Finlly, if committing sleepmode cndidte cuses power increse or timing violtion even fter prtil committing, we cn simply uncommit the sleepmode cndidte y removing ll inserted logic on the control nd dt pth, nd then dissolve the inserted hierrchicl modules. Figure 6. Gte level sleepmode commit lgorithm. commitment succeeds t step 3, then it is clled fully committed. Tht is, whtever cndidtes nd enle logic identified t RTL is fully committed to sve power without violting timing constrints. For exmple, to fully commit the sleepmode modules inserted in Figure 5, we cn simply connect the control portion of the circuit within the SleepModeModule nd insert AND gtes on the dt signls, s shown in Figure Gtelevel Prtilly Committing However, the full commit my cuse new timing violtions. For exmple, let s ssume tht fter fully committing ll sleepmode modules, the pth from to the second input of multiplier violtes timing constrints, s highlighted in Figure 7. To void the newly introduced timing violtion, one solution is to completely remove the sleepmode logic t input in2 of the multiplier, ut doing this will significntly limit the power reduction tht cn e chieved. A much etter solution is to prtilly commit the sleepmode SleepModeModule_0 5. Flow Integrtion nd Implementtion The proposed RTL power optimiztion technique cn e semlessly integrted into ny existing design flow. The RTL explortion cn e dded t the end of norml RTL synthesis, nd the gtelevel commitment cn e dded fter timing optimiztion completes. Existing flow needs no modifiction to pply the technique. More importntly, the seprtion of RTL explortion from gtelevel elimintes possile itertions etween the RTL nd the gte level tht cn occur in trditionl pproches. In trditionl pproches, it is possile tht timing constrints cn not e met even y undoing ll the sleepmode trnsformtions fter gte level optimiztion, ecuse they my hve shifted the criticl pths. This is not prolem for the proposed technique ecuse the decision for commitment of cndidte is delyed until the circuit hs een optimized for timing. At this stge, the ccurte power nd dely estimtion cn e esily otined from the gte level power nd timing nlysis engine. As result, ech commitment mkes sure tht it sves power without violting timing constrints. The dely of the circuit fter gtelevel committing is gurnteed to e no worse thn the dely of the RTL elortion sleepmode explortion in1 in2 SleepModeModule_1 Figure 7. Netlist fter gtelevel sleepmode full commitment for the exmple in Figure preplcement gte level optimiztion sleepmode commitment physicl synthesis plce & route Figure 8. Flow integrtion
6 # Inst. Slck Tot. Pow. DP Power (ns) (mw) (mw) (%) circuit efore committing. Finlly, since the decision of sleepmode commitment is delyed to gtelevel, it elimintes the need for complicted nd generlly inccurte RTL power nd dely models [5]. The proposed lgorithm is implemented in Cdence PKS/LPS 5.0 relese [10]. As shown in Figure 8, the stndrd flow consists of locks with no shdes nd the sleepmode flow includes the two shded oxes. The flow strts from the RTL of design. During RTL explortion, sleepmode logic is inserted ut not fully connected. After norml flow of preplcement timing nd dtpth optimiztion, including resource shring nd opertor merging [10], it then strts the gtelevel commitment phse of the sleepmode trnsformtion. This is done efore the physicl plcement of the design. The reson we do not perform the commitment phse fter plcement ecuse the commitment phse my introduce significnt mount of new logic which could cuse the incrementl plcement filure. The signoff qulity power nd timing nlysis engine provided y PKS re used to compute the power nd dely (Step 3 of Figure 6) ccurtely in the commitment phse. More specificlly, fter insertion of the gting logic (Step 2 of Figure 6), the PKS/LPS incrementl power nd timing nlysis engine is used to otin the ccurte power nd dely informtion to compre it with the power nd dely informtion efore the trnsformtion. If power is reduced nd dely is not worsened, the sleepmode trnsformtion will then e ccepted nd committed into the netlist. Otherwise, the sleepmode logic is removed. In other words, the dely nd power penlty due to the inserted gting logic is considered during the commitment phse. 6. Experiment Results Six industril circuits were chosen for experiments. Design 4 is microprocessor, Design 5 nd 6 re communiction chips. The types of the rest circuits re unknown. All designs except Design 6 hve customer provided test enches, which were used to simulte the circuit to get the switching ctivities for power nlysis. For Design 6, rndom input ptterns were used to simulte to otin the switching ctivities for power nlysis. Tle 1 shows the chrcteristics of ech design. The column Inst shows the numer of instnces of the design. The columns Slck nd Tot. Pow re the slck nd power dissiption of the design fter norml synthesis nd optimiztion. The lst column DP Power shows the totl dtpth component power nd its percentge of the totl power in column Tot. Pow. Since sleepmode trnsformtions trget only for power optimiztion on these RTL Explortion SM cnd. CPU SM Comm Gtelevel commitment Slck Pow. (ns) Sved D % D % % 16.3% D % D % % 6.4% D % D % % 20.0% D % D % % 4.1% D % D % % 14.7% D % D % % 23.5% Tle 1. Designs used for experiments Tle 2. Experimentl results with proposed method 44 CPU locks, in the experiment, we only use the power of these locks to show the power svings of the proposed technique. The experimentl results re shown in Tle 2. Column SM cnd. shows the numer of sleepmode cndidtes identified during RTL explortion. The second column CPU shows the run time increse in percentge of sleepmode RTL explortion compred to tht of norml RTL elortion. The results show tht the RTL explortion is very efficient nd introduces lmost no dditionl computtion time. Column SM comm. shows the numer of sleepmode cndidtes committed in the gtelevel commitment phse. Column Slck shows the slck fter gte level optimiztion. Column Pow. Sved shows the totl power sved s percentge of the dtpth power, s shown in Column 5 in Tle 1. The lst column shows the CPU run time of the gtelevel commitment s percentge of the totl run time of the norml gte level optimiztion. The re increse due to the finl inserted sleepmode modules re not shown ecuse the mximum re overhed mong ll designs is less thn 1%. Since the proposed method will not modify the originl timing pth fter RTL explortion nd the commitment of ech sleepmode logic is delyed fter timing optimiztion, the timing optimiztion will work s if there is no sleep mode logic inserted. The trget slck of gte level optimiztion for ech design is 0. For designs with negtive slck in Tle 1, the finl slck fter gte level commitment is not worse thn tht in Tle 1. For designs with positive slck in Tle 1, the finl slck is smller ut not less thn 0 fter the gte level commitment. The power svings cn e chieved strongly depend on the timing constrints, the switching ctivities of the enle function, nd the power dissiption of the dt pth locks. For exmple, in Design 2, most of the sleepmode cndidtes re not committed t the gte level ecuse the proilities of enle signls re close to 1 which leves little room for power svings. For Design 6, most of the sleepmode cndidtes re not committed due to the tight dely constrint. As comprison we did nother set of experiments. In these experiments, fter RTL explortion, we simply mp the netlist without ny other optimiztion nd commit the sleepmode cndidtes sed on the power nd dely informtion otined t this level. This is similr to the trditionl pproch [5] where the sleepmode trnsformtions re committed sed on RTL power nd dely estimtion. The results re shown in Tle 3. The column SM inserted shows the numer of sleep mode logic inserted. The column slck shows the slck fter timing optimiztion. The column power sved shows the dtpth power sved in percentge compred to the netlist without ny sleep
7 SM Inserted Slck (ns) power sved CPU overhed D % 0.98 D % 1.01 D % 1.63 D % 0.96 D % 1.57 D % 2.10 Tle 3. Results of committing cndidtes t RTL mode inserted, column 5 of Tle 1. The column of CPU overhed is the rtio of the totl CPU time of this experiment to the CPU time using the proposed technique. Compre the Tle 2 nd 3 we cn see tht for Design 1, 2 nd 4, the results re very similr. However, the results of Design 3, 5 nd 6 from Tle 2 re much etter thn those from Tle 3. For exmple, for Design 6 in Tle 3, lot of sleep mode cndidtes re committed sed on the inccurte power nd dely informtion. Unfortuntely, it ws found during timing optimiztion tht most of the inserted sleepmode logic ecome prt of the timing criticl pths nd significntly worsen the performnce of the design. Therefore the timing optimiztion spends significntly more run time nd gte resources to improve the slck. As result, the finl design consumes more power thn the one without the sleepmode trnsformtions nd misses the timing trget. Overll, for Design 6, the proposed method chieved 4.3% power svings with no degrdtion of circuit dely nd the trditionl method produced finl netlist with more power, worst dely nd rn twice slower. To show the roustness of the proposed technique in terms of chieving est power delys trdeoffs, we select Design 6 to run gtelevel commitment with different nd relxed timing constrints. The result is shown in Tle 4. Ech row shows the experimentl results with different set of timing constrints. Row 1 shows the results with the originl timing constrints. Rows 2 to 4 show the results with the relxed timing constrints. The column Relxed constr. shows the degree of the relxtion of timing constrints in percentge. It cn e seen tht, for Design 6 when the timing constrint is relxed, more sleepmode cndidtes cn e committed t the gte level nd significnt more power svings, s much s 45%, cn e chieved. The results show tht the chievle power svings of the proposed technique re mostly ounded y the timing constrints nd the switching ctivities of the enle signls. The lower the ctivities of the enle signls nd the looser the timing constrints, the more power reduction cn e chieved. Given the specified timing constrints, the proposed technique will pply the sleepmode trnsformtions to sve the most power without worsening the timing. Relxed constr. SM Inserted power sved not relxed 0% % relxed 1 25% % relxed 2 50% % relxed 3 100% % Tle 4. Results of Design 6 with relxed timing constrints 7. Conclusion nd Future Work In this pper we propose new pproch to pply known RTL power optimiztion technique to chieve the est possile power dely trdeoffs. The concept of reking the optimiztion into two steps, i.e. RTL explortion nd gtelevel commitment, hs lot of dvntges over trditionl techniques s shown in the experimentl results. First, it hs little impct on the norml logic nd timing optimiztion ecuse ll sleepmode modules inserted fter RTL explortion preserve the originl connectivity nd lods of the dt nd control pths of the design. Therefore the run time nd finl slck of timing optimiztion re the sme s if there is no sleepmode logic inserted. This mkes the proposed technique very prcticl for current min strem design methodology where the first design trget is timing nd power is normlly secondry concern. Secondly, since the committing of the sleepmode is delyed until the design is timing optimized, ccurte power dely trdeoff cn e chieved given the exct timing nd power informtion ville t tht point. Finlly it hs the cpility of prtil committing of the sleepmode modules which leds to much lrger solution spce eing explored to chieve the optiml power nd dely trdeoff. Overll, no itertion etween RTL nd gtelevel optimiztion required to chieve timing closure nd sve power when using the proposed technique. The experimentl results show tht the proposed method cn chieve meningful power svings with no impct on existing norml timing optimiztion t ll where the trditionl methods my produce design with worse timing nd power nd longer run time. Currently we re working on pply the sme concept to other RTL power trnsformtions such s clock gting. 8. REFERENCES [1] A.P. Chndrksn nd R. W. Brodersen, Low Power Digitl CMOS Design, Kluwer Acdemic Pulishers, [2] K. Keutzer nd P. Vnekergen, The Impct of CAD on the Design of Low Power Digitl Circuits [3] M. Pedrm, Power Minimiztion in IC Design: Principles nd Applictions, ACM Trnsctions on Design Automtion of Electronics Systems, Jnury 1996, Vol 11, pp [4] H. Kpdi, L. Benini, nd G. De Micheli, Reducing Switching Activity on Dtpth Buses with ControlSignl Gting, IEEE Journl of SolidStte Circuits, Vol. 34, No. 3, Mrch 1999, pp [5] M. Munch, nd et. l., Automting RTLevel Opernd Isoltion to Minimize Power Consumption in Dtpths, Proceedings of Design nd Test Automtion Conference in Europe. [6] S. Dey nd et. l., ControllerBsed Power Mngement for ControlFlow Intensive Designs, IEEE Trns. on ComputerAided Design of Integrted Circuits nd Systems, Vol. 18, No. 10, Octoer 1999, pp [7] J. vn Eijndhoven, G. de Jong, nd L. Stok. The ASCIS dt flow grph: semntics nd textul formt. Technicl Report EUTReport 91E251, Eindhoven University of Technology, Eindhoven, Netherlnds, June [8] De Micheli. Synthesis nd Optimiztion of Digitl Circuits. McGrwhill, Inc., [9] R. Brynt. Grphsed lgorithms for oolen function mnipultion. IEEE Trnsctions on Computers, C35(8): , Aug [10] Cdence Low Power Synthesis (LPS) User s Guide for Cdence PKS. 45
Assuming all values are initially zero, what are the values of A and B after executing this Verilog code inside an always block? C=1; A <= C; B = C;
B26 Appendix B The Bsics of Logic Design Check Yourself ALU n [Arthritic Logic Unit or (rre) Arithmetic Logic Unit] A rndomnumer genertor supplied s stndrd with ll computer systems Stn KellyBootle,
More informationReasoning to Solve Equations and Inequalities
Lesson4 Resoning to Solve Equtions nd Inequlities In erlier work in this unit, you modeled situtions with severl vriles nd equtions. For exmple, suppose you were given usiness plns for concert showing
More informationSirindhorn International Institute of Technology Thammasat University at Rangsit
Sirindhorn Interntionl Institute of Technology Thmmst University t Rngsit School of Informtion, Computer nd Communiction Technology COURSE : ECS 204 Bsic Electricl Engineering L INSTRUCTOR : Asst. Prof.
More informationEQUATIONS OF LINES AND PLANES
EQUATIONS OF LINES AND PLANES MATH 195, SECTION 59 (VIPUL NAIK) Corresponding mteril in the ook: Section 12.5. Wht students should definitely get: Prmetric eqution of line given in pointdirection nd twopoint
More informationOr more simply put, when adding or subtracting quantities, their uncertainties add.
Propgtion of Uncertint through Mthemticl Opertions Since the untit of interest in n eperiment is rrel otined mesuring tht untit directl, we must understnd how error propgtes when mthemticl opertions re
More informationBinary Golomb Codes. CSE 589 Applied Algorithms Autumn Constructing a Binary Golomb Code. Example. Example. Comparison of GC with Entropy
CSE 589 pplied lgorithms utumn Golom Coding rithmetic Coding LZW Sequitur Binry Golom Codes Binry source with s much more frequent thn s. Vriletovrile length code Prefix code. Golom code of order 4 input
More informationCS99S Laboratory 2 Preparation Copyright W. J. Dally 2001 October 1, 2001
CS99S Lortory 2 Preprtion Copyright W. J. Dlly 2 Octoer, 2 Ojectives:. Understnd the principle of sttic CMOS gte circuits 2. Build simple logic gtes from MOS trnsistors 3. Evlute these gtes to oserve logic
More information1 Numerical Solution to Quadratic Equations
cs42: introduction to numericl nlysis 09/4/0 Lecture 2: Introduction Prt II nd Solving Equtions Instructor: Professor Amos Ron Scribes: Yunpeng Li, Mrk Cowlishw Numericl Solution to Qudrtic Equtions Recll
More informationSmall Business Networking
Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd processes. Introducing technology
More informationIn the following there are presented four different kinds of simulation games for a given Büchi automaton A = :
Simultion Gmes Motivtion There re t lest two distinct purposes for which it is useful to compute simultion reltionships etween the sttes of utomt. Firstly, with the use of simultion reltions it is possile
More informationSmall Business Networking
Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd business. Introducing technology
More informationOutline of the Lecture. Software Testing. Unit & Integration Testing. Components. Lecture Notes 3 (of 4)
Outline of the Lecture Softwre Testing Lecture Notes 3 (of 4) Integrtion Testing Topdown ottomup igng Sndwich System Testing cceptnce Testing istriution of ults in lrge Industril Softwre System (ISST
More information2 DIODE CLIPPING and CLAMPING CIRCUITS
2 DIODE CLIPPING nd CLAMPING CIRCUITS 2.1 Ojectives Understnding the operting principle of diode clipping circuit Understnding the operting principle of clmping circuit Understnding the wveform chnge of
More informationPolynomial Functions. Polynomial functions in one variable can be written in expanded form as ( )
Polynomil Functions Polynomil functions in one vrible cn be written in expnded form s n n 1 n 2 2 f x = x + x + x + + x + x+ n n 1 n 2 2 1 0 Exmples of polynomils in expnded form re nd 3 8 7 4 = 5 4 +
More informationSmall Business Networking
Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd business. Introducing technology
More informationRegular Sets and Expressions
Regulr Sets nd Expressions Finite utomt re importnt in science, mthemtics, nd engineering. Engineers like them ecuse they re super models for circuits (And, since the dvent of VLSI systems sometimes finite
More informationRegular Language Membership Constraint
Regulr Lnguge Memership Constrint Niko Pltzer Universität des Srlndes, Deutschlnd, nikopp@ps.unis.de, Advisor: Lutz Strßurger Astrct. This pper minly dels with the work of Gilles Pesnt on the stretch
More informationSmall Business Networking
Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd processes. Introducing technology
More informationSmall Business Networking
Why Network is n Essentil Productivity Tool for Any Smll Business TechAdvisory.org SME Reports sponsored by Effective technology is essentil for smll businesses looking to increse their productivity. Computer
More informationSmall Business Networking
Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd processes. Introducing technology
More informationVendor Rating for Service Desk Selection
Vendor Presented By DATE Using the scores of 0, 1, 2, or 3, plese rte the vendor's presenttion on how well they demonstrted the functionl requirements in the res below. Also consider how efficient nd functionl
More informationSection 54 Trigonometric Functions
5 Trigonometric Functions Section 5 Trigonometric Functions Definition of the Trigonometric Functions Clcultor Evlution of Trigonometric Functions Definition of the Trigonometric Functions Alternte Form
More informationHillsborough Township Public Schools Mathematics Department Computer Programming 1
Essentil Unit 1 Introduction to Progrmming Pcing: 15 dys Common Unit Test Wht re the ethicl implictions for ming in tody s world? There re ethicl responsibilities to consider when writing computer s. Citizenship,
More informationQuadratic Equations  1
Alger Module A60 Qudrtic Equtions  1 Copyright This puliction The Northern Alert Institute of Technology 00. All Rights Reserved. LAST REVISED Novemer, 008 Qudrtic Equtions  1 Sttement of Prerequisite
More informationAppendix D: Completing the Square and the Quadratic Formula. In Appendix A, two special cases of expanding brackets were considered:
Appendi D: Completing the Squre nd the Qudrtic Formul Fctoring qudrtic epressions such s: + 6 + 8 ws one of the topics introduced in Appendi C. Fctoring qudrtic epressions is useful skill tht cn help you
More informationP.3 Polynomials and Factoring. P.3 an 1. Polynomial STUDY TIP. Example 1 Writing Polynomials in Standard Form. What you should learn
33337_0P03.qp 2/27/06 24 9:3 AM Chpter P Pge 24 Prerequisites P.3 Polynomils nd Fctoring Wht you should lern Polynomils An lgeric epression is collection of vriles nd rel numers. The most common type of
More informationAntiSpyware Enterprise Module 8.5
AntiSpywre Enterprise Module 8.5 Product Guide Aout the AntiSpywre Enterprise Module The McAfee AntiSpywre Enterprise Module 8.5 is n ddon to the VirusScn Enterprise 8.5i product tht extends its ility
More informationEngineertoEngineer Note
EngineertoEngineer Note EE280 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources http://www.nlog.com/eenotes nd http://www.nlog.com/processors or emil
More informationEngineertoEngineer Note
EngineertoEngineer Note EE265 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our
More informationConcept Formation Using Graph Grammars
Concept Formtion Using Grph Grmmrs Istvn Jonyer, Lwrence B. Holder nd Dine J. Cook Deprtment of Computer Science nd Engineering University of Texs t Arlington Box 19015 (416 Ytes St.), Arlington, TX 760190015
More informationBasics of Logic Design: Boolean Algebra, Logic Gates. Administrative
Bsics of Logic Design: Boolen Alger, Logic Gtes Computer Science 104 Administrtive Homework #3 Due Sundy Midterm I Mondy in clss, closed ook, closed notes Ø Will provide IA32 instruction set hndout Ø Lst
More informationSection 5.2, Commands for Configuring ISDN Protocols. Section 5.3, Configuring ISDN Signaling. Section 5.4, Configuring ISDN LAPD and Call Control
Chpter 5 Configurtion of ISDN Protocols This chpter provides instructions for configuring the ISDN protocols in the SP201 for signling conversion. Use the sections tht reflect the softwre you re configuring.
More informationIntroducing Kashef for Application Monitoring
WextWise 2010 Introducing Kshef for Appliction The Cse for Reltime monitoring of dtcenter helth is criticl IT process serving vriety of needs. Avilbility requirements of 6 nd 7 nines of tody SOA oriented
More informationEconomics Letters 65 (1999) 9 15. macroeconomists. a b, Ruth A. Judson, Ann L. Owen. Received 11 December 1998; accepted 12 May 1999
Economics Letters 65 (1999) 9 15 Estimting dynmic pnel dt models: guide for q mcroeconomists b, * Ruth A. Judson, Ann L. Owen Federl Reserve Bord of Governors, 0th & C Sts., N.W. Wshington, D.C. 0551,
More informationLINEAR TRANSFORMATIONS AND THEIR REPRESENTING MATRICES
LINEAR TRANSFORMATIONS AND THEIR REPRESENTING MATRICES DAVID WEBB CONTENTS Liner trnsformtions 2 The representing mtrix of liner trnsformtion 3 3 An ppliction: reflections in the plne 6 4 The lgebr of
More informationVariable Dry Run (for Python)
Vrile Dr Run (for Pthon) Age group: Ailities ssumed: Time: Size of group: Focus Vriles Assignment Sequencing Progrmming 7 dult Ver simple progrmming, sic understnding of ssignment nd vriles 2050 minutes
More informationVersion 001 CIRCUITS holland (1290) 1
Version CRCUTS hollnd (9) This printout should hve questions Multiplechoice questions my continue on the next column or pge find ll choices efore nswering AP M 99 MC points The power dissipted in wire
More informationMATLAB: Mfiles; Numerical Integration Last revised : March, 2003
MATLAB: Mfiles; Numericl Integrtion Lst revised : Mrch, 00 Introduction to Mfiles In this tutoril we lern the bsics of working with Mfiles in MATLAB, so clled becuse they must use.m for their filenme
More informationSmall Businesses Decisions to Offer Health Insurance to Employees
Smll Businesses Decisions to Offer Helth Insurnce to Employees Ctherine McLughlin nd Adm Swinurn, June 2014 Employersponsored helth insurnce (ESI) is the dominnt source of coverge for nonelderly dults
More informationQuadratic Equations. Math 99 N1 Chapter 8
Qudrtic Equtions Mth 99 N1 Chpter 8 1 Introduction A qudrtic eqution is n eqution where the unknown ppers rised to the second power t most. In other words, it looks for the vlues of x such tht second degree
More informationa. Implement the function using a minimal network of 2:4 decoders and OR gates.
CSE4 Eercise Solutions I. Given threeinput Boolen function f(,, c) = m(, 2, 4, 6, 7) + d().. Implement the function using miniml network of 2:4 decoders nd OR gtes. Stndrd solution: Use s the enle signl,
More informationTechniques for Requirements Gathering and Definition. Kristian Persson Principal Product Specialist
Techniques for Requirements Gthering nd Definition Kristin Persson Principl Product Specilist Requirements Lifecycle Mngement Elicit nd define business/user requirements Vlidte requirements Anlyze requirements
More informationDIGITAL CIRCUITS EXAMPLES (questions and solutions) Dr. N. AYDIN
DIGITAL CIRCUITS EXAMPLES (questions nd solutions) Dr. N. AYDIN nydin@yildiz.edu.tr Emple. Assume tht the inverter in the network elow hs propgtion dely of 5 ns nd the AND gte hs propgtion dely of ns.
More informationAPPLICATION NOTE Revision 3.0 MTD/PS0534 August 13, 2008 KODAK IMAGE SENDORS COLOR CORRECTION FOR IMAGE SENSORS
APPLICATION NOTE Revision 3.0 MTD/PS0534 August 13, 2008 KODAK IMAGE SENDORS COLOR CORRECTION FOR IMAGE SENSORS TABLE OF FIGURES Figure 1: Spectrl Response of CMOS Imge Sensor...3 Figure 2: Byer CFA Ptterns...4
More informationEcon 4721 Money and Banking Problem Set 2 Answer Key
Econ 472 Money nd Bnking Problem Set 2 Answer Key Problem (35 points) Consider n overlpping genertions model in which consumers live for two periods. The number of people born in ech genertion grows in
More informationMath 135 Circles and Completing the Square Examples
Mth 135 Circles nd Completing the Squre Exmples A perfect squre is number such tht = b 2 for some rel number b. Some exmples of perfect squres re 4 = 2 2, 16 = 4 2, 169 = 13 2. We wish to hve method for
More informationSuffix Trees CMSC 423
Suffix Trees CMSC 423 Preprocessing Strings Over the next few lectures, we ll see severl methods for preprocessing string dt into dt structures tht mke mny questions (like serching) esy to nswer: Suffix
More informationTwo hours UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE. Date: Friday 16 th May 2008. Time: 14:00 16:00
COMP20212 Two hours UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE Digitl Design Techniques Dte: Fridy 16 th My 2008 Time: 14:00 16:00 Plese nswer ny THREE Questions from the FOUR questions provided
More informationA Note on Complement of Trapezoidal Fuzzy Numbers Using the αcut Method
Interntionl Journl of Applictions of Fuzzy Sets nd Artificil Intelligence ISSN  Vol.  A Note on Complement of Trpezoidl Fuzzy Numers Using the αcut Method D. Stephen Dingr K. Jivgn PG nd Reserch Deprtment
More informationMorgan Stanley Ad Hoc Reporting Guide
spphire user guide Ferury 2015 Morgn Stnley Ad Hoc Reporting Guide An Overview For Spphire Users 1 Introduction The Ad Hoc Reporting tool is ville for your reporting needs outside of the Spphire stndrd
More informationRethinking Virtual Network Embedding: Substrate Support for Path Splitting and Migration
Rethinking Virtul Network Emedding: Sustrte Support for Pth Splitting nd Migrtion Minln Yu, Yung Yi, Jennifer Rexford, Mung Ching Princeton University Princeton, NJ {minlnyu,yyi,jrex,chingm}@princeton.edu
More informationFAULT TREES AND RELIABILITY BLOCK DIAGRAMS. Harry G. Kwatny. Department of Mechanical Engineering & Mechanics Drexel University
SYSTEM FAULT AND Hrry G. Kwtny Deprtment of Mechnicl Engineering & Mechnics Drexel University OUTLINE SYSTEM RBD Definition RBDs nd Fult Trees System Structure Structure Functions Pths nd Cutsets Reliility
More informationOperations with Polynomials
38 Chpter P Prerequisites P.4 Opertions with Polynomils Wht you should lern: Write polynomils in stndrd form nd identify the leding coefficients nd degrees of polynomils Add nd subtrct polynomils Multiply
More information10.5 Graphing Quadratic Functions
0.5 Grphing Qudrtic Functions Now tht we cn solve qudrtic equtions, we wnt to lern how to grph the function ssocited with the qudrtic eqution. We cll this the qudrtic function. Grphs of Qudrtic Functions
More informationEquivalence Checking. Sean Weaver
Equivlene Cheking Sen Wever Equivlene Cheking Given two Boolen funtions, prove whether or not two they re funtionlly equivlent This tlk fouses speifilly on the mehnis of heking the equivlene of pirs of
More informationffiiii::#;#ltlti.*?*:j,'i#,rffi
5..1 EXPEDTNG A PROJECT. 187 700 6 o 'o' 600 E 500 17 18 19 20 Project durtion (dys) Figure 66 Project cost vs. project durtion for smple crsh problem. Using Excel@ to Crsh Project T" llt ffiiii::#;#ltlti.*?*:j,'i#,rffi
More informationSpace Vector Pulse Width Modulation Based Induction Motor with V/F Control
Interntionl Journl of Science nd Reserch (IJSR) Spce Vector Pulse Width Modultion Bsed Induction Motor with V/F Control Vikrmrjn Jmbulingm Electricl nd Electronics Engineering, VIT University, Indi Abstrct:
More informationEECE 481. Static MOS Gate and FlipFlop Circuits Lecture 8
EECE 48 Sttic MOS Gte nd FlipFlop Circuits Lecture 8 Rez Molvi Dept. of ECE University of British Columi rez@ece.uc.c Slides Courtesy : Dr. Res Sleh (UBC), Dr. D. Sengupt (AMD), Dr. B. Rzvi (UCLA) EECE
More informationTests for One Poisson Mean
Chpter 412 Tests for One Poisson Men Introduction The Poisson probbility lw gives the probbility distribution of the number of events occurring in specified intervl of time or spce. The Poisson distribution
More informationTreatment Spring Late Summer Fall 0.10 5.56 3.85 0.61 6.97 3.01 1.91 3.01 2.13 2.99 5.33 2.50 1.06 3.53 6.10 Mean = 1.33 Mean = 4.88 Mean = 3.
The nlysis of vrince (ANOVA) Although the ttest is one of the most commonly used sttisticl hypothesis tests, it hs limittions. The mjor limittion is tht the ttest cn be used to compre the mens of only
More informationT H E S E C U R E T R A N S M I S S I O N P R O T O C O L O F S E N S O R A D H O C N E T W O R K
Z E S Z Y T Y N A U K O W E A K A D E M I I M A R Y N A R K I W O J E N N E J S C I E N T I F I C J O U R N A L O F P O L I S H N A V A L A C A D E M Y 2015 (LVI) 4 (203) A n d r z e j M r c z k DOI: 10.5604/0860889X.1187607
More information5 a LAN 6 a gateway 7 a modem
STARTER With the help of this digrm, try to descrie the function of these components of typicl network system: 1 file server 2 ridge 3 router 4 ckone 5 LAN 6 gtewy 7 modem Another Novell LAN Router Internet
More informationVoIP for the Small Business
Reducing your telecommunictions costs VoIP (Voice over Internet Protocol) offers low cost lterntive to expensive trditionl phone services nd is rpidly becoming the communictions system of choice for smll
More information1.00/1.001 Introduction to Computers and Engineering Problem Solving Fall 2011  Final Exam
1./1.1 Introduction to Computers nd Engineering Problem Solving Fll 211  Finl Exm Nme: MIT Emil: TA: Section: You hve 3 hours to complete this exm. In ll questions, you should ssume tht ll necessry pckges
More informationEquations between labeled directed graphs
Equtions etween leled directed grphs Existence of solutions GrretFontelles A., Misnikov A., Ventur E. My 2013 Motivtionl prolem H 1 nd H 2 two sugroups of the free group generted y X A, F (X, A). H 1
More informationTool Support for FeatureOriented Software Development
Tool Support for FetureOriented Softwre Development FetureIDE: An EclipseBsed Approch Thoms Leich leich@iti.cs.unimgdeurg.de Sven Apel pel@iti.cs.unimgdeurg.de Lur Mrnitz mrnitz@cs.unimgdeurg.de ABSTRACT
More informationNew Internet Radio Feature
XXXXX XXXXX XXXXX /XWSMA3/XWSMA4 New Internet Rdio Feture EN This wireless speker hs een designed to llow you to enjoy Pndor*/Internet Rdio. In order to ply Pndor/Internet Rdio, however, it my e necessry
More informationAnswer, Key Homework 10 David McIntyre 1
Answer, Key Homework 10 Dvid McIntyre 1 This printout should hve 22 questions, check tht it is complete. Multiplechoice questions my continue on the next column or pge: find ll choices efore mking your
More informationClearPeaks Customer Care Guide. Business as Usual (BaU) Services Peace of mind for your BI Investment
ClerPeks Customer Cre Guide Business s Usul (BU) Services Pece of mind for your BI Investment ClerPeks Customer Cre Business s Usul Services Tble of Contents 1. Overview...3 Benefits of Choosing ClerPeks
More informationVirtual Machine. Part II: Program Control. Building a Modern Computer From First Principles. www.nand2tetris.org
Virtul Mchine Prt II: Progrm Control Building Modern Computer From First Principles www.nnd2tetris.org Elements of Computing Systems, Nisn & Schocken, MIT Press, www.nnd2tetris.org, Chpter 8: Virtul Mchine,
More informationFactoring Polynomials
Fctoring Polynomils Some definitions (not necessrily ll for secondry school mthemtics): A polynomil is the sum of one or more terms, in which ech term consists of product of constnt nd one or more vribles
More informationNetwork Configuration Independence Mechanism
3GPP TSG SA WG3 Security S3#19 S3010323 36 July, 2001 Newbury, UK Source: Title: Document for: AT&T Wireless Network Configurtion Independence Mechnism Approvl 1 Introduction During the lst S3 meeting
More informationMATLAB Workshop 13  Linear Systems of Equations
MATLAB: Workshop  Liner Systems of Equtions pge MATLAB Workshop  Liner Systems of Equtions Objectives: Crete script to solve commonly occurring problem in engineering: liner systems of equtions. MATLAB
More informationSimulation of operation modes of isochronous cyclotron by a new interative method
NUKLEONIKA 27;52(1):29 34 ORIGINAL PAPER Simultion of opertion modes of isochronous cyclotron y new intertive method Ryszrd Trszkiewicz, Mrek Tlch, Jcek Sulikowski, Henryk Doruch, Tdeusz Norys, Artur Srok,
More informationSource Code verification Using Logiscope and CodeReducer. Christophe Peron Principal Consultant Kalimetrix
Source Code verifiction Using Logiscope nd CodeReducer Christophe Peron Principl Consultnt Klimetrix Agend Introducing Logiscope: Improving confidence nd developer s productivity Bsed on stteofthert
More informationSquare Roots Teacher Notes
Henri Picciotto Squre Roots Techer Notes This unit is intended to help students develop n understnding of squre roots from visul / geometric point of view, nd lso to develop their numer sense round this
More informationDlNBVRGH + Sickness Absence Monitoring Report. Executive of the Council. Purpose of report
DlNBVRGH + + THE CITY OF EDINBURGH COUNCIL Sickness Absence Monitoring Report Executive of the Council 8fh My 4 I.I...3 Purpose of report This report quntifies the mount of working time lost s result of
More informationData replication in mobile computing
Technicl Report, My 2010 Dt repliction in mobile computing Bchelor s Thesis in Electricl Engineering Rodrigo Christovm Pmplon HALMSTAD UNIVERSITY, IDE SCHOOL OF INFORMATION SCIENCE, COMPUTER AND ELECTRICAL
More informationBasic Research in Computer Science BRICS RS0213 Brodal et al.: Solving the String Statistics Problem in Time O(n log n)
BRICS Bsic Reserch in Computer Science BRICS RS0213 Brodl et l.: Solving the String Sttistics Prolem in Time O(n log n) Solving the String Sttistics Prolem in Time O(n log n) Gerth Stølting Brodl Rune
More informationLearning Outcomes. Computer Systems  Architecture Lecture 4  Boolean Logic. What is Logic? Boolean Logic 10/28/2010
/28/2 Lerning Outcomes At the end of this lecture you should: Computer Systems  Architecture Lecture 4  Boolen Logic Eddie Edwrds eedwrds@doc.ic.c.uk http://www.doc.ic.c.uk/~eedwrds/compsys (Hevily sed
More informationOne Minute To Learn Programming: Finite Automata
Gret Theoreticl Ides In Computer Science Steven Rudich CS 15251 Spring 2005 Lecture 9 Fe 8 2005 Crnegie Mellon University One Minute To Lern Progrmming: Finite Automt Let me tech you progrmming lnguge
More informationJPAE Application: A StepbyStep Guide
JPAE Appliction: A StepyStep Guide Copyright 2016 2014 NCS Pte. Pte. Ltd. Ltd. All All Rights Rights Reserved. Step 1: Access JPAE You my ccess the JPAE Appliction t jpe.polytechnic.edu.sg You will e
More informationTemplate deed of assignment of intellectual property
Templte deed of ssignment of intellectul property User notes This document is intended for use y the founders of strt up compny to formlly trnsfer intellectul property relevnt to the usiness, products
More informationScalable Mining of Large Diskbased Graph Databases
Sclle Mining of Lrge Disksed Grph Dtses Chen Wng Wei Wng Jin Pei Yongti Zhu Bile Shi Fudn University, Chin, {chenwng, weiwng1, 2465, shi}@fudn.edu.cn Stte University of New York t Bufflo, USA & Simon
More informationA Network Management System for PowerLine Communications and its Verification by Simulation
A Network Mngement System for PowerLine Communictions nd its Verifiction y Simultion Mrkus Seeck, Gerd Bumiller GmH UnterschluerscherHuptstr. 10, D90613 Großhersdorf, Germny Phone: +49 9105 996051,
More informationA.7.1 Trigonometric interpretation of dot product... 324. A.7.2 Geometric interpretation of dot product... 324
A P P E N D I X A Vectors CONTENTS A.1 Scling vector................................................ 321 A.2 Unit or Direction vectors...................................... 321 A.3 Vector ddition.................................................
More informationMathematics. Vectors. hsn.uk.net. Higher. Contents. Vectors 128 HSN23100
hsn.uk.net Higher Mthemtics UNIT 3 OUTCOME 1 Vectors Contents Vectors 18 1 Vectors nd Sclrs 18 Components 18 3 Mgnitude 130 4 Equl Vectors 131 5 Addition nd Subtrction of Vectors 13 6 Multipliction by
More informationEE247 Lecture 4. For simplicity, will start with all pole ladder type filters. Convert to integrator based form example shown
EE247 Lecture 4 Ldder type filters For simplicity, will strt with ll pole ldder type filters Convert to integrtor bsed form exmple shown Then will ttend to high order ldder type filters incorporting zeros
More informationCombined Liability Insurance. Information and Communication Technology Proposal form
Comined Liility Insurnce Informtion nd Communiction Technology Proposl form Comined Liility Insurnce Informtion nd Communiction Technology  Proposl form This proposl form must e completed nd signed y
More informationExperiment 6: Friction
Experiment 6: Friction In previous lbs we studied Newton s lws in n idel setting, tht is, one where friction nd ir resistnce were ignored. However, from our everydy experience with motion, we know tht
More informationUse Geometry Expressions to create a more complex locus of points. Find evidence for equivalence using Geometry Expressions.
Lerning Objectives Loci nd Conics Lesson 3: The Ellipse Level: Preclculus Time required: 120 minutes In this lesson, students will generlize their knowledge of the circle to the ellipse. The prmetric nd
More informationWEB DELAY ANALYSIS AND REDUCTION BY USING LOAD BALANCING OF A DNSBASED WEB SERVER CLUSTER
Interntionl Journl of Computers nd Applictions, Vol. 9, No., 007 WEB DELAY ANALYSIS AND REDUCTION BY USING LOAD BALANCING OF A DNSBASED WEB SERVER CLUSTER Y.W. Bi nd Y.C. Wu Abstrct Bsed on our survey
More informationBayesian Updating with Continuous Priors Class 13, 18.05, Spring 2014 Jeremy Orloff and Jonathan Bloom
Byesin Updting with Continuous Priors Clss 3, 8.05, Spring 04 Jeremy Orloff nd Jonthn Bloom Lerning Gols. Understnd prmeterized fmily of distriutions s representing continuous rnge of hypotheses for the
More informationSolving Linear Equations  Formulas
1. Solving Liner Equtions  Formuls Ojective: Solve liner formuls for given vrile. Solving formuls is much like solving generl liner equtions. The only difference is we will hve severl vriles in the prolem
More informationLiveEngage Agent Guide. Version 1.0
Agent Guide Version 1.0 Tle of Contents Contents LOGGING IN... 3 NAVIGATING LIVEENGAGE... 4 Visitor List, Connection Are, Enggement Br & Going Online... 4 ENGAGEMENT OPTIONS... 5 Tking n Enggment... 5
More informationTuring Machine Extensions
Red K & S 4.3.1, 4.4. Do Homework 19. Turing Mchine Extensions Turing Mchine Definitions An lterntive definition of Turing mchine: (K, Σ, Γ, δ, s, H): Γ is finite set of llowble tpe symbols. One of these
More informationChapter 6 Solving equations
Chpter 6 Solving equtions Defining n eqution 6.1 Up to now we hve looked minly t epressions. An epression is n incomplete sttement nd hs no equl sign. Now we wnt to look t equtions. An eqution hs n = sign
More informationCAD PROJECT AND PROTOTYPE FOR AN ANTHROPOMORPHIC GRIPPER FOR ROBOTS  SIMULATION AND TESTING
Proceedings of the Annul Symposium of the Institute of Solid Mechnics nd Session of the Commission of Acoustics, SISOM 2015 Buchrest 2122 My CAD PROJECT AND PROTOTYPE FOR AN ANTHROPOMORPHIC GRIPPER FOR
More informationChapter 9: Quadratic Equations
Chpter 9: Qudrtic Equtions QUADRATIC EQUATIONS DEFINITION + + c = 0,, c re constnts (generlly integers) ROOTS Synonyms: Solutions or Zeros Cn hve 0, 1, or rel roots Consider the grph of qudrtic equtions.
More information