Combinational Functions and Circuits

Transcription

1 Introduction to Digital Logic Prof. Nizamettin DIN ourse Outline. Digital omputers, Number Systems, rithmetic Operations, Decimal, lphanumeric, and Gray odes. inary Logic, Gates, oolean lgebra, Standard orms. ircuit Optimization, Two-Level Optimization, Map Manipulation, Multi-Level ircuit Optimization. dditional Gates and ircuits, Other Gate Types, Exclusive-OR Operator and Gates, High-Impedance Outputs. Implementation Technology and Logic Design, Design oncepts and utomation, The Design Space, Design Procedure, The major design steps 6. Programmable Implementation Technologies: Read-Only Memories, Programmable Logic rrays, Programmable rray Logic,Technology mapping to programmable logic devices 7. ombinational unctions and ircuits. rithmetic unctions and ircuits 9. Sequential ircuits Storage Elements and Sequential ircuit nalysis. Sequential ircuits, Sequential ircuit Design State Diagrams, State Tables. ounters, register cells, buses, & serial operations. Sequencing and ontrol, Datapath and ontrol, lgorithmic State Machines (SM). Memory asics Introduction to Digital Logic Lecture 7 ombinational unctions and ircuits Overview unctions and functional blocks Rudimentary logic functions Decoding Encoding Selecting Implementing ombinational unctions Using: Decoders and OR gates Multiplexers (and inverter) ROMs PLs PLs Lookup Tables unctions and unctional locks The functions considered are those found to be very useful in design orresponding to each of the functions is a combinational circuit implementation called a functional block. In the past, many functional blocks were implemented as SSI, MSI, and LSI circuits. Today, they are often simply parts within a VLSI circuit. Rudimentary Logic unctions unctions of a single variable an be used on the inputs to functional blocks to implement other than the block s intended function unctions of One Variable = = = = V or V DD (c) (d) 6 opyright N. DIN. ll rights reserved.

2 Multiple-bit Rudimentary unctions Enabling unction Multi-bit Examples: wide line is used to represent a bus which is a vector signal In of the example, = (,,, ) is a bus. The bus can be split into individual bits as shown in Sets of bits can be split from the bus as shown in (c) for bits and of. : (:) (c),: (), (:) (d) The sets of bits need not be continuous as shown in (d) for bits,, and of. Enabling permits an input signal to pass through to an output Disabling blocks an input signal from passing through to an output, replacing it with a fixed value The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates),, or When disabled, output EN When disabled, output Enabling applications? EN 7 Decoding Decoder Examples Decoding - the conversion of an n-bit input code to an m-bit output code with n m n such that each valid code word produces a unique output code ircuits that perform decoding are called decoders Here, functional blocks for decoding are called n-to-m line decoders, where m n, and generate n (or fewer) minterms for the n input variables -to--line Decoder -to--line Decoder D D D D D D Note that the --line made up of -to-- line decoders and ND gates. D = D = D = D = D = D = 9 Decoder Expansion General procedure given in book for any decoder with n inputs and n outputs. This procedure builds a decoder backward from the outputs. The output ND gates are driven by two decoders with their numbers of inputs either equal or differing by. These decoders are then designed using the same procedure until -to--line decoders are reached. The procedure can be modified to apply to decoders with the number of outputs n Decoder Expansion - Example -to--line decoder Number of output NDs = Number of inputs to decoders driving output NDs = losest possible split to equal -to--line decoder -to--line decoder -to--line decoder Number of output NDs = Number of inputs to decoders driving output NDs = losest possible split to equal Two -to--line decoders opyright N. DIN. ll rights reserved.

3 Decoder Expansion - Example Decoder Expansion - Example Result -input NDs -input NDs -to--line decoder -to--line decoders -to- Line decoder D D D D D D D 6 D 7 7-to--line decoder Number of output NDs = Number of inputs to decoders driving output NDs = 7 losest possible split to equal -to-6-line decoder -to--line decoder -to-6-line decoder Number of output NDs = 6 Number of inputs to decoders driving output NDs = losest possible split to equal -to--line decoders omplete using known - and -to- line decoders Decoder with Enable In general, attach m-enabling circuits to the outputs Truth table for the function Note use of s to denote both and ombination containing two s represent four binary combinations lternatively, can be viewed as distributing value of signal EN to of outputs EN In this case, called a demultiplexer EN D D D D D D D D Encoding Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n m n such that each valid code word produces a unique output code ircuits that perform encoding are called encoders n encoder has n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is to a binary code corresponding to the position in which the appears. 6 Encoder Example decimal-to-d encoder Inputs: bits corresponding to decimal digits through 9, (D,, D 9 ) Outputs: bits with D codes unction: If input bit D i is a, then the output (,,, ) is the D code for i, The truth table could be formed, but alternatively, the equations for each of the four outputs can be obtained directly. Encoder Example (continued) Input D i is a term in equation j if bit j is in the binary value for i. Equations: = D + D 9 = D + D + D 6 + D 7 = D + D + D 6 + D 7 = D + D + D + D 7 + D 9 = D 6 + D 7 can be extracted from and 7 opyright N. DIN. ll rights reserved.

4 Priority Encoder If more than one input value is, then the encoder just designed does not work. One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder. mong the s that appear, it selects the most significant input position (or the least significant input position) containing a and responds with the corresponding binary code for that position. Priority Encoder Example Priority encoder with inputs (D, D, D, D, D ) - highest priority to most significant present - ode outputs,, and V where V indicates at least one present. No. of Minterms/Row D D Inputs D D 6 s in input part of table represent or ; thus table entries correspond to product terms instead of minterms. The column on the left shows that all minterms are present in the product terms in the table D Outputs V 9 Priority Encoder Example (continued) ould use a K-map to get equations, but can be read directly from table and manually optimized if careful: = D = D D + D D D = D, = (D + D ) = D D + D D D D = D (D + D D) V = D + + D + D Selecting Selecting of data or information is a critical function in digital systems and computers ircuits that perform selecting have: set of information inputs from which the selection is made single output set of control lines for making the selection Logic circuits that perform selecting are called multiplexers Selecting can also be done by three-state logic or transmission gates Multiplexers multiplexer selects information from an input line and directs the information to an output line typical multiplexer has n control inputs (S n, S ) called selection inputs, n information inputs (I n, I ), and one output multiplexer can be designed to have m information inputs with m < n as well as n selection inputs -to--line Multiplexer Since =, n = The single selection variable S has two values: S = selects input I S = selects input I The equation: = SI + SI The circuit: S Decoder I I Enabling ircuits opyright N. DIN. ll rights reserved.

5 -to--line Multiplexer (continued) Example: -to--line Multiplexer Note the regions of the multiplexer circuit shown: -to--line Decoder Enabling circuits -input OR gate To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a ND-OR circuit: -to--line decoder ND-OR In general, for an n -to--line multiplexer: n-to- n -line decoder n ND-OR -to- -line decoder ND-OR S S S S Decoder Decoder I I I x ND-OR I 6 Multiplexer Width Expansion Select vectors of bits instead of bits Use multiple copies of n ND-OR in parallel Example: -to--line quad multiplexer Other Selection Implementations Three-state logic in place of ND-OR S I I S I I Gate input cost = compared to (or ) for gate implementation 7 Other Selection Implementations ombinational unction Implementation Transmission Gate Multiplexer S Gate input S cost = compared I (S = ) to for -state logic I (S = ) and or for gate logic I (S = ) I (S = ) (S = ) (S = ) lternative implementation techniques: Decoders and OR gates Multiplexers (and inverter) ROMs PLs PLs Lookup Tables an be referred to as structured implementation methods since a specific underlying structure is assumed in each case 9 opyright N. DIN. ll rights reserved.

6 Decoder and OR Gates Implement m functions of n variables with: Sum-of-minterms expressions One n-to- n -line decoder m OR gates, one for each output pproach : ind the truth table for the functions Make a connection to the corresponding OR from the corresponding decoder output wherever a appears in the truth table pproach ind the minterms for each output function OR the minterms together Decoder and OR Gates Example Implement the following set of odd parity functions of ( 7, 6,, ) P = P = P = inding sum of minterms expressions P = Σ m (,,,6,,,,) P = Σ m (,,,6,,,,) P = Σ m (,,,,,9,,) ind circuit Is this a good idea? P P P Multiplexer pproach Example: Gray to inary ode Implement m functions of n variables with: Sum-of-minterms expressions n m-wide n -to--line multiplexer Design: ind the truth table for the functions. In the order they appear in the truth table: pply the function input variables to the multiplexer inputs S n,, S Label the outputs of the multiplexer with the output variables Value-fix the information inputs to the multiplexer using the values from the truth table (for don t cares, apply either or ) Design a circuit to convert a -bit Gray code to a binary code The formulation gives the truth table on the right It is obvious from this table that = and the and Z are more complex Gray inary x y z Gray to inary (continued) Gray to inary (continued) Rearrange the table so that the input combinations are in counting order unctions y and z can be implemented using a dual -to--line multiplexer by: connecting,, and to the multiplexer select inputs placing y and z on the two multiplexer outputs connecting their respective truth table values to the inputs Gray inary x y z D D D D D D D6 D7 S S S Out -to- MU Note that the multiplexer with fixed inputs is identical to a ROM with -bit addresses and -bit data! D D D D D D D6 D7 S S S Out -to- MU Z 6 opyright N. DIN. ll rights reserved. 6

7 Multiplexer pproach Example: Gray to inary ode Implement any m functions of n + variables by using: n m-wide n -to--line multiplexer single inverter Design: ind the truth table for the functions. ased on the values of the first n variables, separate the truth table rows into pairs or each pair and output, define a rudimentary function of the final variable (,,, ) Using the first n variables as the index, value-fix the information inputs to the multiplexer with the corresponding rudimentary functions Use the inverter to generate the rudimentary function Design a circuit to convert a -bit Gray code to a binary code The formulation gives the truth table on the right It is obvious from this table that x = and the and Z are more complex Gray inary x y z 7 Gray to inary (continued) Rearrange the table so that the input combinations are in counting order, pair rows, and find rudimentary functions Gray inary x y z Rudimentary unctions of for y = = = = Rudimentary unctions of for z = = = = ssign the variables and functions to the multiplexer inputs: Gray to inary (continued) D D D D S S Out -to- MU Note that this approach (pproach ) reduces the cost by almost half compared to pproach. This result is no longer ROM-like Extending, a function of more than n variables is decomposed into several sub-functions defined on a subset of the variables. The multiplexer then selects among these sub-functions. D D D D S S Out -to- MU Z 9 Read Only Memory Truth table unctions are implemented by storing the truth table Other representations such as equations more convenient Generation of programming information from equations usually done by software Text Example - : Design a combinational circuit using a ROM. The circuit accepts a bit number and generates an output binary number equal to the square of the input number opyright N. DIN. ll rights reserved. 7

8 Implementation Programmable rray Logic Two outputs are generated outside of the ROM In the implementation of the system, these two functions are hardwired and even if the ROM is reprogrammable or removable, cannot be corrected or updated There is no sharing of ND gates as in the ROM and PL Design requires fitting functions within the limited number of NDs per OR gate Single function optimization is the first step to fitting Otherwise, if the number of terms in a function is greater than the number of NDs per OR gate, then factoring is necessary Programmable rray Logic Example Programmable rray Logic Example ND gates inputs Equations: = = + + must be factored since four terms actor out last two terms as W Product term ND Inputs D W Outputs W = + = = + + W = = + + D Product term W D D W W ll fuses intact (always ) use intact use blown W D D W 6 Programmable Logic rray The set of functions to be implemented must fit the available number of product terms The number of literals per term is less important in fitting The best approach to fitting is multiple-output, two-level optimization (which has not been discussed) Since output inversion is available, terms can implement either a function or its complement or small circuits, K-maps can be used to visualize product term sharing and use of complements or larger circuits, software is used to do the optimization including use of complemented functions Programmable Logic rray Example K-map specification How can this be implemented with four terms? omplete the programming table = + + = + + = = + + PL programming table Product Inputs term Outputs (T) 7 opyright N. DIN. ll rights reserved.

9 Programmable Logic rray Example Lookup Tables use intact use blown Lookup tables are used for implementing logic in ield-programmable Gate rrays (PGs) and omplex Logic Devices (PLDs) Lookup tables are typically small, often with four inputs, one output, and 6 entries Since lookup tables store truth tables, it is possible to implement any -input function Thus, the design problem is how to optimally decompose a set of given functions into a set of - input two- level functions. We will illustrate this by a manual attempt 9 Lookup Table Example Equations to be implemented: (,,,D,E) = D E + D E + D E (,,D,E,) = D E + D E + D E Extract -input function: (,,D,E) = D E + D E (,D,E, ) = + D E (D,E,, ) = + D E The cost of the solution is lookup tables opyright N. DIN. ll rights reserved. 9