MC74VHC1GT04. Inverting Buffer / CMOS Logic Level Shifter. LSTTL Compatible Inputs

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Lewis Bridges
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1 MC74CGT04 Inverting Buffer / CMOS Logic Level Shifter LSTTL Compatible Inputs The MC74CGT04 is a single gate inverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL type input thresholds and the output has a full CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic level translator from 3 CMOS logic to CMOS Logic or from.8 CMOS logic to 3 CMOS Logic while operating at the high voltage power supply. The MC74CGT04 input structure provides protection when voltages up to 7.0 are applied, regardless of the supply voltage. This allows the MC74CGT04 to be used to interface circuits to 3 circuits. The output structures also provide protection when CC = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. Features igh Speed: t PD = 3.8 ns (Typ) at CC = Low Power Dissipation: I CC = A (Max) at T A = 2 C TTL Compatible Inputs: IL = ; I = 2 CMOS Compatible Outputs: O > CC ; OL < 0. Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 0; Equivalent Gates = 26 Pb Free Packages are Available DF SUFFIX CASE 49A TSOP DT SUFFIX CASE 483 PIN ASSIGNMENT NC 2 IN A 3 GND 4 OUT Y CC MARKING DIAGRAMS K M K = Device Code M = Date Code* = Pb Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. M K M NC CC A Input FUNCTION TABLE Y Output IN A 2 L L GND 3 4 OUT Y Figure. Pinout (Top iew) IN A OUT Y ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Figure 2. Logic Symbol Semiconductor Components Industries, LLC, 2007 Publication Order Number: MC74CGT04/D

2 MC74CGT04 MAXIMUM RATINGS Symbol Characteristics alue Unit CC DC Supply oltage 0. to +7.0 IN DC Input oltage 0. to +7.0 OUT DC Output oltage CC = 0 igh or Low State 0. to to CC + 0. I IK Input Diode Current 20 ma I OK Output Diode Current OUT < GND; OUT > CC +20 ma I OUT DC Output Current, per Pin +2 ma I CC DC Supply Current, CC and GND +0 ma P D Power dissipation in still air, TSOP 200 mw JA Thermal resistance, TSOP 333 C/W T L Lead temperature, mm from case for 0 s 260 C T J Junction temperature under bias +0 C T stg Storage temperature 6 to +0 C ESD ESD Withstand oltage uman Body Model (Note ) Machine Model (Note 2) Charged Device Model (Note 3) > 2000 > 400 N/A I Latchup Latchup Performance Above CC and Below GND at 2 C (Note 4) ±00 ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Tested to EIA/JESD22 A4 A 2. Tested to EIA/JESD22 A A 3. Tested to JESD22 C0 A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit CC DC Supply oltage. IN DC Input oltage. OUT DC Output oltage CC = 0 igh or Low State T A Operating Temperature Range +2 C. CC t r, t f Input Rise and Fall Time CC = 3.3 ± 0.3 CC =.0 ± ns/ DEICE JUNCTION TEMPERATURE ERSUS TIME TO 0.% BOND FAILURES Junction Temperature C Time, ours Time, Years 80,032, , , , , , ,900.0 NORMALIZED FAILURE RATE FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 30 C TJ = 20 C TJ = 0 C TJ = 00 C TJ = 90 C TJ = 80 C TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature 2

3 MC74CGT04 DC ELECTRICAL CARACTERISTICS Symbol Parameter Test Conditions I IL O OL I IN Minimum igh Level Input oltage Maximum Low Level Input oltage Minimum igh Level Output oltage IN = I or IL Maximum Low Level Output oltage IN = I or IL Maximum Input Leakage Current IN = I or IL I O = 0 A IN = I or IL I O = 4 ma I O = 8 ma IN = I or IL I OL = 0 A IN = I or IL I OL = 4.0 ma I OL = 8.0 ma IN =. or GND CC () to. T A = 2 C T A 8 C T A 2 C Min Typ Max Min Max Min Max Unit ±0. ±.0 ±.0 A I CC I CCT Maximum Quiescent Supply Current Quiescent Supply Current IN = CC or GND A Input: IN = ma I OPD Output Leakage Current OUT = A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CARACTERISTICS C load = 0 pf, Input t r = t f = ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ T A = 2 C T A 8 C T A 2 C ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Symbol Parameter Test Conditions Min Typ Max Min Max Min Max Unit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t ÎÎÎÎ PL, Maximum Propagation t PL ÎÎÎÎÎÎÎ Delay, Input A to Y ÎÎÎÎÎÎÎÎÎ CC = 3.3 ± 0.3 C L = C L = 0 pfîîî ÎÎÎ ÎÎÎÎ ÎÎ 3. ÎÎÎ ÎÎÎ.0 ÎÎÎ.0ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ns 7. ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ CC =.0 ± 0. C L = pfîîîîî 3.8 ÎÎÎÎÎÎÎÎÎÎÎÎ C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ L = 0 pfîîîîî 4.2 ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ C IN ÎÎÎÎÎÎÎ Maximum Input ÎÎÎÎÎÎÎÎÎÎÎÎÎ.0 ÎÎ 0 ÎÎÎÎÎ 0 ÎÎÎÎÎ 0 ÎÎ pf Capacitance 2 C, CC =.0 C PD Power Dissipation Capacitance (Note ) 0 pf. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC. C PD is used to determine the no load dynamic power consumption; P D = C PD 2 CC f in + I CC CC. 3

4 MC74CGT04 A 0% GND t PL t PL Y 0% CC O OL Figure 4. Switching Waveforms TEST POINT DEICE UNDER TEST OUTPUT C L * *Includes all probe and jig capacitance Figure. Test Circuit ORDERING INFORMATION MC74CGT04DFT M74CGT04DFTG Device Package Type Package (Pb Free) MC74CGT04DFT2 M74CGT04DFT2G (Pb Free) 3000 / Tape & Reel MC74CGT04DTT M74CGT04DTTG TSOP TSOP (Pb Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 4

5 MC74CGT04 PACKAGE DIMENSIONS / SOT 33 / SC 70 CASE 49A 02 ISSUE J S A G 4 B 2 3 D PL C 0.2 (08) M B M N J NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, CONTROLLING DIMENSION: INC A 0 OBSOLETE. NEW STANDARD 49A DIMENSIONS A AND B DO NOT INCLUDE MOLD FLAS, PROTRUSIONS, OR GATE BURRS. INCES MILLIMETERS DIM MIN MAX MIN MAX A B C D G 26 BSC 0.6 BSC 04 J K N 08 REF 0.20 REF S K SOLDERING FOOTPRINT* SCALE 20: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

6 MC74CGT04 PACKAGE DIMENSIONS TSOP CASE ISSUE F 2X 2X NOTE T 0.20 T L G A B C D X 0.20 C A B T S SEATING PLANE J K DETAIL Z M DETAIL Z NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.M, CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD TICKNESS INCLUDES LEAD FINIS TICKNESS. MINIMUM LEAD TICKNESS IS TE MINIMUM TICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLAS, PROTRUSIONS, OR GATE BURRS.. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN TIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE TAN 0.2 FROM BODY. MILLIMETERS DIM MIN MAX A 0 BSC B.0 BSC C D 0.2 G 0.9 BSC J 0.26 K L.2. M 0 0 S 0 SOLDERING FOOTPRINT* SCALE 0: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6 MC74CGT04/D

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