MM74C74 Dual D-Type Flip-Flop

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1 Dual D-Type Flip-Flop General Description The MM74C74 dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit cotructed with N- and P-channel enhancement traistors. Each flip-flop has independent data, preset, clear and clock inputs and Q and Q outputs. The logic level present at the data input is traferred to the output during the positive going traition of the clock pulse. Preset or clear is independent of the clock and accomplished by a low level at the preset or clear input. Features October 1987 Revised May 2002 Supply voltage range: 3 to 15 Tenth power TTL compatible: Drive 2 LPT 2 L loads High noise immunity: 0.45 CC (typ.) Low power: 50 nw (typ.) Medium speed operation: 10 MHz (typ.) with 10 supply Applicatio Automotive Data terminals Itrumentation Medical electronics Alarm system Industrial electronics Remote metering Computers MM74C74 Dual D-Type Flip-Flop Ordering Code: Order Number Package Number Package Description MM74C74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74C74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Truth Table Preset Clear Q n Q n Q n (Note 1) Note 1: No change in output from previous state. Q n (Note 1) Note: A logic 0 on clear sets Q to logic 0. A logic 0 on preset sets Q to logic 1. Top iew 2002 Fairchild Semiconductor Corporation DS

2 Logic Diagram 2

3 Absolute Maximum Ratings(Note 2) oltage at Any Pin (Note 2) 0.3 to CC +0.3 Operating Temperature Range 55 C to +125 C Storage Temperature Range 65 C to +150 C Power Dissipation Dual-In-Line 700 mw Small Outline 500 mw Lead Temperature (Soldering, 10 seconds) 260 C Operating CC Range 3 to 15 CC (Max) 18 Note 2: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditio for actual device operation. MM74C74 DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditio Min Typ Max Units CMOS TO CMOS IN(1) Logical 1 Input oltage CC = CC = IN(0) Logical 0 Input oltage CC = CC = OUT(1) Logical 1 Output oltage CC = CC = OUT(0) Logical 0 Output oltage CC = CC = I IN(1) Logical 1 Input Current CC = µa I IN(0) Logical 0 Input Current CC = µa I CC Supply Current CC = µa CMOS/LPTTL INTERFACE IN(1) Logical 1 Input oltage CC = 4.75 CC 1.5 IN(0) Logical 0 Input oltage CC = OUT(1) Logical 1 Output oltage CC = 4.75, I D = 360 µa 2.4 OUT(0) Logical 0 Output oltage CC = 4.75, I D = 360 µa 0.4 OUTPUT DRIE (See Family Characteristics Data Sheet) I SOURCE Output Source Current CC = 5, IN(0) = 0 T A = 25 C, OUT = ma I SOURCE Output Source Current CC = 10, IN(0) = 0 T A = 25 C, OUT = ma I SINK Output Sink Current CC = 5, IN(1) = 5 T A = 25 C, OUT = CC 1.75 ma I SINK Output Sink Current CC = 10, IN(1) = 10 T A = 25 C, OUT = CC 8.0 ma 3

4 AC Electrical Characteristics (Note 3) T A = 25 C, C L = 50 pf, unless otherwise noted Symbol Parameter Conditio Min Typ Max Units C IN Input Capacitance Any Input (Note 4) 5.0 pf t pd Propagation Delay Time to a CC = Logical 0 t pd0 or Logical 1 CC = t pd1 from Clock to Q or Q t pd Propagation Delay Time to a CC = Logical 0 from Preset or Clear CC = t pd Propagation Delay Time to a CC = Logical 1 from Preset or Clear CC = t S0, t S1 Time Prior to Clock Pulse that CC = Data Must be Present t SETUP CC = t H0, t H1 Time after Clock Pulse that CC = Data Must be Held CC = t PW1 Minimum Clock Pulse CC = Width (t WL = t WH ) CC = t PW2 Minimum Preset and CC = Clear Pulse Width CC = t r, t f Maximum Clock Rise CC = and Fall Time CC = µs f MAX Maximum Clock Frequency CC = CC = MHz C PD Power Dissipation Capacitance (Note 5) 40 pf Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. Note 5: C PD determines the no load AC power coumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. Typical Applicatio Ripple Counter (Divide by 2 n ) 74C Compatibility Shift Register Guaranteed Noise Margin as a Function of CC 4

5 Switching Time Waveform CMOS to CMOS MM74C74 t r = t f = 20 AC Test Circuit 5

6 Physical Dimeio inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 6

7 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) MM74C74 Dual D-Type Flip-Flop 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 7

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