MC74VHC1GT50. Noninverting Buffer / CMOS Logic Level Shifter. TTL Compatible Inputs

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1 MC7CGT0 Noninverting Buffer / CMOS Logic Level Shifter TTL Compatible Inputs The MC7CGT0 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL type input thresholds and the output has a full CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic level translator from 3 CMOS logic to CMOS Logic or from.8 CMOS logic to 3 CMOS Logic while operating at the high voltage power supply. The MC7CGT0 input structure provides protection when voltages up to 7 are applied, regardless of the supply voltage. This allows the MC7CGT0 to be used to interface high voltage to low voltage circuits. The output structures also provide protection when CC = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. Features Designed for.6 to. CC Operation igh Speed: t PD = 3. ns (Typ) at CC = Low Power Dissipation: I CC = A (Max) at T A = C TTL Compatible Inputs: IL = ; I =, CC = CMOS Compatible s: O > CC ; OL < Power Down Protection Provided on Inputs and s Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 0; Equivalent Gates = 6 Pb Free Packages are Available SC 88A/SOT 33/SC 70 DF SUFFIX CASE 9A PSSIGNMENT NC 3 GND TSOP /SOT 3/SC 9 DT SUFFIX CASE 83 L M OUT Y MARKING DIAGRAMS = Device Code = Date Code* = Pb Free Package M L M L M (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. CC NC CC GND 3 OUT Y Figure. Pinout (Top iew) FUNCTION TABLE A Input Y L L Figure. Logic Symbol OUT Y ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 007 Publication Order Number: MC7CGT0/D

2 MC7CGT0 MAXIMUM RATINGS Symbol Characteristics alue Unit CC DC Supply oltage 0. to +7.0 IN DC Input oltage 0. to +7.0 OUT DC oltage CC = 0 igh or Low State 0. to to CC + 0. I IK Input Diode 0 ma I OK Diode OUT < GND; OUT > CC +0 ma I OUT DC, per Pin + ma I CC DC Supply, CC and GND +0 ma P D Power dissipation in still air SC 88A, TSOP 00 mw JA Thermal resistance SC 88A, TSOP 333 C/W T L Lead temperature, mm from case for 0 secs 60 C T J Junction temperature under bias +0 C T stg Storage temperature 6 to +0 C ESD ESD Withstand oltage uman Body Model (Note ) Machine Model (Note ) Charged Device Model (Note 3) > 000 > 00 N/A I Latchup Latchup Performance Above CC and Below GND at C (Note ) ±00 ma Stresses exceeding Ratings may damage the device. Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Tested to EIA/JESD A A. Tested to EIA/JESD A A 3. Tested to JESD C0 A. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit CC DC Supply oltage.6. IN DC Input oltage. OUT DC oltage CC = 0 igh or Low State. CC T A Operating Temperature Range + C t r, t f Input Rise and Fall Time CC = 3.3 ± 0.3 CC =.0 ± ns/ Device Junction Temperature versus Time to % Bond Failures Junction Temperature C Time, ours Time, Years 80,03, , , , , , ,900.0 NORMALIZED FAILURE RATE FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 30 C TJ = 0 C TJ = 0 C TJ = 00 C TJ = 90 C TJ = 80 C TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature

3 MC7CGT0 DC ELECTRICAL CARACTERISTICS CC T A = C T A 8 C T A C Symbol Parameter Test Conditions () Min Typ Max Min Max Min Max Unit I Minimum.6 to.9 CC CC CC igh Level Input oltage.3 to CC. 0. CC. 0. CC. IL Low Level Input oltage.6 to.9.3 to.99 0 CC CC 0 CC CC 0 CC CC O OL I IN I CC I CCT I OPD Minimum igh Level oltage Low Level oltage Input Leakage Quiescent Supply Quiescent Supply Leakage IN = I I O = 0 A IN = I I O = ma I O = 8 ma IN = IL I OL = 0 A IN = IL I OL = ma I OL = 8 ma IN =. or GND..6 to.99.6 to.99 0 to. CC CC CC A IN = CC or GND A Input: IN = ma OUT = A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CARACTERISTICS C load = 0 pf, Input t r = t f = ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ T A = C ÎÎÎÎ T A 8 CÎÎÎÎÎÎ T A CÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Min ÎÎÎ Typ ÎÎÎ Max ÎÎ Min ÎÎÎ Max ÎÎÎ Min ÎÎÎÎ Max ÎÎ Symbol t PL, t PL Parameter Propagation Delay, Input A to Y Test Conditions CC =.8 ± C L = pf ns CC =. ± 0. C L = pf C L = 0 pf Unit ns CC = 3.3 ± 0.3 C L = pf C L = 0 pf ns CC =.0 ± 0. C L = pf C L = 0 pf C IN Input Capacitance pf C, CC =.0 C PD Power Dissipation Capacitance (Note ) pf. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC. C PD is used to determine the no load dynamic power consumption; P D = C PD CC f in + I CC CC. 3

4 MC7CGT0 A 0% CC GND t PL t PL Y 0% CC O OL Figure. Switching Waveforms TEST POINT DEICE UNDER TEST OUTPUT C L * *Includes all probe and jig capacitance Figure. Test Circuit ORDERING INFORMATION Device Package Shipping MC7CGT0DFT M7CGT0DFTG MC7CGT0DFT M7CGT0DFTG MC7CGT0DTT SC 88A / SOT 33 / SC 70 SC 88A / SOT 33 / SC 70 SC 88A / SOT 33 / SC 70 SC 88A / SOT 33 / SC 70 TSOP / SOT 3 / SC / Tape & Reel M7CGT0DTTG TSOP / SOT 3 / SC 9 For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D.

5 MC7CGT0 PACKAGE DIMENSIONS SC 88A, SOT 33, SC 70 CASE 9A 0 ISSUE J S A G B 3 D PL 0. (08) M B M N NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 98.. CONTROLLING DIMENSION: INC. 3. 9A 0 OBSOLETE. NEW STANDARD 9A 0.. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLAS, PROTRUSIONS, OR GATE BURRS. INCES MILLIMETERS DIM MIN MAX MIN MAX A B 3..3 C D G 6 BSC 0.6 BSC 0 0 J K N 08 REF 0.0 REF S C J K SOLDERING FOOTPRINT* SCALE 0: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC132A. Quad 2-Input NAND Gate with Schmitt-Trigger Inputs. High Performance Silicon Gate CMOS

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