LOAD LINES AND DC BIAS CIRCUITS

Transcription

1 C H A P T E R 58 Learning Objectives DC Load Line Q-Point and Maximum Undistorted Output Need for iasing a Transistor Factor Affecting ias Variations Stability Factor eta Sensitivity Stability Factor for C and CE Circuits Different Methods for Transistor iasing ase ias ase ias with Emitter Feedback ase ias with Collector Feedback ase ias with Collector and Emitter Feedbacks Emitter ias with two Supplies Voltage Divider ias Load Line and Output Characteristics AC Load Line LOAD LINES AND DC IAS CIRCUITS Ç DC biasing is used to establish a steady level of transistor current and voltage called the dc operating point or quescent point (Q-Point)

2 2220 Electrical Technology 58 DC Load Line For drawing the dc load line of a transistor, one need to know only its cut-off and saturation points It is a straight line jointing these two points For the CE circuit of Fig 5828, the load line is drawn in Fig 58 A is the cut-off point and is the saturation point The voltage equation of the collector-emitter is V IC RL + VCE IC R R Consider the following two particular cases : (i) when 0, cut-off point A (ii) when 0, / saturation point Obviously, load line can be drawn if only V CC and are known Incidentally slope of the load line A / Note The above given equation can be written as L CE L V V E CC C + RL RL It is a linear equation similar to y mx + c The graph of this equation is a straight line whose slope is m / Active Region Fig 58 All operating points (like C, D, E etc in Fig 58) lying between cut-off and saturation points form the active region of the transistor In this region, E/ junction is forward-biased and C/ junction is reverse-biased conditions necessary for the proper operation of a transistor Quiescent Point V EE 30 5K I V CC 20V 5K ma 4 V 0 A C V C (a) (b) 3 2 Fig 582 Q-POINT V CC 0 Saturation E D Active Region Cut-off C A V CC It is a point on the dc load line, which represents the values of and that exist in a transistor circuit when no input signal is applied It is also known as the dc operating point or working point The best position for this point is midway between cut-off and saturation points where 2 V CC (like point D in Fig 58) Example 58 For the circuit shown in Fig 582 (a), draw the dc load line and locate its quiescent or dc working point Solution The cut-off point is easily found because it lies along X-axis where 20 V ie point A in Fig 582 (b) At saturation point, saturation value of collector current is (sat) / 20 V/5 K 4 ma

3 Load Lines and DC ias Circuits 222 The line A represents the load line for the given circuit We will now find the actual operating point V EE / 30 V/5 K 2 ma neglecting V E α 2 ma; V C V Hence, Q-point is located at (0 V ; 2 ma) as shown in Fig 582 (b) Example 582 In the C circuit of Fig 83 (a), find (a) dc operating point and dc load line (b) maximum peak-to-peak unclipped signal (c) the approximate value of ac source voltage that will cause clipping (Electronics and Telecom Engg Jadavpur Univ) Solution (a) I C(sat) R 2 ma R S K V S 0 V 20 V 20 K (a) ma 0 K 20 V C 5 Fig Q A (b) L point V C at cut-off V CC 20 V point A Hence, A is the dc load line and is shown in Fig 583 (b) Now, 0/20 05 ma 05 ma V C V The Q-point is located at (5 V, 05 ma) (b) It is obvious from Fig 583 (b) that maximum positive swing can be from 5 V to 20 V ie 5 V only Of course, on the negative swing, the output swing can go from 5 V down to zero volt The limiting factor being cut-off on positive half-cycle, hence maximum unclipped peak-to-peak voltage that we can get from this circuit is V (c) The approximate voltage gain of the above circuit is V0 RL 0K Av 0 V S R S K It means that signal voltage will be amplified 0 times Hence, maximum value of source voltage for obtaining unclipped or undistorted output is V 0V 0 p p Vs V 0 0 p p Example 583 For the CE circuit shown in Fig 584 (a), draw the dc load line and mark the dc working point on it Assume b00 and neglect V (Applied Electronics, Punjab Univ) Solution Cut-off point A is located where, 0 and 30 V Saturation point is given where 0 and (sat) 30 V/5 K 6 ma Line A represents the load line in Fig 584 Fig 584 (b) I 5 M V C (a) V _ CC 30 V 5K ma A V (b) Q

4 2222 Electrical Technology Let us find the dc working point from the given values of resistances and supply voltage I 30 V/5 M 20 µa; βi µa 2 ma ; V C V Hence, Q point is (20 V ; 2 ma) as shown in Fig Q-Point and Maximum Undistorted Output Position of the Q-point on the dc load line determines the maximum signal that we can get from the circuit before clipping occurs Consider the cases shown in Fig 585 In Fig 585 (a), when Q is located near cut-off point, signal first starts to clip at A It is called cut-off clipping because the positive swing of the signal drives the transistor to cut-off In fact, as seen from Fig 585 (a), maximum positive swing is Q R ac I Saturation C Q 2 (sat) Cut-Off Q Q Q V 0 CE Q A A A (a) (b) (c) Fig 585 If the Q-point Q 2 is located near saturation point, then clipping first starts at point as shown in Fig 585 (b) It is caused by saturation The maximum negative swing Q In Fig 585 (c), the Q-point Q 3 is located at the centre of the load line In this condition, we get the maximum possible output signal The point Q 3 gives the optimum Q-point The maximum undistorted signal 2Q In general, consider the case shown in Fig 586 Since A <, maximum possible peak-to-peak output signal 2 A If the operating point were so located that A >, then maximum possible peak-to-peak output signal 2 When operating point is located at the centre of the load line, then maximum undistorted peak-to-peak signal is 2 A 2 2 V C EQ Under optimum working conditions corresponding to Fig 585 (c), Q is half the saturation value given by V CC / (Art 8) V CC ICQ Fig RL 2R Example 584 Determine the value of required to adjust the circuit of Fig 587 to optimum operating point Take β 50 and V E 07 V Solution As seen from above 20 ICQ ma 2RL 2 0 The corresponding base current is ICQ IQ 2µ A β 50 0 Q A

5 Load Lines and DC ias Circuits 2223 Now, V CC I + V E VE R Κ I Need For iasing a Transistor For normal operation of a transistor amplifier circuit, it is essential that there should be a (a) forward bias on the emitter-base junction and (b) reverse bias on the collector-base junction In addition, amount of bias required is important for establishing the Q-point which is dictated by the mode of operation desired Fig 587 If the transistor is not biased correctly, it would work inefficiently and 2 produce distortion in the output signal It is desirable that once selected, the Q-point should remain stable ie should not shift its position due to temperature rise etc Unfortunately, this does not happen in practice unless special efforts are made for the purpose 584 Factors Affecting ias Variations In practice, it is found that even after careful selection, Q-point tends to shift its position This bias instability is the direct result of thermal instability which itself is produced by cumulative increase in that may, if unchecked, lead to thermal runaway (Art 583) The collector current for C E circuit is given by βi + EO βi + ( + β) O This equation has three variables : β, I and O all of which are found to increase with temperature In particular, increase in O produces significant increase in collector current This leads to increased power dissipation with further increase in temperature and hence eing a cumulative process, it can lead to thermal runaway which will destroy the transistor itself! However, if by some circuit modification, is made to decrease with temperature automatically, then decrease in the term βi can be made to neutralize the increase in the term ( + β) O, thereby keeping constant This will achieve thermal stability resulting in bias stability 585 Stability Factor The degree of success achieved in stabilizing in the face of variations in O is expressed in terms of current stability factor S It is defined as the rate of change of with respect to O when both β and I (V E ) are held constant dic S di β and I constant CO Larger the value of S, greater the thermal instability and vice versa (in view of the above, this factor should, more appropriately, be called instability factor!) The stability factor may be alternatively expressed by using the well-known equation Iβ + (I + β) O which, on differentiation with respect to, yields di dico di ( +β) Iβ + ( +β ) β + ( +β) S dic dic dic S β ( di / dic) The stability factor of any circuit can be found by using the general formula + R / S + ( α ) ( R / R ) E RS V S C 0K V CC C 2 20V V out

6 2224 Electrical Technology where total series parallel resistance in the base total series dc resistance in the emitter α dc alpha of the transistor 586 eta Sensitivity y β sensitivity of a circuit is meant the influence that the β-value has on its dc operating point Variations in β-value are caused by variations in the circuit operating conditions or by the substitution of one transistor with another eta sensitivity K b is given by dic di β dic Kβ Kβ IC β IC di Obviously, K β is dimensionless ratio and can have values ranging from zero to unity 587 Stability Factor for C and CE Circuits (i) C Circuit Here, collector current is given by IC áie + ICO dic dico 0 + or S (ii) CE Circuit βi + ( + β) O dic ( +β ) dico treating I as a constant S ( + β) If β 00, then S 0 which means that changes 0 times as much as O 588 Different Methods for Transistor iasing Some of the methods used for providing bias for a transistor are : base bias or fixed current bias (Fig 589) It is not a very satisfactory method because bias voltages and currents do not remain constant during transistor operation 2 base bias with emitter feedback (Fig 580) This circuit achieves good stability of dc operating point against changes in β with the help of emitter resistor which causes degeneration to take place 3 base bias with collector feedback (Fig 58) It is also known as collector-to-base bias or collector feedback bias It provides better bias stability 4 base bias with collector and emitter feedbacks It is a combination of (2) and (3) above 5 emitter bias with two supplies (Fig 583) This circuit uses both a positive and a negative supply voltage Here, base is at approximately 0 volt ie V 0 6 voltage divider bias (Fig 585) It is most widely used in linear discrete circuits because it provides good bias stability It is also called universal bias circuit or base bias with one supply Each of the above circuits will now be discussed separately 589 ase ias It has already been discussed in Art 5820 and is shown in Fig 5825 For such a circuit, S ( + β) β and K β

7 Load Lines and DC ias Circuits ase ias with Emitter Feedback This circuit is obtained by simply adding an emitter resistor to the base bias circuit as shown in Fig 588 At saturation, is essentially zero, hence V CC is distributed over and IC( sat) + RL 2 can be found as follows : Consider the supply, base, emitter and ground route Applying Kirchhoff s Voltage Law, we have IR VE IE + 0 Fig 588 or V CC I + V E + (i) Now I /β and Substituting these values in the above equation, we have C V I R CC + VE + IC β VE IC + R / β + R / β neglecting VE (we could have applied the β-rule given in Art 5724) 3 collector-to-ground voltage V C 4 emitter-to-ground voltage V E 5 + R / + R / S + R /( +β ) + R / βrå 6 The β-sensitivity of this circuit is Kβ +β / Example 585 For the circuit shown in Fig 589, find (i) (sat), (ii), (iii) V C, (iv) V E, (v) and (vi) K β Solution (i) 30 IC( sat) 0 ma + RL (ii) actual IC 75 ma + R / β + 300/00 (iii) V C V (iv) V E V (v) V C V E V Fig 589 (vi) K β + 00 / Example 586 The base-biased transistor circuit of Fig 580 is subjected to increase in junction temperature from 25 C to 75 C If β increases from 00 to 50 with rising temperature, calculate the percentage change in Q-point values (, ) over the temperature range Assume that V E remains constant at 07 V Solution At 25 C VE 2 07 I 03mA 3 R V E 300K 00 K +V CC I V E V CC 30V 2K V E V C V C

8 2226 Electrical Technology +2V V CC R C K Fig 580 βi ma R C 2 ( ) 635 V R C 2 ( ) 6 35 V At 25 I 03 ma β I ma 2 ( )352 V % (increase) % (decrease) 635 It is seen that Q-point is very much dependent on temperature and makes the base-bias arrangement very unstable 58 ase ias with Collector Feedback This circuit (Fig 58) is like the base bias circuit except that base resistor is returned to collector rather than to the V CC supply It derives its name from the fact that since voltage for is derived from collector, there exists a negative feed back effect which tends to stabilise against changes in β To understand this action, suppose that somehow β increases It will increase as well as but decrease V C which is applied across Consequently, I will be decreased which will partially compensate for the original increase in β (i) (sat) / since 0 (ii) V C (I + ) V CC Also, V C I + V E Equating the two expressions for V C, we have I IC + V E _ Fig 58 V CC ( +I ) I + V E V CC Since I /β, we get IC R + V V I R β E CC C L VE IC R + R / β R + R / β L L This is also the approximate value of (again, we could take the help of β-rule) The β- sensitivity factor is given by IC Kβ β RL / R IC( sat) + R / RL S + R /( +β ) R R + R / β L L Example 587 In Fig 58, V CC 2 V, V E 07 V, K, 00K, β 00 Find (i), (ii), (iii) I,(iv) K β and (v) S

9 Load Lines and DC ias Circuits Solution (i) IC IE 56 ma + 00/00 (ii) 2 (565 ) 635 V (iii) I / β 565/ µa (iv) K 05 (v) + 00 / / S /0 582 ase ias with Collector and Emitter Feedbacks In the circuit of Fig 582, both collector and emitter feedbacks have been used in an attempt to reduce circuit sensitivity to changes in β If β increases, emitter voltage increases but collector voltage decreases It means that voltage across is reduced causing I to decrease thereby partially off-setting the increase in β Under saturation conditions, V CC is distributed over and Assuming I to be negligible as compared to, we get, (sat) / ( + ) Actual value of is VE R + R + R / β E L going via because is unknown V V ( I + I ); R V I R C CC C L CC C L V I R I R V V V E E E C E; CE C E VCE IC ( RL + ) R /( RL) S R / β ( R + R ) It can be proved that E L K β I +β ( R + R )/ R I E L C( sat) Obviously, K β will be degraded with increase in Example 588 For the circuit shown in Fig 583, find (a) (sat) (b) and (c) K β Neglect V E and take β 00 Solution (a) (sat) 5/(0 + 0) 075 ma 5 (b) IC 06mA + RL + R / β / (0 + 0) 3 V (c) K β (0 + 0) / 50 or K β /(sat) 06/07502 Obviously, K β will be degraded with increase in 583 Emitter ias with Two Supplies This circuit gives a reasonably stable Q-point and is widely used whenever two supplies (positive and negative) are available Its popularity is due to the fact that is essentially independent of β C I 500 K Fig V CC 0 K ( +I ) 5V Fig 583 V E 0 K V C

10 2228 Electrical Technology It can be shown that V 0 and V E V E Starting from ground and going clockwise round the base-emitter circuit, we get according to KVL I V E + V EE 0 or I + V EE V E (i) Now, I /β /β Substituting this in (i) above we have IER V EE VE + IE VEE VE or IE β + R / β If V EE» V E and» /β, V EE / If V E is the emitter to ground voltage, then I V E V E 0 I + R _ V E V EE +V CC or V E (I + V E ) (V E + /β) V E Fig R / For this circuit, S and K + R / β +β / Example 589 For the circuit of Fig 585, find (i), (ii), (iii) V C, (iv) V E, (v), (vi) stability factor and (vii) K β for a β of 50 Take V E 07 V (Electronics-II, angalore Univ 995) VEE VE 0 07 Solution (i) IE 046 ma + R / β 20+ 0/50 (ii) 046 ma (iii) V C V (iv) V E (V E + /β) ( /50) 08 V (v) V C V E 54 ( 08) 62 V + R / + 0/20 (vi) S R / β R + 0/ (vii) K β R / R /0 E β Fig Voltage Divider ias The arrangement is commonly used for transistors incorporated in integrated circuits (ICs) The name voltage divider is derived from the fact that resistors R and R 2 form a potential divider across V CC (Fig 586)* The voltage drop V 2 across R 2 forward-biases the emitter whereas V CC supply reverse-biases the collector As per voltage divider theorem V 2 R 2 /(R + R 2 ) As seen, V E V 2 V E VE V2 VE V2 IE Also, V C R + V R 2 V E _ 2 Fig 586 +V CC V E V C * It is also known as Universal ias Stabilization Circuit

11 Load Lines and DC ias Circuits 2229 V C V E V CC ( + ) As before, I C(sat) RL + It is seen from above calculations that value of β was never used anywhere The base voltage is set by V CC and R and R 2 The dc bias circuit is independent of transistor β That is why it is such a very popular bias circuit Kβ +β /( R R 2) + ( R R2)/ Re S + ( R R2)/( +β ) + ( R R2)/ + ( R R )/ β R 2 Using Thevenin s Theorem More accurate results can be obtained by Thevenizing the voltage divider circuit as shown in Fig 587 The first step is to open the base lead at point A and remove the transistor along with and thereby leaving the voltage divider circuit behind as in Fig 587 (a) and (b) E R V V V R R R R R ( ) 2 2 th 2 CC and th 2 R+ R2 R+ R2 The original circuit is reduced to that shown in Fig 587 (c) where V th V ; R th Now, applying KVL to the base-emitter loop, we get V I V E 0 Substituting the value of ( + β) I in (i) above, we get V VE I R + ( +β) However, if we substitute the value of I /( + β), we get V VE IE + R /( +β) V CC ( + ) Fig 588 The above results could also be obtained directly by applying β-rule (Art 582) Using β-rule +V CC R R A A R 2 V 2 V th R 2 R th As per β-rule (Art 582) when is transferred to the base circuit, it becomes ( + β) and is in parallel with R 2 as shown in Fig 88 Now, V CC drops over R and R 2 ( + β) I R R th V (a) (b) (c) Fig V E +V CC _ V th

12 2230 Electrical Technology R2 ( +β) V R+ R2 ( +β) V E V V E ; V E / and so on Example 580 For the circuit of Fig 589, find (a) (sat), (b), (c), (d) K β Neglect V E and take β 50 (Electronics, Gorakhpur Univ) Solution 20 (a) IC( sat) RL + R E ma (b) V 2 / 6/6 ma (c) ( + ) 20 (2 + 6) 2 V (d) R R 2 84/20 42 K Fig 589 K β /42 Example 58 For the circuit shown in Fig 5820 (a), draw the dc load line and mark the Q-point of the circuit Assume germanium material with V 03 V and β 50 (Electronics-I, MS Univ 99) Solution ( cut off ) 20 V 20 IC( sat) 2mA R + R K 25 K (a) Approximate Method R2 25 Fig 5820 V V R + R 2 25 V2 VE 4 03 IE 062mA 6 ( + ) V This Q-point (38 V, 062 ma) is shown in Fig 582 (a) As seen from Fig 5820 (b) V 20 25/25 4 V V VE I R + ( +β) µa I C (a) 20 V 6K β I K 0565 ma ( + β I 576 µa 0576 ma R 20 K V 4 V (b) 20 V 4K 6K ma ma 2 2 L 062 Q 0565 Q V (a) (b) E Fig V 2 4 K 2K 6K 6K 20 V

13 Load Lines and DC ias Circuits 223 R C V The new and more accurate Q-point (43 V, 0565 ma) is shown in Fig 582 (b) 585 Load Line and Output Characteristics In order to study the effect of bias conditions on the performance of a CE circuit, it is necessary to superimpose the dc load line on the transistor output ( / ) characteristics Consider a silicon NPN transistor which is connected in CE configuration (Fig 5822) and whose output characteristics are given in Fig 5823 Let its β 00 First, let us find the cut-off and saturation points for drawing the dc load line and then mark in the Q-point (sat) 0/2 5 ma point in Fig 5823 (cut-off) 0 V point A in Fig 5823 The load line is drawn in Fig 5823 below Fig 5822 Fig 5823 VE 0 07 Actual I 20ìA R 470 βi µa 2 ma V This locates the Q-point in Fig 5823 Suposse an ac input signal voltage injects a sinusoidal base current of peak value 0 µa into the circuit of Fig 5822 Obviously, it will swing the operating or Q-point up and down along the load line When positive half-cycle of I is applied, the Q-point shifts to point C which lies on the (20 + 0) 30 ma line Similarly, during negative half-cycle of input base current, Q-point shifts to point D which lies on the (20 0) 0 µa line y measurement, at point C, 29 ma Hence, V Similarly, at point D, measures µahence, V It is seen that decreases from 6 V to 42 V ie by a peak value of (6-42) 8 V when base current goes positive On the other hand, increases from 6 V to 78 V ie by a peak value of (78 6) 8 V when input base current signal goes negative Since changes in represent changes in output voltage, it means that when input signal is applied, I varies according to the signal

14 2232 Electrical Technology amplitude and causes to vary, thereby producing voltage variations Incidentally, it may be noted that variations in voltage drop across are exactly the same as in Steady drop across when no signal is applied V When base signal goes positive, drop across V When base signal goes negative, ma and drop across 2 22 V Hence, voltage variation is V during positive input half-cycle and V during negative input half-cycle Obviously, rms voltage variation V Now, proper dissipated in RL by ac component of output voltage is P ac 27 2 /2 08 mw and P dc 2 R mw Total power dissipated in 88 mw 586 AC Load Line It is the line along which Q-point shifts up and down when changes in output voltage and current of an amplifier are caused by an ac signal This line is steeper than the dc line but the two intersect at the Q-point determined by biasing dc voltage and currents AC load line takes into account the ac load resistance whereas dc load line considers only the dc load resistance (i) DC Load Line The cut-off point for this line is where It is also written as (cut-off) Saturation point is given by / It is also written as (sat) It is represented by straight line AQ in Fig 5824 (ii) AC Load Line The cut-off point is given by (out-off) Q + Q R ac where Rac is the ac load resistance* Saturation point is given by (sat) Q + Q /R ac It is represented by straight line CQD in Fig 5824 The slope of the ac load line is given by y /R ac It is seen from Fig 5824 that maximum possible positive signal swing is Q R ac Similarly, maximum possible negative signal swing is Q In other words, peak-signal handling capacity is Fig 5824 limited to Q Rac or Q whichever is smaller Example 582 Draw the dc and ac load lines for the CE circuit shown in Fig 5825 (a) What is the maximum peak-to-peak signal that can be obtained? (Applied Electronics, Kerala Univ 99) Solution DC Load Line [Fig 5825 (b)] (cut-off) 20 V (point A) and (sat) /(R + ) 20/5 4mA (point ) Hence, A Q represents dc load line for the given circuit Approximate bias conditions can be quickly found by assuming that I is too small to affect the base bias in Fig 5825 (a) * Written as r L in Art 594

15 V /(4 + 6) 4 V If we neglect V E, V 2 V E ;, VE V2 4 IE 2 2 ma Also, 2 ma Hence, Q 2 ma The corresponding value of Q can be found by drawing dotted line in Fig 5825 (b) or may be calculated as under : AC Load Line Cut-off pont, (cut-off) Q + Q R ac Now, for the given circuit, ac load resistance is R ac R C 3K Cut-off point V [Fig 5825 (b)] VCEQ 0 Saturation point, Icsat ( ) ICQ mA R 3 C v S 4K 2KV E ac R 6 K Load Lines and DC ias Circuits 2233 V 2 Fig 5825 Hence, line joining 6-V point and 53 ma point gives ac load line as shown in Fig 5825 (b) As expected, this line passes through the Q-point Now, Q R ac V and Q 0 V Taking the smaller quantity, maximum peak output signal 6 V Hence, peak-to-peak value V Example 583 Find the dc and ac load lines for CE circuit shown in Fig 5826 (a) Solution The given circuit is identical to that shown in Fig 5825 (a) except for the addition of 6-K resistor This makes R AC 3 K 6 K 2 K because collector feeds these two resistors in parallel The dc loadline would remain unaffected Change would occur only in the ac load line AC Load Line (cut-off) O + Q R ac Fig V (sat) O + O /R ac 2 + 0/2 7 ma Example 584 Draw the dc and ac load lines for the C circuit shown in Fig 5827 (a) Which swing starts clipping first? Solution The dc load line passes through cut-off point of 30 V and saturation point of V CC / ma Now, 20/40 05 ma ; 05 ma; Q 05 ma V C R C V ; V CQ 5 V R R 2 6 K 3K 3K 6K R 2 V 2 R 4K E V E 2K C 2 V CC 20V ma Q G (a) (b) C V CC 20V v out ma (a) (b) ac Load Line dc Load Line Q 6 A V Q V

16 2234 Electrical Technology V EE -20V 30V 40K 30K V CC R C ma 5 0 C C 2 v S 30K (a) Q V V C (b) 225 Hence, dc operating point or Q-point is (5 V, 05 ma) as shown in Fig 5827 (b) The cut-off point for ac load line is V CQ + Q R AC Since collector sees an ac load of two 30 K resistors in parallel, hence R ac 30 K 30 K 5 K V CQ + Q R ac V Saturation current for ac line is Q + V CQ /R ac /5 5 ma The line joining these two points (and also passing through Q) gives the ac load line as shown in Fig 5827 (b) Note Knowing ac cut-off point and Q-point, we can draw the ac load line Hence, we need not find the value of saturation current for this purpose As seen, positive swing starts clipping first because Q R ac is less than V CQ Obviously, maximum peak-to-peak signal that can be obtained from this circuit V Example 585 For the circuit shown in Fig 5827 (a), find the approximate value of source voltage us that will cause clipping The voltage source has an internal resistance of K Solution As found out in Ex 584, the maximum swing of the unclipped output V Vout Rac 5 Now, A 5 υ V R s V 5V out p p VS V 5 A υ S p-p Fig 5827 Tutorial Problems No 58 For the C circuit shown in Fig 5828, find the approximate location of Q-point [0 V, 2 ma] 2 For the circuit of Fig 5829, find (a) dc operating-point, (b) maximum peak-to-peak unclipped signal [(5 V, 05 ma) ; 0 V p p ] 3 What is the maximum peak-to-peak signal that can be obtained from the circuit of Fig 5830? [20 V p p ] 4 Find the value of maximum peak-to-peak output of signal that can be obtained from the circuit of Fig 583 [0 V p p ]

17 Load Lines and DC ias Circuits V 20V -25V 20V -0V 30V 0K 5K 50K 0K 5K 0K 30V 20K R C 20K V C 50K 30K -5V Fig 5828 Fig 5829 Fig 5830 Fig 583 OJECTIVE TESTS 58 The dc load line of a transistor circuit (a) has a negative slope (b) is a curved line (c) gives graphic relation between and I (d) does not contain the Q-point 2 The positive swing of the output signal in a transistor circuit starts clipping first when Q- point of the circuit moves (a) to the centre of the load line (b) two-third way up the load line (c) towards the saturation point (d) towards the cut-off point 3 To avoid thermal run away in the design of analog circuit, the operating point of the JT should be such that it satisfies the condition (a) /2 V CC (b) < /2 V CC (c) > /2 V CC (d) < 078 V CC 4 In the case of a JT amplifier, bias stability is achieved by (a) keeping the base current constant (b) changing the base current in order to keep the and V C constant (c) keeping the temperature constant (d) keeping the temperature and the base current constant 5 For a transistor amplifier with self-biasing network, the following components are used : R 4 k Ω, R 2 4 k Ω and k Ω the approximate value of the stability factor S will be (a) 4 (b) 3 (c) 2 (d) 5 6 A transistor circuit employing base bias with collector feedback has greater stability than the one without feedback because (a) decrease in magnitude (b) V E is decreased (c) of negative feedback effect (d) becomes independent of β 7 The universal bias stabilization circuit is most popular because (a) does not depend on transistor characteristics (b) its β-sensitivity is high (c) voltage divider is heavily loaded by transistor base (d) equals 8 Improper biasing of a transistor circuit leads to (a) excessive heat production at collector terminal (b) distortion in output signal (c) faulty location of load line (d) heavy loading of emitter terminal 9 The negative output swing in a transistor circuit starts clipping first when Q-point (a) has optimum value (b) is near saturation point (c) is near cut-off point (d) is in the active region of the load line 0 When a JT is employed as an amplifier, it operates

18 2236 Electrical Technology (a) in cut-off (b) in saturation (c) well into saturation (d) over the active region Which of the following method used for biasing a JT in integrated circuits is considered independent of transistor beta? (a) fixed biasing (b) voltage divider bias (c) collector feedback bias (d) base bias with collector feedback 2 The voltage V 0 of the circuit shown in Fig 5832 is, 2 +5 V (a) 5 V (b) 3 V (c) 25 V (d) zero 3 The collector voltage V C of the circuit shown in Fig 5833, is approximately (a) 2 V (b) 46 V (c) 96 (d) 86 V 20 k 2k +0V V C 5 C V o 20 k 43 k E Fig 5832 Fig 5833 ANSWERS (a) 2 (d) 3 (c) 4 (a) 5 (b) 6 (b) 7 (a) 8 (b) 9 (b) 0 (d) (b) 2 (d) 3 (a)