3 Frequency Divider. LAB Objectives. 3.1 Background

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1 Frequency Divider LAB Objectives This LAB experiment builds on the previous experiment to introduce more advance topics in schematic editing and system simulation using Proteus Virtual System Modeling (VSM). The experiment is design to guide the students through the process of designing, editing and simulating a frequency-divider circuit based on the modulo-n counter designed in the previous experiment. The LAB covers more advance schematic editing and simulation topics such as multiple design sheets and virtual instruments.. Background In this experiment, we will design an odd frequency divider with 50% duty cycle. A frequency divider, also called a clock divider, is a circuit that takes an input signal of a frequency, fin, and generates an output signal of a frequency : fout = fin /n where n is an integer. Figure. shows an example of the output of a frequency divider with fin = 8kHz and n = 4. The duty cycle of a clock signal is the percentage of the time the signal is high in one clock cycle. For example a clock signal with a 60% duty cycle is high during 60% of its cycle and low for the remaining 40% as illustrated in Figure.. The frequency divider circuit that we are going to design will divide the input frequency by 5 with a 50% duty cycle. This circuit will designed based on the modulo-5 binary counter that we have implemented in the previous experiment. Conceptually, the easiest way to create an odd frequency divider circuit with a 50% duty cycle is to generate two reference clocks fx and fy at half the desired output frequency (i.e. fx = fy = fin /) with a constant 90 deg phase difference between the two reference

2 Frequency Divider f in = 8 khz - T in = /f in = 0. 5 x 0s e c o n d s T in f out = f in /n = 8/ 4 = khz,t out = /f out = 0. 5 x - 0 s e c o n d s f out = khz T out Figure. The output of a frequency divider with f in = 8kHz and n = 4. 60% 40% T Figure. Example of a clock signal with 60% duty cycle. clocks. You can then generate the output frequency by exclusive-oring the two waveforms together. Because of the constant 90 deg phase offset, only one transition occurs at a time on the input of the exclusive-or gate, effectively eliminating any glitches on the output waveform. The two reference clocks with 90 deg phase difference can be generated with the help of a modulo-n counter. The first reference clock f x is set high with the rising edge of the clock whenever the count equals 0, whereas the second reference clock f y is set high with the falling edge of the clock whenever the count equals n/. As an example, consider the timing diagram of a frequency divider by 5 shown in Figure.. The first reference clock f x is set high with the rising edge of the clock on count equals 0. On the other hand, the second reference clock f y is set high with falling edge of the clock on count equals 5/ = f in f x f y f o u t Figure. Timing diagram of a frequency divider by 5 with 50% duty cycle.

3 J J 4 4 S S 6 6. Required Components In order to create an odd frequency divider (e.g. divide by, 5, 7,..., etc.) with a 50% duty cycle using the previously described approach, we can apply the follow procedure (See Figure.4) :. Create a modulo-n counter that counts from 0 to (n ), where n is the natural number by which the input reference clock is supposed to be divided (n is an odd number).. Take two JK flip-flops, x and y, and connect their inputs as follows : (a) J x = K x = (Count == 0) (b) J y = K y = (Count == n/ ). Connect the clock inputs of the two flip-flops as follows : (a) CLK x = f in (b) CLK y = ˉ f in 4. Exclusive-OR the outputs of the two flip-flops (f x and f y ) to generate the output frequency (i.e. f out = f x f y ). V CC N O T 7 4 LS 0 4 X O R M O D _ 5_ CO U N T E R Q 0 N O R 7 4 LS 7 X CLK K 7 4 LS Q Q LS 8 6 F o u t F i n 5 CLK Q Q M O D 5CN T R Q 4 A N D 7 4 LS 0 8 Y CLK K 7 4 LS Q Q 5 Figure.4 Frequency divider by 5 with 50% duty cycle. Exercise. Show how to design a frequency divider by with 50% duty cycle using modulo- binary counter and two JK flip-flops. Repeat the exercise for frequency divider by 4, 6 and 7.. Required Components. Hex Inverters (74LS04). Triple -Input Positive NOR Gates (74LS7). Quad -Input XOR Gate (74LS86) 4. Dual Negative-Edge-Triggered JK Flip-Flop With Set (74LS). Schematic Entry In this section, we will design the frequency divider by 5 with 50% duty cycle. It is common in larger designs to split the schematic into multiple sheets. This serves both to reduce clutter

4 4 Frequency Divider on the schematic and also to organize the design into logical blocks. ISIS fully supports this methodology and we have arranged our tutorial design into two sheets in order to cover the relevant procedures. The work we have done so far to design the modulo-5 counter has been to complete the first sheet. The second part of our design (i.e. designing the logic for the two reference clocks) will be done on a separate sheet. The procedure to design our frequency divider circuit is summarized below :. Open the modulo-5 counter project file created in LAB and save it with a new name of your choice (say "frequency_divider.pdsprj").. Get the required circuit components from the Library.. Add a new sheet to you design (Section..). 4. On the newly added sheet, place the circuit components required for building the logic of the two reference clocks. 5. On the same sheet, place an oscilloscope device (Section..). 6. Connect the circuit components as shown in Figure.6. Note that in order to connect two terminals in two separate design sheets, you need to assign the same name to both terminals... Adding Sheets to a Design To add a new sheet to the schematic we simply invoke the command from the Design menu as shown in Figure.5. Figure.5 Add new design sheet.. Place Virtual Instruments In this experiment, we need to use an oscilloscope device to compare the input and output frequencies of the frequency divider circuit. To insert an oscilloscope choose Virtual Mode then select OSCILLOSCOPE from Instruments List Box as shown in Figure.7.

5 . Schematic Entry 5 Figure.6 Schematic of the reference clocks. Figure.7 Inserting an oscilloscope.

6 6 Frequency Divider.4 Testing the Design Run the simulation and observe the input and output frequencies on the oscilloscope as shown in Figure.8. If the oscilloscope window does not pop-up when you run the simulation, then you need to open it manually by right clicking on the oscilloscope component and then select "Digital Oscilloscope". Figure.8 Comparing the input and output frequencies of the frequency divider using the oscilloscope. We will refer to Figure.9 to illustrate the usage of the oscilloscope. This oscilloscope consists of three main parts : () input channels, () display scree and () control panels. Figure.9 Illustrating different parts of the oscilloscope. The considered oscilloscope has four input channels labeled A, B, C and D as shown in

7 .4 Testing the Design 7 Figure.6. You can trace a given signal by connecting its terminal (or wire) to one of the four channels. The trace signals connected to the input channels of the oscilloscope will be displayed on the screen. The x-axis of the screen represents time, while the y-axis represents voltage. The control panels consist of a trigger control, horizontal control and channel control (one for each channel). The trigger control panel, as illustrated in Figure.0, provides the user with the following control functions : Change the position the horizontal reference line. Specify signal display type : analog (AC) or digital (DC). Complement the input signals display. Enable/disable continuous tracing of input signals. Enable/disable one-shot tracing of input signals. This option works for periodical signals only, and it will freeze the display so the user can perform any required analysis for the input signal. Enable/disable cursors. When this control is enabled, a cursor can be inserted by clicking on any place on the display screen. When a cursor is inserted it will display the time measure between the vertical reference line and the inserted cursor. Focus the display by selecting the main source of input channels. This is useful when displaying signals with large difference in their frequencies which my distort the display. P osition the horiz ontal referenc e line Change signal display from analog to digital and vise versa Complement signal E nab le/ disab le c ontinu ou s trac ing of inpu t signals E nab le/ disab le one shot trac ing of inpu t signals ( for periodic al signals) E nab le/ disab le c u rsors S elec t main inpu t c hannel Figure.0 Trigger panel functions. The horizontal control panel, as illustrated in Figure., provides the user with the following control functions : Change the position of the signal trace on the x-axis. Change time division scale which allows the user to zoom-in or zoom-out on the x-axis.

8 8 Frequency Divider Change the position of the signal trace on the x-axis Change tim e d iv ision scale Figure. Horizontal panel functions. The channel control panel, as illustrated in Figure., provides the user with the following control functions for the specified channel (A, B, C or D) : Change the position of the signal trace on the y-axis Change the type of signal display : analog (AC), digital (CD), ground (GND) or turn the signal off (OFF). Complement the signal trace. Combine two signals (A + B or C + D) in one signal trace by adding their amplitudes. Change voltage division scale which allows the user to zoom-in or zoom-out on the y-axis. Change the position of the signal trace on the y-axis Change the type of signal d isplay Com plem ent the signal trace A d d tw o signals Change v oltage d iv ision scale Figure. Channel panel functions. Exercise. Referring to Figure.6, complete the reference clocks circuit on the new design sheet, run the simulation and with the help of your instructor learn how to utilize the oscilloscope to compare the input and output frequencies.