Raimond LAPTIK DIGITAL DEVICES. Project No VP12.2ŠMM07K The Essential Renewal of Undergraduates Study Programs of VGTU Electronics Faculty


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1 Raimon LAPTIK DIGITAL DEVICES Project No VP2.2ŠMM7K47 The Essential Renewal of Unergrauates Stuy Programs of VGTU Electronics Faculty Vilnius Technika 22
2 VILNIUS GEDIMINAS TECHNICAL UNIVERSITY Raimon LAPTIK DIGITAL DEVICES A Laboratory Manual Vilnius Technika 22
3 R. Laptik. Digital Devices: A Laboratory Manual. Vilnius: Technika, p. [4,35 author s sheets, ]. The goal of this manual for laboratory works is to provie means for stuents to prepare for laboratory works in the subject of igital evices. The manual is for the Faculty of Electronics of VGTU, stuy programs in electronics engineering, automation, telecommunications engineering, computer engineering, information systems engineering. The main topics are: number systems an binary coes; simulation software EWB an Multisim; basic logic gates; minimization of logic functions; TTL, CMOS an BiCMOS switches; esign of arithmetic an combinational logic evices; combinational logic IC evices; basic latches, registers an counters. Each work is presente with objectives, short theory an methoology, example of the task an control questions to check mastering of the theory. The publication has been recommene by the Stuy Committee of VGTU Electronics Faculty. Reviewe by: Prof Habil Dr Raimunas Kirvaitis, VGTU Department of Electronic Systems, Prof Habil Dr Vygauas Kvearas, VGTU Department of Electrical Engineering This publication has been prouce with the financial assistance of Europe Social Fun an VGTU (Project No VP2.2ŠMM7K47). The book is a part of the project The Essential Renewal of Unergrauates Stuy Programs of VGTU Electronics Faculty. This is an eucational methoology book, No 336S, issue by VGTU Press TECHNIKA Language eitor Via Bėkštienė Typesetter Laura Petrauskienė eisbn oi:.3846/336s Raimon Laptik, 22 Vilnius Geiminas Technical University, 22
4 Contents Introuction Introuction into number systems an binary coes EWB an Multisim. Basic logic gates Minimization of logic functions Algebraic minimization of logic functions bjt switch. Investigation of RTL an DTL gates Investigation of Stanar TTL gate Investigation of mos an cmos switches Investigation of BiCmos switch Design of arithmetic evices Gate level esign of other combinational logic evices Combinational logic ic evices Basic synchronous latches Registers Counters References
5 introuction The goal of this manual for laboratory works is to provie means for stuents to prepare for laboratory works in the subject of igital evices. Each work is presente with objectives, short theory, methoology, example of the task an control questions to check mastering of the theory. At the en of each work the literature is presente where the stuent can get more information regaring the subject. During the laboratory work the tutor presents an iniviual task for each stuent. Each task consists of two parts. The main part is obligatory an shoul be fulfille before starting the aitional part. The maximum evaluation of the main part is 6 points, an the maximum evaluation of the aitional part is 4 points. In the majority of the tasks stuents will esign various igital circuits. Electronics Workbench an Multisim software packages are use for circuit simulation, so the stuent has the opportunity to check the operation of the circuit esigne an to show the operation of the circuit to the tutor. 4
6 . introuction into number systems an binary coes Objectives of the Work The goal of this introuction is to provie the basic theory for stuents to get acquainte with ifferent positional number systems an binary coes an to be able to perform simple arithmetical operations in various number systems. Theory Introuction It is crucial to unerstan composition of number systems an binary coes because the subject of igital evices is base on this knowlege. The majority of number systems are positional. In positional number system, the base of the system an position of igit or symbol of this number system together etermine the final value of the number. The most popular number system is ecimal. It is calle ecimal because of ten symbols from to 9 which are use to represent one position of a multipositional number. The number of symbols use to represent one position is calle the base B or raix of the system an is usually inicate by a subscript. The position of a symbol in a number etermines value of the symbol. In ecimal system B = an every position in the number has the value of in power n, where n is a position calculate from the raix point. Values of positions in ecimal system are presente in Table..
7 Table. Values of positions in ecimal system Position Value With each position to the left, value of position increases times, with each position to the right value of position ecreases times. So to the left of the raix point in ecimal system there is the position of ones, the position of tens, then hunres an so on. To the right of the raix point there is the position of tenths, the position of hunreths an so on. The same rules are applie to every positional number system. An infinite number of positional number systems exists with base B, however the most popular are binary, octal, ecimal an hexaecimal systems. Binary system In conventional arithmetic, number system base on ten symbols is use. However, igital circuits use in computers an other igital systems usually operate with two istinct voltage levels, expresse as s an s. Number system with the basic symbols an is calle binary an it s base is B = 2. Values of positions of bits in binary system are presente in Table.2. Table.2 Values of positions in binary system Position Value
8 Example of conversion from the binary system to ecimal: = = = 6.25 (.) Conversion is performe by multiplying the symbol of each position by the base raise into the power of position. Conversion from ecimal system to binary is a little bit more complicate as it requires ivision of the integer part an multiplication of the fractional, thus both parts shoul be converte separately an then ae. Example of conversion from ecimal to binary is shown in Fig... At first the number is ivie into integer an fractional parts. Then integer part is continuously ivie by the base transferring the result into ivien for the next ivision until the result is zero. The remainer of the ivision is taken as a resulting igit for one position of binary system. The binary number is fille with values starting from the right so, that the first remainer will be the rightmost igit. In the case of fractional part, the number is being multiplie by a base an the first integer part of the result is written into the leftmost position. The result without the integer part is taken as the multiplican for the next multiplication. Multiplication is continue until the result is zero, or in the case of infinite fraction, until the require precision is reache. Infinite fraction is inicate by a repeating sequence of numbers. For example:.3 = or.7 =
9 6.25 = / 2 = 3, remainer 3 / 2 =, remainer / 2 =, remainer / 2 =, stop 6.25 = +. = =.5, integer part.5 2 =., integer part. 2 =., stop Fig.. Decimal to binary conversion Octal system Octal number system with the base B = 8 is using eight symbols from to 7 to express the value of one position. Table.3 Values of positions in octal system Position Value Conversion from octal to ecimal is performe in a similar way as from binary to ecimal: 8
10 = = = (.2) Conversion from ecimal to octal system is also performe via the ivision of the integer part an multiplication of the fractional part (Fig..2) = / 8 = 3, remainer 2 3 / 8 =, remainer 3 / 8 =, stop = = = 2., integer part 2. 8 =., stop Fig..2 Decimal to octal conversion Octal number system is less frequently use than binary or hexaecimal, however it is still popular because of the ease of the conversion from binary to octal system an vice versa. In general all number systems coul be easily converte if the base of one system coul be expresse as the base of other system raise to the integer power. An the exponent will point how many positions are neee in the other system to express one position in the current system. For example, the relation of the bases of octal an binary systems 3 is 8 = 2, so one position in octal system will take three positions 9
11 in binary system. Again, the position is calculate from the raix point. This coul be use for irect conversion:. = = (.3) Hexaecimal system Hexaecimal system is quite often use to express binary numbers in a more reaable form as hexaecimal number is usually four times shorter than binary. Hexaecimal system with base B = 6 is using 6 ifferent symbols from to F (numbers from to 9 an letters from A to F) to express values from to 5. Table.4 Values of positions in hexaecimal system Position Value Conversion from hexaecimal system to ecimal is performe in a similar way as from binary to ecimal: 6 = B3F.A B F 6 A 6 6 = = = (.4) Conversion from ecimal to hexaecimal is the same as in the majority of positional number systems (Fig..3).
12 = / 6 = 79, remainer 5 F 79 / 6 =, remainer 3 / 6 =, remainer B /6 =, stop = B 3 F +.A = B3F.A =.625, integer part A =., integer part. 6 =., stop Fig..3 Decimal to hexaecimal conversion Conversion from hexaecimal to binary an vice versa is 4 straightforwar as their bases are relate as 6 = 2, so one position in hexaecimal system is expresse as four positions in binary system. Position is always calculate from the raix point:. 2 = 2c c. 3. (.5) 2 c. = Binary coe ecimals Binary coe ecimal (BCD) is a family of binary coes for ecimal number encoing with s an s. It is known that conver
13 sion between ecimal an binary numbers requires a lot of calculations. In BCD coe a fixe number of bits is use to encoe one position of ecimal number. Also when BCD coe is use its name is inicate by a subscript an the name of the coe usually consists of the weights for each position of the bit: = = = 8+ 5= 4+ 3= 2+ = = = 4+ 3= 2+ 3= = Bc842 Bc422 Bc842 4 = Bc422 Gray coe. (.6) Gray coe is a cyclic binary coe where only one bit is changing when the number is increase or ecrease. Such coe is use in the circuits where fluctuation of the voltage is not esirable. For example, the counter output is connecte to the wie bus an if binary system is use then, when an overflow occurs an the counting starts from, there is an impact on the bus voltage, when a lot of bits are switche at the same time. On the contrary, when Gray coe is use, only one bit will change uring overflow. Conversion from binary system to Gray coe is performe via XOR (exclusive OR) operation. XOR operation, enote with symbol, is pointing if two bits are ifferent or not. If two bits are ifferent, then the result is, if two bits are the same then the result is. During the first step, the most significant bit (one from the left) is written own (Fig..4 a), next XOR operation is performe with the bit to the right an the result is written into the next free position (Fig..4 b). This step is repeate until all the bits are converte. 2
14 2 2 G G a) b) 2 2 G G c) Fig..4 Binary to Gray conversion ) 2 a) G G 2 b) G 2 G 2 c) Fig..5 Gray to binary conversion ) 3
15 In the similar way the conversion from Gray coe to binary system is one (Fig..5). The first step is exactly the same the left bit is written own. Next XOR operation is performe between the written own bit an the next bit in Gray coe an the result is written into the next free position. XOR operation is repeate until all the bits are calculate. The reflective property of Gray coe (Fig..6) coul be use to generate a sequential set of numbers by reflecting the leftmost 2 position every 2 bits, the secon position every 2 bits, the thir 3 position every 2 an so on. Fig..6 Reflective property of Gray coe Arithmetical operations In the majority of positional number systems arithmetical operations are performe in the same way as in ecimal system. In aition an subtraction numbers shoul be aligne relative to the raix point. Position of the raix point is static (oes not change) in aition an subtraction. However in multiplication alignment of numbers is not necessary, as the position of the raix point in the result shoul be recalculate accoring to the sum of positions in the fractional parts of the numbers being multiplie. 4
16 In aition when there is an overflow in one position the value is being carrie into another position to the left, in the same way as it is one in ecimal system. Example of binary aition is provie: (.7) Overflow in octal system happens when the sum of igits is 8 or greater. Aition in octal number system: (.8) In hexaecimal system the overflow happens when the sum is 6 or greater: 37 A6 F A F4e 7.B B 5BA 7c (.9) Subtraction is also performe in a similar way as in ecimal system. During the unerflow, the borrowing shoul be one from the next position to the left, if that position is empty then the next one is consiere. The borrowe unit from the left position is expresse as B units in the current position. In the case of binary subtraction B = 2 an the borrowe unit from the left is transforme into exactly two units in the current position: 5
17 one is consiere. Borrowe unit from the left position is expresse as B units in the current position. in the case of binary subtraction B = 2 an borrowe unit from the left is transforme into exactly two units in the current position: ii i (.) (.).2 Binary fractional numbers is performe by by Binarymultiplication multiplicationof of fractional numbers is performe shifting the raix point to the rightmost position an multiplying shifting the raix point to the rightmost position an multiplying the the numbers as integers. After the result is obtaine the raix point 4 position is recalculate from the initial numbers by aing number of positions in fractional parts. If in the first number the fractional part was mae of two positions an in the secon number of one position, then the resulting number shoul have 2 + = 3 positions in fractional part. An example of binary multiplication: (.).2 Tasks During the laboratory work you will receive ifferent tasks from the tutor. Example of the obligatory task (for 6 points out of possible):. Multiply the given numbers an write own the result in ecimal an octal systems an also in BCD842 coe
18 Example of the aitional tasks (2 points each): 2. Convert the binary number.2 into ecimal. 3. From stuents 22 are female an 22 are male. What is the base of the system use? (All the numbers are in the same system). Control questions. Convert these binary numbers ; ;. into ecimal system. 2. Convert these octal numbers 75; ; 5.4 into ecimal system. 3. Convert these hexaecimal numbers AF; ; B.A into ecimal system. 4. Convert these ecimal numbers 458; 9; into binary, octal an hexaecimal number systems. 5. Perform irect conversion of binary number into octal an hexaecimal number systems. 6. Convert these octal numbers 234; 32; 2.5 into hexaecimal number system. 7. Convert these ecimal numbers 4; 587; 355 into BCD842 coe. 8. Convert binary number into Gray coe. 9. A these binary numbers: an... Subtract these binary numbers: an... Multiply these binary numbers:. an.. 2. Multiply these binary numbers:. an. Literature. Kleitz, W. (28). Digital Electronics: A Practical Approach. McGraw Hill, p
19 2. Lala, Parag, K. (27). Principles of Moern Digital Design. A John Willey & Sons Inc., p Kirvaitis, R. (2). Digital Devices. ETextbook. Available from the author, p Kirvaitis, R. (999). Loginės schemos. Vilnius: Enciklopeija, p (in Lithuanian) 8
20 2. EWB an Multisim. Basic logic gates Objective The goal of this work is: to get acquainte with the igital circuits simulation software; to get the basic unerstaning of the logic gates an their conversion; to be able to fill the truth table an esign a simple circuit implementing the logic function. Theory EWB an Multisim In the laboratory you will use one of the two simulation software packages: Electronics Workbench or Multisim, which is the newer version of Electronics Workbench with wier functionality. Both of them are suitable for simulation of igital circuits an provie all the necessary tools for analysis of igital evices. However the oler Electronics Workbench is simpler for application an its functionality is more than sufficient for laboratory works. Using these packages you can esign a circuit from the basic logic gates an perform its simulation using Logic Analyzer with Wor Generator or Logic Converter tools. Basic logic functions an gates Three main logic functions AND, OR an NOT may be realize with corresponing logic gate. In the case of the logic function, Boolean algebra notation is use, where means low level or false, means high level or true. Because of the manufacturing processes the integrate igital circuits usually are mae from NAND or from 9
21 NOR logic gates. Using NAND gates only or NOR gates only it is possible to realize every logic expression or esign of any igital evice. Table 2. Basic logic gates Name Graphical Logic function Truth table Table 2. Basic logic gates symbol Name AND Graphical A symbol Logic function & F = AB Truth A table B F Table 2. Basic logic gates F AND Table Basic Name A logic logic B gates gates Graphical symbol F Logic = AB A B F & function Truth table Name Graphical symbol F Logic function Truth AND A F = AB A table table B F B & AND A A F F F = = AB AB A A B B F F && B F F OR B B A F = A+ B A B F OR F A F = A+ B A B F OR B A F F = A+ B A B F OR ORB A A F F F = = A+ A+ B B A A B B F F B F F B B XOR XOR A F = A B = XOR A F = A B A A= = F F = A B A B B F F XOR F B F A A F F = = A A B B A A B B F F B = = B F F B B NAND NAND NAND A A & A B F & F = F AB A B F NAND = AB A A F F & F = AB A B F & F = AB A B F B B F F B B NOR A F = A+ B A B F NOR NOR NOR A F F = A+ B A A A B F F B F F = = A+ A+ B A B F B F F B B B XNOR A = F = A B A B F XNOR XNOR F A A A B= = F = AF = AB B A B F = F = A B A B F F F F B B B 2 NOT A F Inverter F = A A F NOT A A F F
22 XNOR A B = F F = A B A B F NOT Inverter A F F = A A F Table 2. represents all types of the basic logic gates together with their European graphical representation, expressions of logic functions they realize, an truth tables of these logic functions. Methoology In the Electronics Workbench you can click on an element or tool an rag it onto workspace. The properties of an element or tool coul be change by oubleclicking the element or tool. Short help coul be receive by clicking the element an pressing F. Elements an tools coul be interconnecte by simply clicking one of the pins of one element or tool an ragging the wire to the other pin of element or tool. For accurate connection the use of zoom function is recommene (5 2 %). Disconnection of wires is possible by ragging the en of the wire from the noe or pin. Wires, elements or tools can be elete by the selection of the wire, element or tool an pressing Del button on the keyboar. Inicators are accessible by clicking Inicators icon on the toolbar (Fig. 2. a). Inicators are use to isplay information. The most common inicators use uring the laboratory works are voltmeters, ammeters, re probes an seven segment isplays that ecoe binary to hexaecimal. 2
23 Tools for analysis of circuits are accessible from toolbar Instruments (Fig. 2. b). The most common tools use are oscilloscope, logic converter, wor generator an logic analyzer. Logic gates are accessible from Logic gates toolbar (Fig. 2. c). Useful elements as power supplies an switches are accessible from Sources an Basic toolbars. This is not the full list of toolbars available in Electronics Workbench environment. There exists toolbars eicate to specific items as ioes, transistors, analogue integrate circuits, igital integrate circuits, mixe integrate circuits, flipflops an other miscellaneous items. a) b) c) Fig. 2. Toolbars of Electronics Workbench 5 The use of wor generator, logic analyzer an logic converter tools requires some explanation. By ouble clicking the wor generator tool on the workspace, the winow with tool properties will open (Fig. 2.2). Wor gene 22
24 rator is a tool for generating various combinations of igital signals. In the left column of wor generator user has a possibility to write coe in hexaecimal form an by clicking Step button each line of hexaecimal coe (one wor) will be ecoe into the binary an supplie via the outputs row of wor generator. Sixteen outputs for sixteen bits are place at the bottom of the wor generator an in Electronics Workbench version 5, the least significant bit generate is from the right sie, so usually the connection of the circuit starts from the right. It is possible to automatically fill the wor generator with a sequence of numbers by pressing Pattern button an then choosing one from the list. The most common pattern is Up counter. Cycle button will be generating sequence of wors continuously, after the last wor in the sequence the generation will start from the beginning. Burst button will generate all the wors in the sequence once. To pause an restart the stream of wors at a specifie wor is possible by clicking the Breakpoint button. Fig. 2.2 Wor generator tool 23
25 Fig. 2.3 Logic analyzer tool Logic analyzer (Fig. 2.3) is often use together with wor generator an is use to isplay changes of logic levels on time axis. The only important property of the logic analyzer is the Clocks per ivision variable, by increasing this number you can compress time axis an make the plot more reaable. Logic analyzer has a column of 6 inputs on the left sie. Input signal is being plot in the logic analyzer winow at the row relate to the input. By changing the color of the wire (property accessible through oubleclicking), the color of the plot in the logic analyzer will also change. Logic converter (Fig. 2.4) is a separate powerful tool an it shoul not be use together with the wor generator, as they both use ifferent approaches when ealing with time. Simulation may lea to erroneous results when both tools are use together on the same workspace. If the circuit shoul be teste using both tools, then two files shoul be create for each set of tools. Logic converter combines signal generator an intelligent analyzer in one tool. It has eight outputs an one input in the top right corner. There are six buttons on the right sie of logic converter relate to its functions: the first button can generate the truth table from the circuit, the se 24
26 con logic expression from the truth table, the thir simplifie logic expression from the truth table, the fourth truth table from the logic expression, the fifth circuit from the logic expression an the sixth the circuit mae of NAND gates from the logic expression. Logic expression coul be written into the lower input box of logic converter, by enoting the inverte variables with the symbol. Fig. 2.4 Logic converter tool To check the operation of the evice esigne, two most popular options exist. The first one is to use wor generator together with logic analyzer. Another option is to use logic converter tool. Example of the circuit mae of one AND, one OR, an one NOR gates (Fig. 2.5) shows interconnection between wor generator an logic analyzer. Outputs of the wor generator are connecte to the inputs of the circuit an the same wires are connecte to logic analyzer. The output of the circuit is also connecte to the logic analyzer. So when the circuit is simulate it is possible to see how the input an output signals are changing. The wor generator is fille with Up counter pattern an the circuit is simulate by clicking Step but 25
27 ton. Combinations of input signals are generate one by one, an each combination together with the output is rawn in the logic analyzer. Fig. 2.5 Interconnection with wor generator an logic analyzer It is important to connect wires in the correct orer. If the variable in the truth table was in the rightmost column, then the input of the circuit corresponing to that variable shoul be connecte to the rightmost terminal of the wor generator. The same circuit connecte to logic converter is presente in Fig Fig. 2.6 Interconnection with logic converter 26
28 Often a gate with more than two inputs is require. In this case the number of inputs of logic gate coul be change from the context menu or by stacking elements with the lower number of inputs (Fig. 2.7 a). Noninverting logic gates, such as AND, OR an XOR, coul be stacke irectly, however special care shoul be taken, when stacking gates with inversion, like NAND, NOR an XNOR. These gates outputs shoul be inverte except the last stage. Inverters coul be mae from NAND or NOR logic gates by connecting the same signal to both their inputs. a) b) Fig. 2.7 a) 5AND from 2AND logic gates b) 5AND logic gate Conversion from one type of logic gate to other type coul be one with the help of De Morgan theorem: X + Y = X Y, X Y = X + Y. The theorem shows that inversion of inputs is neee to convert the gate type. With the help of 3 inverters an AND gate or 2 inverters an NAND gate it is possible to make OR gate (Fig. 2.8 a). In the same way from 3 inverters an OR gate or 2 inverters an NOR gate it is possible to make AND gate (Fig. 2.8 b). 27
29 a) A B A B & F = AB = A+ B b) A B A B F = A+ B = AB Fig. 2.8 Logic gate type conversion a) NAND to OR b) NOR to AND Tasks During the laboratory work you will receive ifferent tasks from the tutor. Example of the obligatory task (for 6 points out of possible):. Design 6 input OR gate from the 3 input NAND gates. Show the operation of the circuit in two ifferent ways (with wor generator an logic analyzer an with logic converter). Example of the aitional tasks (2 points each): 2. Design two circuits performing functions F an F 2 an with the help of the wor generator an logic analyzer show if the functions are equal: a. F ( b. F 2 ( 3. Fill in the truth table of the function F( X, Y, Z) = XYZ + XY + Z an show it to the tutor. Next esign the circuit an check if the truth table is the same. 28
30 Control questions. What oes the truth table show? 2. Draw an fill in the truth tables for 3AND, 3NAND, 3OR an 3NOR logic gates. 3. Using 3NOR logic gates only esign the circuit that performs 2AND logic function. 4. From 2NAND logic gates only esign the circuit that performs 3OR logic function. 5. Draw the circuit realizing logic function: F ( A, B, C ) = AB + CD using NOR logic gates only. 6. Draw the circuit realizing logic function: F ( A, B, C ) = ABC + C an fill in its truth table. 7. Simulate the circuit from the 5th question an check its truth table with logic converter. 8. Simulate the circuit from the 5th question an check its truth table with wor generator an logic analyzer. Literature. Kleitz, W. (28). Digital Electronics: A Practical Approach. McGraw Hill, p. 6 93, Lala, Parag, K. (27). Principles of Moern Digital Design. A John Willey & Sons Inc., p Kirvaitis, R. (2). Digital Devices. ETextbook. Available from the author, p Kirvaitis, R. (999). Loginės schemos. Vilnius: Enciklopeija, p (in Lithuanian) 29
31 3. MINIMIZATION OF LOGIC FUNCTIONS Objective The goal of this work is to get acquainte with logic functions minimization technique an implementation of the minimize functions via the basic logic gates. Theory Minimization Minimization is require to avoi the use of reunant elements, to ecrease the cost an to increase the reliability of the evice. Logic functions coul be minimize via two methos. The first one uses Boolean s algebra theorems an axioms an the secon metho uses Karnaugh maps. The Karnaugh map is a graphical way of minimizing a Boolean expression base on the rule of complementation. Minimization via Karnaugh maps is preferable in the case of small number of variables as it is quite straightforwar. Writing own of logic functions in stanar forms A minterm is the prouct of N istinct literals where each literal occurs exactly once. A maxterm is the sum of N istinct literals where each literal occurs exactly once. Any logic function coul be expresse by its truth table. Each row of the truth table coul be expresse via minterm or maxterm. The function coul be expresse in the form of the sum of proucts by writing out the minterms where the function is equal to. For example, XOR gate s 3
32 logic function expresse via minterms m in the form of the sum of proucts is: F( A, B) = m(,2) (3.) here the numbers are pointing to rows of the truth table (starting from zero) in which the values of the function are equal to. The same function coul also be expresse in a prouct of sums form by writing out maxterms M corresponing to rows where the value of the function is equal to : F( A, B) = M (,3) (3.2) here the numbers are pointing to the rows of the truth table where the outputs are. The next example is a more complex expression: ( ) F( A, B, C) = m,2,3,6,7 (3.3) The truth table of this expression together with all minterms an maxterms is presente in Table 3.. The variables in the minterm are written as inverte if they are equal to in the corresponing row of the truth table. The variables in the maxterm are written as inverte if they are equal to in the corresponing row of the truth table. 3
33 Table 3. Truth table of function F(A,B,C) A B C F minterms maxterms A B C A+ B+C A B C A+ B+C A B C A+ B+C A B C A+ B+C A B C A+ B+C A B C A+ B+C A B C A+ B+C A B C A+ B+C Logic function expresse in a isjunctive normal form as the sum of proucts coul be written irectly from the truth table by writing out the minterms where the function is equal to in the expane or short form: F = ABC + ABC + ABC + ABC + ABC = Σm(,2,3,6,7) (3.4) Often the function may have the outputs that in some cases are not important, for example, when certain combinations of the input signals are not applicable. In this case all unimportant outputs are enote by letter (on t care output) or x in the truth table. The Karnaugh map The Karnaugh map is another form of the truth table. The size of the Karnaugh map is etermine by the number of variables. Usu32
34 ally the maximum number of var iables in one map is fou r ( 24 = 6 cells). If a larger number of variables is use then aitional Karnaugh maps shoul be create (minimization of functions with more than four variables is not covere here). The Karnaugh map is usually fille with ones in the squares of the map corresponing to minterms of the rows in which the function has value. Coorinates of the Karnaugh map are presente in the Gray coe. During the minimization process it is necessary to follow these rules:. Draw the rectangular contours that inclue 2n ones in the neighbour squares of the map, here n =,, 2,3.... Opposite sies of the Karnaugh map coul be joine to form a contour. The corners also coul be joine to form a contour. 2. Size of the contour shoul be as big as possible. Cells with on t care values () shoul be also inclue into the contour if they can lea to a bigger contour. 3. The number of contours shoul be as low as possible an inclue all ones in the Karnaugh map. It is not necessary to inclue all. 4. Minimize expression of the function is written as a sum of proucts corresponing to each contour. Only those variables shoul be written into the prouct that are repeate in all squares of the contour in the same irect or inverte form. If the value of logic variable is in all squares of the contour it will be written into the prouct in irect form, if it is, it will be written in inverte form. Methoology As an example let s analyze the function presente in formula 3.3. This expression inclues three variables, so the fille in the Karnaugh map (Fig. 3.) will be mae of 23 = 8 squares. 33
35 BC A F ( A, B, C ) c2 c2 c Fig. 3. Karnaugh map of F(A,B,C) Every of logic function is written into a relate square, corresponing to minterm with number is written into square, the 2n is written into square an so on. Now, accoring to the rules, the square contours shoul be rawn to inclue all s. In this case minimum number of contours possible is 2, c is mae of four s (,,, ) an c2 is connecting the opposite sies of the Karnaugh map an is mae of two s (, ). Vertical sie of c has ifferent values for input A, an therefore A will not be written into minimize expression. Horizontal sie of c has two inputs B an C. At first input B is checke, an in all squares of the contour its value is (,, an ), so B shoul be written into the expression. Input C has ifferent values in the squares of contour c (,, an ), so it will not be written into the expression. Contour c2 has the same value ( an ) for input A, so A shoul be written into minimize expression; for the horizontal sie input B has ifferent values ( an ), so it will not be written into the expression; input C has the same value ( an ), so C shoul be written into the expression. The final minimize expression will be: F ( A, B, C ) = c + c 2 = B + AC (3.5) A ifferent example mae of function with 4 logic variables: F (W, X, Y, Z ) = m (2,3,6,7,8,9,2,3) 34 (3.6)
36 The Karnaugh map fille with minterms is presente in Fig. 3.2: YZ WX F (W, X, Y, Z ) c c2 Fig. 3.2 Karnaugh map of F(W,X,Y,Z) Here two contours c an c2 will hol all the s an the minimize expression will be: F (W, X, Y, Z ) = c + c 2 = WY + W Y (3.7) A more complex example of the Karnaugh map mae of ones an 2 on t care outputs () is presente in Fig CD c AB F ( A, B, C, D) c2 c3 Fig. 3.3 Karnaugh map of F(A,B,C,D) 35 c
37 To minimize this function four contours are mae. Only one on t care output () was inclue into contour c accoring to minimization rule 2. The final minimize expression in the form of the sum of proucts is: F (W, X, Y, Z ) = c + c 2 + c3 = AD + BD + AB (3.8) Tasks During the laboratory work you will receive ifferent tasks from the tutor. Example of the obligatory tasks (for 6 points out of possible):. Minimize logic function an esign the circuit of the minimize function. Check if the truth table is right. F ( A, B, C, D) = m (, 2, 4,5,8,,2,3). (3 points) 2. Minimize logic function an esign the circuit of the minimize function. Check if the truth table is right. F (W, X, Y, Z ) = (W X + WXY + WX Y ) Z. (3 points) Example of the aitional task (4 points): 3. Fill in the truth table of the function F ( A, B, C, D) = A B C D an show it to the tutor. Design a circuit an check if the truth table is the same. Control questions. What o terms minterm an maxterm mean? 2. Write function F ( X, Y, Z ) = m (2,3,6,7 ) in the conjunctive normal form (prouct of sums in expane form). 3. Write function F ( X, Y, Z ) = M (2, 4,5,7 ) in the isjunctive normal form (sum of proucts in expane form). 36
38 = in the isjunctive normal form. 5. How many s shoul be inclue into one contour? 6. How many contours shoul be rawn in one Karnaugh map? 7. Draw the Karnaugh map for this function: 4. Write function F( X, Y ) m( 2,3) ( ) F( X, Y, Z) = m 4,5,7. Minimize the function. 8. Draw the Karnaugh map for this function: F( X, Y, Z) = M (,2,6). Minimize the function. 9. Draw the Karnaugh map for this function: F( A, B, C) = AB + C + B. Minimize the function.. Draw the Karnaugh map for this function: F( A, B, C, D) = ( A + C) D + ACD + ABCD. Minimize the function.. Draw the Karnaugh map for this function: F( X, Y, Z) = ( m( 4,5,7) + x( 6) ). Minimize the function. 2. Draw the Karnaugh map for this function: F( A, B, C, D) = ( m(,4,5,7 ) + x( 2,3,6) ). Minimize the function. 3. Draw the Karnaugh map for this function: F( A, B, C) = A B C. Is it possible to minimize this function? Literature. Kleitz, W. (28). Digital Electronics: A Practical Approach. McGraw Hill, p Lala, Parag, K. (27). Principles of Moern Digital Design. A John Willey & Sons Inc., p Kirvaitis, R. (2). Digital Devices. ETextbook. Available from the author, p Kirvaitis, R. (999). Loginės schemos. Vilnius: Enciklopeija, p (in Lithuanian) 37
39 4. Algebraic MINIMIZATION OF LOGIC FUNCTIONS Objective The goal of this work is to get acquainte with the basic theorems an axioms of Boolean algebra an to learn to apply them for minimization of logic functions. Theory Axioms an theorems of Boolean algebra Axioms of Boolean algebra: X + = X X = X X + Y = Y + X X Y = Y X X + Y Z = ( X + Y ) ( X + Z) X ( Y + Z) = X Y + X Z X + X = X X = The main theorems of Boolean algebra: X = X X + X = X X X = X X + = X = X + X Y = X X ( X + Y ) = X X + ( Y + Z) = ( X + Y ) + Z X ( Y Z) = ( X Y ) Z X + Y + Z +... = X Y Z... X Y Z... = X + Y + Z +... X Y + X Y = X ( X + Y ) ( X + Y ) = X X + X Y = X + Y X ( X + Y ) = X Y X Y + X Z + Y Z = X Y + X Z ( X + Y ) ( X + Z) ( Y + Z) = ( X + Y ) ( X + Z) 38
40 Algebraic minimization Minimizing of expression algebraically involves application of axioms an theorems until the expression coul not be further minimize. One way of algebraic minimization similar to Karnaugh map minimization is repeate application of the rule of complementation X Y + X Y = X, starting with the function in isjunctive normal form by writing out minterms where the function is equal to, an ening up with the minimize expression mae of a set of prouct terms calle prime implicants. Common algebraic minimization rules:. Write a function in a isjunctive normal form. 2. Fin terms which have the same variables an iffer by inversion of one variable only. 3. Combine these terms, removing that variable (application of the rule of complementation). 4. After combining all the terms that coul be combine a new expression coul be written own. 5. Steps 2 4 are repeate until no more terms coul be combine. By following the minimization rules it is possible to minimize the function to a form where no further minimization is possible. Also these minimization steps coul be use for expressions with more variables (6 or more), when the simplest application of the Karnaugh map is not reasonable. When it is not clear how to write the initial expression in isjunctive normal form (not clear which axioms an theorems to apply), the truth table of the function coul be fille an from the truth table the expression in isjunctive normal form coul be written. 39
41 Methoology As an example the logic function F (W, X, Y, Z ) = m (2,3,6,7,8,9,2,3) will be algebraically minimize. The initial expression of the function in the isjunctive normal form (sum of proucts in expane form by writing out the minterms where the function is equal to ) is: F (W, X, Y, Z ) = m (2,3,6,7,8,9,2,3) = = W XY Z + W XYZ + W XY Z + W XYZ + (4.) +W X Y Z + W X YZ + WX Y Z + WX YZ The first an the secon terms iffer by one inverte variable Z only, so they coul be combine by removing the variable Z: W X Y Z + W X YZ = W XY Z + W XY Z = W X Y, a similar situation is with another 3 pairs of terms. So after the first pass the expression will be F = W X Y + W XY + W X Y + WX Y. Here again the first two terms iffer by the inverte variable X, an other two iffer by the inverte variable X. So after the secon pass the new expression is F = WY + W Y. This expression has no terms which coul be combine so it is assume that this is the final minimize expression of the original function. Tasks During the laboratory work you will receive ifferent tasks from the tutor. Example of the obligatory tasks (for 6 points out of possible):. Minimize the function using algebraic minimization rules: F ( A, B, C, D) = m (,3, 4,6,9,,2,4 ). Simulate the minimize function an check if the truth table is the same. Show the results to the tutor. (4 points) 4
42 2. Minimize this function by applying Boolean algebra axioms an theorems: F = D(( A + A) B + AB) + BD. (2 points) Example of the aitional task (4 points): 3. Perform the algebraic minimization of this function: F( A, B, C, D, E) = M (, 2,5,7,8,,3,5,6,8, 2, 23, 24, 26, 29) Control questions. What are the common minimization rules for Boolean algebraic minimization? 2. State the rule of complementation. 3. Write this function in the expane isjunctive normal form: F( A, B, C) = m(,3,4,6 ). 4. Write this function in the expane isjunctive normal form: F( A, B, C) = M (,,2,3). 5. Minimize the function: F( A, B, C, D) = AC D + ACD + AC. 6. Minimize the function: F( X, Y, Z) = m( 4,5,7). 7. Minimize the function: F( A, B, C) = m(,,2,3). 8. Minimize the function: F( A, B, C, D) = M (,,2). 9. Minimize the function: F( A, B, C, D) = M ( 5,7,3,5).. Minimize the function: F( A, B, C) = ( A + BA) B + ABC.. By applying axioms an theorems of Boolean algebra minimize this function: F( X, Y, Z) = ( X + Y )( Y + Z). 2. By applying axioms an theorems of Boolean algebra minimize this function: F( X, Y, Z) = X + XY + XZ. 3. By applying axioms an theorems of Boolean algebra minimize this function: F( X, Y, Z) = X ( Y + Z) + X. 4
43 Literature. Kleitz, W. (28). Digital Electronics: A Practical Approach. McGraw Hill, p Lala, Parag, K. (27). Principles of Moern Digital Design. A John Willey & Sons Inc., p Kirvaitis, R. (2). Digital Devices. ETextbook. Available from author, p Kirvaitis, R. (999). Loginės schemos. Vilnius: Enciklopeija, p (in Lithuanian). 42
44 5. bjt switch. investigation OF RTL an DTL GATES Objective The goal of this work is to get acquainte with the bipolar junction transistor switch an investigate the gates of Resistor Transistor Logic an Dioe Transistor Logic. Theory BJT switch BJT switch is mae of bipolar junction transistor (Fig. 5.) an loaing resistor. It operates as an inverter. Fig. 5. Investigation circuit of BJT switch 43
45 BJT is controlle by the base current. When the saturating current flows through the base of the transistor (logic one supplie), transistor is saturate an the output is connecte to the groun through the collectoremitter circuit (logic zero). When the current is not flowing through the base (logic zero applie), transistor is close an its resistance is very high, so the power supply voltage (logic one) is present at the output. RTL Resistor Transistor Logic (RTL) is a simple circuit mae of resistors connecte to BJT switch usually implementing NOR logic function. Input circuit of RTL NOR gate is shown in Fig Fig. 5.2 Input circuit of RTL gate 44
46 DTL Dioe Transistor Logic (DTL) is a circuit similar to RTL, but instea of resistors ioes are use. This circuit is suitable for NOR gate implementation. Input circuit of DTL NOR gate is shown in Fig Methoology For moeling of BJT switch the virtual npn transistor is necessary. Voltmeters are use to etermine the logic level at the input an output. Interconnection scheme is presente in Fig. 5.. When the switch is turne off (base of transistor is shorte to the groun) no current flows through the close baseemitter junction. Transistor is close an the resistance of the close transistor is very high. So there is almost no current flow through the transistor. In this case almost all power supply voltage rops on the transistor an logic value in output is high. When the switch is turne on, the current through the baseemitter junction will saturate the transistor an voltage rop on the saturate transistor will be low (..2 V). Fig. 5.3 Input circuit of DTL gate 45
47 Calculation of voltages in input circuit of RTL gate is base on Ohm s law. For each possible combination of voltages at inputs the output voltage shoul be calculate an written into the truth table. In our case (Fig. 5.2) voltages for logic zero an logic one at inputs are U = V an U = 5 V. With such inputs enote as A, B an C the left part of the truth table can be fille (Table 5.). As an example for the inputs combination as presente in Fig. 5.2, calculation will be as follows. The first input is connecte to 5 V an all other inputs are connecte to the groun V. In our case R is connecte in series with parallel connection of R2, R3 an R4. The total resistance RΣ of parallel connecte resistors shoul be evaluate first. Next the current coul be calculate an then the voltage rop at the output. All the necessary calculations are presente below (5.). This way the calculation shoul be performe for each combination of inputs in the truth table (Table 5.). R = R + R 2 R3 R 4, R 2 R3 R 4 = R = + I= = = kω, R 2 R3 R 4 4 = kω, 3 3 (5.) U U (5 ) 3 5 = = ma, RΣ 4 4 U R 2 R 3 R 4 = I R 2 R3 R 4 = 46 5 =.25 V. 4 3
48 Table 5. Truth table in volts of input circuit of RTL gate A B C F In the case of DTL gate, ioes are use instea of input resistors R, R2 an R3 (Fig. 5.3). With ioes, calculation is much simpler, as the only thing that matters is the voltage rop on ioe U. As the voltage rop is the same for all ioes, assuming they are of the same type, parallel connection of ioes will still give the same forwar voltage rop U (for the silicon ioe U =.7 V ). When all ioes are connecte to the groun the output voltage will be zero, an when at least one input is connecte to the power supply, the output voltage will be: U = U U U = 5.7 = 4.3 V. (Table 5.2) Table 5.2 Truth table in volts of input circuit of DTL gate A B C F
49 Tasks During the laboratory work you will receive ifferent tasks from the tutor. Example of the obligatory tasks (for 6 points out of possible):. Design BJT switch. Connect all the require tools (power supply, voltmeters) an check if the switch is working as an inverter. (2 points) 2. Calculate the output voltages of input circuit of RTL gate for all possible values of voltages in inputs (let U = V an U = 4 V ) an fill in the truth table in volts. The resistances of resistors are: R = R2 = R3 = R4 = kω. Simulate the circuit an compare the measure values with the calculate ones. (2 points) Fig. 5.4 Input circuit of RTL gate 3. Replace resistors R, R2, R3 in Fig. 5.4 with ioes, calculate the output voltages an fill in the truth table in volts. Next simulate the circuit an compare the measure values with the calculate ones. (2 points) 48
50 Example of the aitional task (4 points): 4. The circuit (Fig. 5.5) is mae of RTL gates, each with one transistor. When the input is high the total circuit current consumption from the power supply is 2 ma, when the input is low the total circuit current consumption is 9 ma. Calculate the current consumption of one gate: a. When its input is high. b. When its input is low. Fig. 5.5 Logic gates connecte in series Control questions. Explain the operation of BJT switch. 2. State Ohm s law. 3. What will be the forwar voltage rop on silicon ioe? 4. What will be the forwar voltage rop on two silicon ioes connecte in parallel? 5. What will be the forwar voltage rop on two silicon ioes connecte in series? 6. Explain the calculation proceure of input circuit of RTL gate. 7. Explain the calculation proceure of input circuit of DTL gate. 49
51 Literature. Kleitz, W. (28). Digital Electronics: A Practical Approach. McGraw Hill, p Kirvaitis, R. (2). Digital Devices. ETextbook. Available from author, p Kirvaitis, R. (999). Loginės schemos. Vilnius: Enciklopeija, p (in Lithuanian) 5
52 6. investigation OF Stanar TTL gate Objective The goal of this work is to get acquainte with operation of stanar TTL gate, calculate an measure parameters of the gate. Theory Before analyzing TTL gate it is necessary to analyze voltage rops across saturate bipolar npn transistor (Fig. 6.)..5V _ B + + c +.2V _.7V _ e Fig. 6. Saturate bipolar npn transistor The circuit of stanar TTL gate is presente in Fig. 6.2 (usually it has 2 or more inputs, however here all the inputs are presente as one input a). To unerstan how TTL gate works it is necessary to analyze voltages at key points enote by letters (a,, e, f, g, h, k) an fill the table of voltages at these points. Calculation is starte from the low voltage of.2v supplie at input a. Low emitter voltage an high base voltage will cause transistor VT to saturate. Voltage rop on the saturate transistor s baseemitter junction is.7 V an moving from the emitter to the base will cause voltage rise. So at point voltage will be =.9 V. By moving from the base to the collector voltage rop is.5 V so at point e voltage will be.9.5 =.4 V. Such 5
53 voltage is not enough to open two baseemitter junctions of VT2 an VT4 transistors, so VT2 transistor s baseemitter junction resistance will be very high, much higher than R2 or R3, so almost all power supply voltage will rop on the close transistor VT2 an at point h voltage will be +E an at point g voltage will be almost zero what will cause the transistor VT4 to be close. Because of the high potential at point h, transistor VT3 will be saturate an voltage rop across its baseemitter junction will be.7 V. So at point k voltage will be E.7 V an at point f voltage will be E.7.7 V = E.4 V because of the aitional voltage rop.7 V on ioe VD. The usual power supply voltage for the TTL gate is 5 V, so the high level in TTL output will be 5.4 = 3.6 V. Fig. 6.2 TTL gate 52
54 When the high level 3.6 V is supplie at input a the circuit behaves in a ifferent way. Now input transistor VT is working in the reverse moe an its baseemitter junction is close. That will cause a high potential at point that will open the basecollector junction of VT an the baseemitter junctions of VT2 an VT4. Now voltage at point g will be equal to voltage rop on the saturate baseemitter junction of VT4 that is.7 V. A similar situation is true for point e, here aitional.7 V will be ae on the baseemitter junction of VT2 transistor, so the total voltage at point e will be =.4 V. The saturate basecollector junction of VT working in reverse moe will give an aitional.7 V voltage rop so at point voltage will be = 2. V. As VT2 is open, voltage at point h will be.4.5 =.9 V because of voltage rop of.5 V on the basecollector junction of VT2. The potential at point h coul also be calculate from point g an voltage rop on the saturate VT2: =.9 V. At point f voltage rop on the saturate VT4 will be.2 V. The last point is k, here voltage potential between h an f is ivie between the two close pn junctions: the first baseemitter junction of VT3 an the secon junction of ioe VD: (.9.2)/2 =.35 V per junction. So voltage at point k will be =.55 V. All voltages are presente in Table 6.. Table 6. Voltages in key points of TTL gate Point a U, V.2 U, V 3.6 e f.9.4 E g h k E E
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