How To Understand A Nnd Gate In A Microprocessor (Mosfet) With A Power Control Circuit (M2) And A Nd Gate (Nnd) (Nd) (M1) (Dn) (I
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1 y R. Jacob aker, opyright Wiley-IEEE M3 M4 M2 M1 ircuit used to determine transfer curves (a) Schematic of a NND gate V in V out V out V in M4 M3 M1 M2 + + (b) Schematic of a NOR gate Figure 12.1 NND and NOR gate circuits and logic symbols.
2 y R. Jacob aker, opyright Wiley-IEEE N put Inputs N 1 1 Figure 12.2 Schematic of an n-input NND gate. V in V out Switching point Input voltage, Figure 12.3 VTs of the three-input minimum-size (using 10/1 MOSFETs) NND gate.
3 y R. Jacob aker, opyright Wiley-IEEE N Inputs 2 1 put Figure 12.4 Schematic of an n-input NOR gate. V in V out Switching point Input voltage, V in Figure 12.5 VTs of the three-input minimum-size (using 10/1 MOSFETs) NOR gate.
4 y R. Jacob aker, opyright Wiley-IEEE Ground (a) 3-input NND gate layout (b) 3-input NOR gate layout Figure 12.6 Layouts of NND (a) and NOR (b) gates.
5 y R. Jacob aker, opyright Wiley-IEEE In M1 M2 M3 MN load R p R p R p R p oxp oxp oxp oxp N load Figure 12.7 Parallel connection of MOSFETs and equivalent digital model.
6 y R. Jacob aker, opyright Wiley-IEEE put put load R n load MN inn outn MN In M3 R n outn M2 inn M3 M1 In R n outn inn M2 R n outn inn M1 Figure 12.8 Series connection of MOSFETs and equivalent digital model.
7 y R. Jacob aker, opyright Wiley-IEEE In N load Figure 12.9 n n-input NND gate driving a load capacitance. Input t PHL t PLH Figure Simulating the operation of a 3-input NND gate in 50 nm MOS driving a 50 ff load capacitance.
8 y R. Jacob aker, opyright Wiley-IEEE Drain NMOS R n R p Source Source Drain PMOS Figure Further simplification of digital models not showing input capacitance. t PHL t PLH Figure Switching delays in a 3-input NND gate with only one changing states and driving a 50 ff load capacitance. Long L I1 I2 I3 I4 N NOR Figure NOR configuration used for a large number of inputs.
9 y R. Jacob aker, opyright Wiley-IEEE Z = NND NOR Z = + + (a) (b) Z = + + NOR (c) NND (d) Z = Figure Logic implementation in MOS.
10 y R. Jacob aker, opyright Wiley-IEEE Z = + (a) Z = + Z = ( + ) = + (b) Figure First logic gate of Ex
11 y R. Jacob aker, opyright Wiley-IEEE D Z = ( + D) = + + D D Figure Second logic gate of Ex Figure Exclusive OR gate.
12 y R. Jacob aker, opyright Wiley-IEEE Z = + = Figure MOS OI XOR gate. n n arry-in arry-out Full adder n n+1 S n Sum-out n n n S n n Figure Full adder.
13 y R. Jacob aker, opyright Wiley-IEEE n n n n n n+1 n n n+1 n n n n n n n n+1 n n S n n n+1 n n n n n Figure OI implementation of a full adder.
14 y R. Jacob aker, opyright Wiley-IEEE put put Inputs N logic block N logic block Inputs Figure VSL block diagram. Z = + Z = + Figure VSL logic gate.
15 y R. Jacob aker, opyright Wiley-IEEE (XOR) (XNOR) (a) (XOR) (XNOR) (b) Figure (a) Two-input and (b) three-input XOR/XNOR gates.
16 y R. Jacob aker, opyright Wiley-IEEE put put M2 M1 V ref = /2 + V THN Inputs N logic block N logic block Inputs Figure DSL block diagram. M2 Enable M1 Enable Logic symbol Figure Tri-state buffer.
17 y R. Jacob aker, opyright Wiley-IEEE Enable Enable Logic symbol Figure Tri-state inverting buffer. In Delay t d t d Figure n edge detector circuit.
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