ENGIN 112 Intro to Electrical and Computer Engineering

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1 ENGIN 112 Intro to Electrical and omputer Engineering Lecture 11 NND and XOR Implementations

2 Overview Developing NND circuits from K-maps Two-level implementations onvert from ND/OR to NND (again!) Multi-level NND implementations onvert from a network of ND/ORs Exclusive OR omparison with SOP Parity checking and detecting circuitry Efficient with XOR gates!

3 NND-NND & NOR-NOR Networks DeMorgan s Law: (a + b) = a b (a b) = a + b a + b = (a b ) (a b) = (a + b ) = = = = push bubbles or introduce in pairs or remove pairs.

4 NND-NND Networks Mapping from ND/OR to NND/NND a b c d a) b) c) d)

5 Implementations of Two-level Logic Sum-of-products ND gates to form product terms (minterms) OR gate to form sum Product-of-sums OR gates to form sum terms (maxterms) ND gates to form product

6 Two-level Logic using NND Gates Replace minterm ND gates with NND gates Place compensating inversion at inputs of OR gate

7 Two-level Logic using NND Gates (cont d) OR gate with inverted inputs is a NND gate de Morgan's: ' + ' = ( )' Two-level NND-NND network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed

8 onversion etween Forms onvert from networks of NDs and ORs to networks of NNDs and NORs Introduce appropriate inversions ("bubbles") Each introduced "bubble" must be matched by a corresponding "bubble" onservation of inversions Do not alter logic function Example: ND/OR to NND/NND D Z D NND NND NND Z

9 onversion etween Forms (cont d) Example: verify equivalence of two forms D Z D NND NND NND Z Z = [ ( )' ( D)' ]' = [ (' + ') (' + D') ]' = [ (' + ')' + (' + D')' ] = ( ) + ( D)

10 onversion to NND Gates Start with SOP (Sum of Products) circle 1s in K-maps Find network of OR and ND gates

11 Multi-level Logic x = D F + E F + D F + E F + D F + E F + G Reduced sum-of-products form already simplified 6 x 3-input ND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires) x = ( + + ) (D + E) F + G Factored form not written as two-level S-o-P 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input ND gate 10 wires (7 literals plus 3 internal wires) D E X F G

12 onversion of Multi-level Logic to NND Gates F = ( + D) + ' Level 1 Level 2 Level 3 Level 4 original ND-OR network D F introduction and conservation of bubbles D F redrawn in terms of conventional NND gates D F

13 onversion etween Forms Example (a) D X F D X F (b) Original circuit dd double bubbles at inputs X (c) D X F D X F (d) Distribute bubbles some mismatches Insert inverters to fix mismatches

14 Exclusive-OR and Exclusive-NOR ircuits Exclusive-OR (XOR) produces a HIGH output whenever the two inputs are at opposite levels. ENGIN112 L11: NND and XOR Implementation September 26, 2003

15 Exclusive-NOR ircuits Exclusive-NOR (XNOR) : Exclusive-NOR (XNOR) produces a HIGH output whenever the two inputs are at the same level.

16 Exclusive-NOR ircuits XNOR gate may be used to simplify circuit implementation.

17 XOR Function XOR function can also be implemented with ND/OR gates (also NNDs).

18 XOR Function Even function even number of inputs are 1. Odd function odd number of inputs are 1.

19 Parity Generation and hecking FIGURE 4-25 XOR gates used to implement the parity generator and the parity checker for an even-parity system.

20 Summary Follow rules to convert between ND/OR representation and symbols onversions are based on DeMorgan s Law NOR gate implementations are also possible XORs provide straightforward implementation for some functions Used for parity generation and checking XOR circuits could also be implemented using ND/Ors Next time: Hazards