CMOS Process Variations EEPROM Fabrication Technology. Dr. Lynn Fuller Webpage:
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1 ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING CMOS Process Variations EEPROM Fabrication Technology Dr. Lynn Fuller Webpage: 82 Lomb Memorial Drive Rochester, NY Tel (585) Department Webpage: EEPROM.PPT Page 1
2 OUTLINE Introduction Tunneling Gate Oxide EEPROM Programming Reading Test Specification/Results Fowler-Nordheim Tunneling Process Variation Tunnel Oxide Recipe Test Chip Layout Step-by-Step Process Page 2
3 INTRODUCTION In certain applications, data must be electrically entered and erased from Read Only Memory (ROM). The procedure can involve the entire ROM sections or one memory cell at a time. From the various technologies available, we have chosen the design of a FLOTOX EEPROM (FLOating-gate Tunneling Oxide Electrically Erasable Programmable ROM, Figure 1. This EEPROM cell has double polysilicon gates, with the top polysilicon as the control gate and the lower polysilicon as the floating gate. A thin tunneling oxide is formed above the drain in the FLOTOX Transistor. Page 3
4 TUNNELING GATE OXIDE EEPROM Another form of the FLOTOX Transistor is shown below. The structure is simpler and smaller but is more difficult to manufacture because of the problems associated with diffusion of phosphorous from the gate poly through the tunnel oxide into the transistor channel region. Most modern EEPROM devices use this structure. Source Gate Drain n+ n+ P-well or P substrate Page 4
5 INTRODUCTION The EEPROM is programmed by transferring electrons between the floating-gate and the substrate, through the tunneling oxide, by means of Fowler-Nordheim tunneling. There are two modes of programming the EEPROM: write and erase. First, in the write mode, the floating-gate is charged negatively by electrons that tunnel from the drain to the floating gate. The charging is done by applying a +15V voltage to the control gate and connecting both the drain and source to ground. The negative charge stored on the floating gate has the effect of shifting the threshold voltage towards a more positive value. When the floating gate is charged, the normal +5V applied to the control gate during a read operation will not be sufficient for the transistor to conduct channel current. Only when the floating gate is uncharged, will the transistor be able to conduct with +5V on the control gate. Page 5
6 PROGRAMMING THE EEPROM CELL Word 0V Bit Word 15V Bit Word 15V Bit 15V 15V 0V Ctrl Ctrl Ctrl 15V 0V 0V Precharge Floating Gate with Electrons Write a 0 Remove Electrons From Floating Gate Write a 1 Leave Electrons on Floating Gate Page 6
7 READING THE CELL If the floating gate is charged with electrons the 5 volts on the control line will not be enough to turn that transistor on. Thus the output will be high. Word 5V 5V R Bit Line If the floating gate is uncharged with electrons the 5 volts on the control line will turn that transistor on. Thus the output will be low. Control 5V Read Output Page 7
8 EEPROM Technology TEST SPECIFICATION Specification Can FLOTOX Transistor be programmed Charge the Floating Gate Measure the subthreshold characteristics Discharge the Floating Gate Measure the subthreshold characteristics Can the FLOTOX Transistor hold the charge Charge the Floating Gate Measure the subthreshold characteristics Wait 1hours, 10 hours, 100 hours, 1000hours Measure the subthreshold characteristics Can the FLOTOX Transistor be cycled many times How much time does it take to charge and discharge Page 8
9 FOWLER-NORDHEIM TUNNELING J = C 1 E c2 exp(-eo/ec) C 1 = q 3 m / (8πhφ b m*) = 9.625E-7 A/V 2 Ec = V FG /tox Eo = 8π(2m) 1/2 φ b 3/2 /(3hq) C G C FG V P V FG = Vp C G /(C G + C FG ) Example: let C FG =0.3 pf, C G =0.2 pf, Vp=25 volts, tox = 100 Å, m*=.5m e, φ b = 3.2 where m e =9.11E-31, h=(6.625e-34)/2π, q=1.6e-19 so Eo=2.765E8 V/cm and Ec = 10/100E-8 V/cm J = 9.625E-7 (Ec) 2 exp (-2.765E8/Ec)=94.4 µa/cm 2 Page 9
10 CMOS PROCESS MODIFICATIONS The fabrication of a FLOTOX EEPROM involves a three modifications to the present CMOS process. An additional n+ drain implant is performed before the polysilicon layers are deposited. A thin 100 Å tunneling oxide is grown above the additional n+ implant region. A second polysilicon layer is deposited for the control gate. Page 10
11 TUNNEL OXIDE RECIPE FOR ~120 Å SiO2 Step Gas Flow Temperature Time Boat 0 Load Tube 15 lpm 650 C? Out 1 Push 15 lpm 650 C 15 min In 2 Stabilization 15 lpm 650 C 15 min 3 Ramp Up 15 lpm 650 to 950 C 30 min 4 First Oxide 15 lpm + 5 lpm 950 C 15 min 5 First Anneal 15 lpm 1050 C 30 min 6 Ramp Down 15 lpm 950 C 20 min 7 2nd Oxide 15 lpm + 5 lpm 950 C 10 min 8 2nd Anneal 15 lpm 950 C 30 min 9 Ramp Down 15 lpm 950 to 650 C 60 min 10 Pull 15 lpm 650 C 15 min Out Page 11
12 Entire Test Chip EEPROM Transistor EEPROM plus Select EEPROM Memory Array Variable Programmable Resistor Binary-weighted Variable Programmable Resistor Resistors Capacitors Page 12
13 Drain EEPROM Transistor Basic transistor with two layers poly, tunnel oxide, and 3 connections. Gate Source Page 13
14 Drain EEPROM Transistor + Select Basic transistor with two layers poly, tunnel oxide, and 4 connections. Gate Select Source Page 14
15 EEPROM 5V R R R R Word Line 0 Control/Read Control/Read Control/Read Control/Read Word Line 1 Word Line 2 Word Line 3 Bit Lines B 3 B 2 B 1 B 0 Page 15
16 Memory array of four-byfour EEPROM cells Page 16
17 A variable programmable resistor with equal 1000 ohm resistors in series. Page 17
18 A variable programmable resistor with binary-weighted resistors, 1k, 2k, 4k, 8k k ohms Page 18
19 TEST RESULTS Programmed with 3 seconds of +25 volts on gate Erase with 4 seconds of 25 volts on the Drain Id (Amps) G S D Id + Vgs=Vds - Sub Vt Swing (Amps) Lights On After erase Vt After programming Vgs Page 19
20 REFERENCES 1. Flash EE PROM Device, Keith Zawadski, Senior Desing Project, May EEPROMs, Edward Storbeck, Visiting Scholar from South Africa, Device Electronics for Integrated Circuits, Richard S. Muller, Theodore I. Kamins, John Wiley and Sons, Inc. 4. Nonvolatile Semiconductor Memory Technology, Edited by William D. Brown and Joe E. Brewer, IEEE Press Page 20
21 HOMEWORK - EEPROM 1.0 Calculate the current that would flow through a 10 by 10 µm tunnel oxide of 100 Å, at a control gate voltage of 10, 15 and 20 Volts, assume CFG=0.3pF and CG=0.2 pf 2.0 How long would it take to charge the floating gate to 2.5 volts. Assume the floating gate is 0.3 pf floating gate and the currents are as found in problem Describe the exact procedure that you would use to test the FLOTOX transistor. Page 21
22 HOMEWORK - EEPROM 1.0 Calculate the current that would flow through a 10 by 10 µm tunnel oxide of 100 Å, at a control gate voltage of 10, 15 and 20 Volts, assume CFG=0.3pF and CG=0.2 pf 2.0 How long would it take to charge the floating gate to 2.5 volts. Assume the floating gate is 0.3 pf floating gate and the currents are as found in problem Describe the exact procedure that you would use to test the FLOTOX transistor. Page 22
23 NOR AND NAND FLASH Flash memory is a non-volatile computer storage that can be electrically erased and reprogrammed. It is a technology that is primarily used in memory cards and USB flash drives for general storage and transfer of data between computers and other digital products. It is a specific type of EEPROM (Electrically Erasable Programmable Read-Only Memory) that is erased and programmed in large blocks; in early flash the entire chip had to be erased at once. Flash memory costs far less than byte-programmable EEPROM and therefore has become the dominant technology wherever a significant amount of non-volatile, solid state storage is needed. Example applications include PDAs (personal digital assistants), laptop computers, digital audio players, digital cameras and mobile phones. It has also gained popularity in console video game hardware, where it is often used instead of EEPROMs or battery-powered static RAM (SRAM) for game save data. Since flash memory is non-volatile, no power is needed to maintain the information stored in the chip. In addition, flash memory offers fast read access times (although not as fast as volatile DRAM memory used for main memory in PCs) and better kinetic shock resistance than hard disks. These characteristics explain the popularity of flash memory in portable devices. Another feature of flash memory is that when packaged in a "memory card," it is extremely durable, being able to withstand intense pressure, extremes of temperature, and even immersion in water. Although technically a type of EEPROM, the term "EEPROM" is generally used to refer specifically to non-flash EEPROM which is erasable in small blocks, typically bytes. Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over old-style EEPROM when writing large amounts of data. Wikipedia contributors. "Flash memory." Wikipedia, The Free Encyclopedia. Wikipedia, The Free Encyclopedia, 3 Feb Web. 11 Feb Page 23
24 NOR AND NAND FLASH NOR and NAND flash differ in two important ways: the connections of the individual memory cells are different the interface provided for reading and writing the memory is different (NOR allows randomaccess for reading, NAND allows only page access) These two are linked by the design choices made in the development of NAND flash. A goal of NAND flash development was to reduce the chip area required to implement a given capacity of flash memory, and thereby to reduce cost per bit and increase maximum chip capacity so that flash memory could compete with magnetic storage devices like hard disks. NOR and NAND flash get their names from the structure of the interconnections between memory cells. In NOR flash, cells are connected in parallel to the bitlines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a NAND gate. The series connections consume less space than parallel ones, reducing the cost of NAND flash. It does not, by itself, prevent NAND cells from being read and programmed individually. When NOR flash was developed, it was envisioned as a more economical and conveniently rewritable ROM than contemporary EPROM, EAROM, and EEPROM memories. Thus random-access reading circuitry was necessary. However, it was expected that NOR flash ROM would be read much more often than written, so the write circuitry included was fairly slow and could only erase in a block-wise fashion. On the other hand, applications that use flash as a replacement for disk drives do not require word-level write address, which would only add to the complexity and cost unnecessarily. Because of the series connection and removal of wordline contacts, a large grid of NAND flash memory cells will occupy perhaps only 60% of the area of equivalent NOR cells (assuming the same CMOS process resolution, e.g. 130nm, 90 nm, 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential-accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random-access of NAND flash memory impossible, but the goal of NAND flash was to replace hard disks, not to replace ROMs. Wikipedia contributors. "Flash memory." Wikipedia, The Free Encyclopedia. Wikipedia, The Free Encyclopedia, 3 Feb Web. 11 Feb Page 24
25 Page 25
26 132GBit NAND FLASH Page 26
27 Page 27
28 RIT EEPROM PROCESS λ = 2.5 Micrometer Design Rules 9 Design Layers 12 Photolithography Layers LOCOS Extended n+ drain n-type Poly Floating and Control Gate 100A Tunneling Oxide over Drain Page 28
29 6000Å n+ Poly FET RIT P-WELL CMOS PROCESS CROSSECTION 3000Å CVD Ox PMOSFET 0.75 µm Aluminum NINE PHOTO LEVELS p-w ell 10,000Å Field Ox p+ p+ p+ n+ n+ n+ n+ D/S 4e15, 100KeV P31 thru gate Oxide 4e12, 50 kev, B11, 1123 C, 20 hr field Vt adj 8e13 B11, 100KeV Bare p+ D/S 2e15, 150 KeV BF2 thru gate oxide Vt adj nmos 1.2e12, 60 KeV B11, 1000Å Kooi Vt adj pmos 1e11, 60 kev Blanket, 1000Å Kooi LVL 1 - WELL LVL 2 - ACTIVE LVL 6 - P+ D/S LVL 7 - N+ D/S n-type substrate 10 ohm-cm (100) SIX LAYOUT LEVELS +V POLY ACTIVE P SELECT LVL 3 - FIELD VT LVL 8 - CC LVL 4 - VT LVL 9 - METAL WELL CC METAL LVL 5 - POLY Vin Vout
30 CROSS-SECTION EEPROM p+ n+ n+ n+ n+ 4e12, 50 kev, B11, 1123 C, 20 hr p+ D/S 4e15, 120 KeV BF2 into bare silicon n+ D/S 4e15, 100KeV P31 thru gate Oxide Vt adj blanket and nmos e, 60 KeV B11, 1000Å Kooi field Vt adj 8e13 B11, 100KeV Bare n+ D/S 4e15, 100KeV P31 thru gate Oxide Three extra layers: Drain Extension Tunnel Oxide Floating Poly Page 30
31 IDENTIFY AND FOUR POINT PROBE F D1 I V N-TYPE WAFER, 10 OHM CM Rho = V / I * Pi / ln 2 ohm-cm Page 31
32 EEPROM EEPROM Technology ALIGNMENT OXIDE Well Oxide, 5000 Å Push, 12 in/min at 900 C, 5 lmp N 2 Ramp to 1100 C, 5 lpm Dry O 2 Soak for 48 min, 5 lpm wet O 2 Ramp to 1000 C, 5 lpm N 2 Pull, 12 in/min, 5 lpm N 2 n-type substrate, 5-15 ohm-cm, (100) Page 32
33 LEVEL 1 PHOTO - WELL EEPROM Photoresist well Oxide, 5000 Å n-type substrate, 5-15 ohm-cm, (100) Page 33
34 EEPROM EEPROM Technology OXIDE ETCH Page 34
35 EEPROM EEPROM Technology WELL IMPLANT implant, 4e12, 50 KeV, B11 Page 35
36 EEPROM EEPROM Technology STRIP RESIST implant, 4e12, 50 KeV, B11 Page 36
37 EEPROM EEPROM Technology POST WELL DRIVE 5800 Å Oxide (increase by 800 Å) 2850 Å Oxide, 4 hours Dry O2, 4e12, 50 KeV, B11, 1125 C, 20 hrs xj = 4.5 µm Rhos = 3000 ohms Page 37
38 EEPROM EEPROM Technology OXIDE ETCH 925 Å alignment step height Page 38
39 EEPROM EEPROM Technology GROW PAD OXIDE Well Oxide, 500 Å Push, 12 in/min at 900 C, N 2 Ramp to 1100, Dry O 2 Soak for 8 min, Dry O 2 Ramp down to 1000 C, N 2 Pull, 12 in/mi, N 2 Page 39
40 LPCVD SILICON NITRIDE EEPROM 500 Å Oxide 1500 Å Nitride, 810 C, 20 min Page 40
41 LEVEL 2 PHOTO - ACTIVE EEPROM 10,000 Å photoresist Page 41
42 EEPROM EEPROM Technology NITRIDE PLASMA ETCH SF6, 300 mtorr, 30 sccm 50 W, 60 seconds Page 42
43 EEPROM EEPROM Technology STRIP RESIST Page 43
44 LEVEL 3 PHOTO - CHANNEL STOP / FIELD VT ADJ EEPROM Page 44
45 11 B EEPROM Technology IMPLANT CHANNEL STOPS EEPROM 11 B, 100 kev, 8E13 Page 45
46 EEPROM EEPROM Technology STRIP RESIST Page 46
47 EEPROM EEPROM Technology OXIDE ETCH 1 min in BOE HF Page 47
48 EEPROM EEPROM Technology GROW FIELD OXIDE Push in 900C, ramp to 1100C in O2, soak 210 min wet O2, ramp down to 1000C and pull. Page 48
49 EEPROM EEPROM Technology NITRIDE ETCH Page 49
50 EEPROM EEPROM Technology OXIDE ETCH Page 50
51 EEPROM EEPROM Technology GROW KOOI OXIDE Page 51
52 IMPLANT BLANKET Vt ADJ EEPROM 11B, 60 kev, 0e12 Page 52
53 LEVEL 4 PHOTO - Vt ADJ EEPROM Page 53
54 IMPLANT - Vt ADJ EEPROM 11B, 60 kev, 1.2e12 Page 54
55 EEPROM EEPROM Technology STRIP RESIST Page 55
56 LEVEL 5 PHOTO - N + DRAIN EEPROM Page 56
57 EEPROM EEPROM Technology IMPLANT N + DRAIN 31 P, 100 kev, 4e15 Page 57
58 EEPROM EEPROM Technology STRIP RESIST n+ Page 58
59 EEPROM EEPROM Technology OXIDE ETCH n+ Page 59
60 EEPROM EEPROM Technology GROW GATE OXIDE n+ TCA tube clean during warm up Push at 900 C, 12 in/min, N2 Ramp up to 1100 C, dry O2 Soak 1100 C, dry O2, 8 min Pull at 900 C, 12 in/min, N2 Xox desired = 500 Å Page 60
61 EEPROM EEPROM Technology PHOTO 6 - TUNNEL OXIDE n+ Page 61
62 EEPROM EEPROM Technology ET06 n+ Page 62
63 EEPROM EEPROM Technology ET07 n+ Page 63
64 EEPROM EEPROM Technology OX06-TUNOX n+ Page 64
65 EEPROM EEPROM Technology POLYSILICON DEPOSITION n+ LPCVD Polysilicon 0.6 micrometers 610 C, 60 min Page 65
66 EEPROM EEPROM Technology POLYSILICON DOPING n+ Spin-on n-type Dopant 1000 C, 20 min, N 2 Page 66
67 ET06 EEPROM EEPROM Technology n+ Spin-on n-type Dopant 1000 C, 20 min, N 2 Page 67
68 LEVEL 5 PHOTO - POLYSILICON EEPROM n+ Page 68
69 PLASMA ETCH POLYSILICON EEPROM n+ SF6 + O2, 30 sccm + 3 sccm, 75 mt, 75 watts Page 69
70 ET07 EEPROM EEPROM Technology n+ SF6 + O2, 30 sccm + 3 sccm, 75 mt, 75 watts Page 70
71 EEPROM EEPROM Technology ET06 n+ Page 71
72 EEPROM EEPROM Technology CL01 & OX06 n+ Page 72
73 EEPROM EEPROM Technology CV01 n+ Page 73
74 EEPROM EEPROM Technology DI04 n+ Page 74
75 EEPROM EEPROM Technology ET06 n+ Page 75
76 PHOTO 8 - SECOND GATE EEPROM n+ Page 76
77 EEPROM EEPROM Technology ET08 n+ Page 77
78 EEPROM EEPROM Technology ET07 n+ Page 78
79 LEVEL 6 PHOTO - P+ D/S, OXIDE ETCH EEPROM n+ Page 79
80 EEPROM EEPROM Technology ION IMPLANT P+ D/S 11 B, kev, e n+ 4e15, 120 KeV, BF 2 into bare silicon 4e15, 120 KeV, BF 2 into bare silicon Page 80
81 EEPROM EEPROM Technology ET07 p+ n+ 4e15, 120 KeV, BF 2 into bare silicon 4e15, 120 KeV, BF 2 into bare silicon Page 81
82 LEVEL 7 PHOTO - N+ D/S EEPROM p+ n+ 4e15, 120 KeV, BF 2 into bare silicon Page 82
83 ION IMPLANT N+ D/S EEPROM 11B, 60 kev, 1.2e12 p+ n+ 4e15, 100KeV, P31 thru gate Oxide Page 83
84 ET07 EEPROM Technology EEPROM n+ n+ n+ p+ n+ 4e15, 100KeV, P31 thru gate Oxide Page 84
85 ANNEAL, 950 C, 30 MIN, N 2 EEPROM n+ n+ n+ p+ n+ Page 85
86 EEPROM EEPROM Technology CVD (LTO) GLASS DEPOSITION 6000Å LTO CVD Oxide n+ n+ n+ p+ n+ Page 86
87 LEVEL 8 PHOTO - CONTACT CUT EEPROM n+ n+ n+ p+ n+ Etch in BHF 7min Page 87
88 CONTACT CUT ETCH EEPROM n+ n+ n+ p+ n+ Page 88
89 EEPROM EEPROM Technology STRIP RESIST n+ n+ n+ p+ n+ Page 89
90 EEPROM EEPROM Technology METAL DEPOSITION n+ n+ n+ p+ n+ 1µm Aluminum Page 90
91 LEVEL 9 PHOTO - METAL EEPROM n+ n+ n+ p+ n+ 1µm Aluminum Page 91
92 ETCH METAL AND STRIP RESIST EEPROM n+ n+ n+ p+ n+ Page 92
93 EEPROM EEPROM Technology SINTER n+ n+ n+ p+ n+ Page 93
94 EEPROM EEPROM Technology EEPROM 1 µm Aluminum p+ n+ n+ n+ n+ 4e12, 50 kev, B11, 1123 C, 20 hr n+ D/S 4e15, 100KeV P31 thru gate Oxide field Vt adj 8e13 B11, 100KeV Bare p+ D/S 4e15, 120 KeV BF2 into bare silicon Vt adj blanket and nmos e, 60 KeV B11, 1000Å Kooi n+ D/S 4e15, 100KeV P31 thru gate Oxide Page 94
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