Flash Memory Jan Genoe KHLim Universitaire Campus, Gebouw B 3590 Diepenbeek Belgium

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1 Flash Memory Jan Genoe KHLim Universitaire Campus, Gebouw B 3590 Diepenbeek Belgium [1] Geheugen 1

2 Product evolution Jan Genoe: Geheugen 2 Geheugen 2

3 p Verkochte FLASH geheugens 2.0 B illio n s Handheld Computers Pocket Data Storage Device Flash Storage Cards MP3 Players Digital Camcorders Digital Still Cameras Mobile Terminals Jan Genoe: Geheugen 3 Geheugen 3

4 Kostprijs Jan Genoe: Geheugen 4 Geheugen 4

5 Magnetische versus optische opslag Jan Genoe: Geheugen 5 Geheugen 5

6 Transistor VT verschuiving bepaalt het aan of af zijn van de transistor Jan Genoe: Geheugen 6 Geheugen 6

7 Opladen van de bitlijnen Precharge fase (φ = 0): De uitgang is opgeladen tot 1 (V DD ) φ Precharge Evaluatie Evaluatie fase (φ = 1): De ingangen kunnen de uitgang naar 0 trekken. Dit kan maar één keer. Gedurende de evaluatie fase is er geen overgang van 1 naar 0 meer toegelaten op de ingang inputs φ PDN CL Jan Genoe: Geheugen 7 Geheugen 7

8 Flash-gerichte NVM Markt $ Millions $45,000 $40,000 $35,000 $30,000 $25,000 $20,000 $15,000 $10,000 $5,000 $0 Source: Webfeet Research, Inc. NOR and NAND Revenue Forecast NOR NAND Flash Groeisnelheid: ~20% NOR: ~11% NAND: ~30% Code storage Data storage Jan Genoe: Geheugen 8 Geheugen 8

9 Aantal schrijf-lees cycli Jan Genoe: Geheugen 9 Geheugen 9

10 NOR Jan Genoe: Geheugen 10 Geheugen 10

11 NAND Jan Genoe: Geheugen 11 Geheugen 11

12 Multiple level cells Jan Genoe: Geheugen 12 Geheugen 12

13 downscaling NOR Scaling issue: tunnel oxide thickness Feature size F (nm) NAND Scaling issue: interpoly dielectric thickness Year Jan Genoe: Geheugen 13 Geheugen 13

14 Gate lek Jan Genoe: Geheugen 14 Geheugen 14

15 Non-Volatile Memory Products Code Read Writes Density Reliability Fast Random Medium Small Medium No bad bits Mobile Consumer Electronics Networking Data Read Writes Density Reliability Fast Sequential Fast Large Bad bits allowed Cards MP3 USB Drives Jan Genoe: Geheugen 15 Geheugen 15

16 Non-Volatile Memory History MRAM, Phase Change, Polymer 2000 s?? Ferro-electric electric 1988 Nitride Storage 2002 MLC NOR Flash 1995 EPROM 1971 NAND Flash 1985 NOR Flash 1988 AND, DiNOR Flash 1990 s MLC NAND Flash 1996 Bipolar ROMS/PROMS Late 60 s EEPROM MLC = Multi-Level Cell Jan Genoe: Geheugen 16 Geheugen 16

17 Non-Volatile Memory Terminology Program: Storing charge on a floating gate Erase: Removing charge from the floating gate Data Retention: The longest time for the NVM to keep the stored information Endurance: The number of Program/Erase Cycles the memory can withstand Disturbs: A mechanism that corrupts the stored data in the memory cell Memory Cell: Device that contains the memory storage element Memory Array: Arrangement of Memory cells Jan Genoe: Geheugen 17 Geheugen 17

18 Technology Comparison Production Research NOR Flash NAND Flash Nitride Phase Change MRAM FeRam Cost Cell Size 10λ 2 6λ 2 6λ λ λ λ 2 Read Characteristics Cell Read Latency Cell Read Bandwidth (Array Attribute) 10 s ns 100 s cells 10 s us 1000 s cells 10 s ns 100 s cells 10 s ns 10 s-100 s cells 10 s ns 100 s cells 10 s ns 100 s cells Write Characteristics Cell Write Time Cell Write Bandwidth (Array Attribute) 100 s ns 10 s cells 100 s us 1000 s cells 100 s ns 10 s cells 10 s ns 10 s cells 10 s ns 10 s cells 10 s ns 10 s cells λ represents minimum feature size for any technology Feature size=process lithography capability Example: 0.12u lithography, 10λ 2 cell size yields a cell area of 0.144u 2 Jan Genoe: Geheugen 18 Geheugen 18

19 Nor vs. Nand Specification READ PROGRAM ERASE Random Throughput Random Throughput Throughput Nor 98 ns 266 MB/s (x16) 500 us (512 bytes) 1 MB/s MB/s (1 s per block) Nand 25 us (1 st byte) 37 MB/s (x16) 300 us (2112 bytes) 5 MB/s 64 MB/s (2 ms per block) Multi-Level Cell Significant Cost Reduction, but not easy Offers 2x density at approximately same die size Block Size = 128KB Jan Genoe: Geheugen 19 Geheugen 19

20 Flash Memory Device NAND & NOR D Tunnel Oxide POLY2 CONTROL GATE Inter Poly Dielectric ONO FG POLY1 FLOATING GATE CG N+ SOURCE N+ DRAIN P-WELL Deep N-Well P-Substrate S Stacked Gate NMOS Transistor Poly1 Floating Gate for charge storage Poly2 Control Gate for accessing the transistor Tunnel-oxide for Gate oxide Oxide-Nitride-Oxide (ONO) for the inter Poly Jan Genoe: Geheugen 20 Geheugen 20

21 NAND vs. NOR Cross-sections bitline 0 N O R String of 16 cells Bitline bitline N A N D sel Sourceline sel String of 16 cells Bitline sel 0 Select Transistors 2 sel sel sel Two of the Most Popular Flash Memory Types Both have Dual Gate NMOS with charge storage in Poly1 floating gate Lack of contacts in NAND cell makes it inherently smaller in size Jan Genoe: Geheugen 21 Geheugen 21

22 Flash Memory Device Basic Operation D D Stored Electrons FG C DRN CG CG C CG FG Erased 1 Programmed 0 C SRC C SUB Ids 1 0 S S Programming = Electrons Stored on the FG = High Vt Erasing = Remove electrons from the FG = Low Vt Jan Genoe: Geheugen 22 Vcg Geheugen 22

23 Nand Flash Programming FN Tunneling 20V Ec 0V 0V Ev N + N + Channel Floating Gate 0 -Program P-well Ec Ev Y. S. Yim, et al. IEDM 2003 Tunnel Programming from channel by biasing the Top Gate positive with respect to the ground Program Time ~300us Program current ~ Displacement plus Tunneling current. Low current allows large Jan Genoe: Geheugen 23 Geheugen 23

24 NOR Flash Programming Channel Hot Electron 0V 10V N N + + N N + + P-Well Program 0V P-well 5V Ec Ev Substrate Lucky Electron Channel Ec Ev Floating Gate Vt (V) Vgate = 10V 1.E-07 1.E-06 1.E-05 1.E-04 Time (s) Vd=3.0V Vd=3.25V Vd=3.5V Vd=3.75V Vd=4.0V Channel Hot Electron Programming - Gate voltage inverts channel; drain voltage accelerates electrons towards drain; gate voltage pulls them to the floating gate In Lucky Electron Model, electron crosses channel without collision, gaining > 3.2eV, hits Si atom, bounces over barrier Jan Genoe: Geheugen 24 Geheugen 24

25 Floating Gate Electrons vs. Lithography 30nm Lithography Jan Genoe: Geheugen 25 Geheugen 25

26 Single-Level Cell (SLC) vs. Multi-Level Cell (MLC) Number of Cells SLC Data = 1 0 Program Erase MLC Take advantage of the threshold voltage difference between the erased and programmed states of the single-levelcell case Two levels = 1 bit/cell Four levels = 2 bits/cell In general: n bits/cell = log 2 (#levels) Need additional reference cells for program / read One read reference cell for 1 bit/cell Three read reference cells for 2bits/cell N-1 reference cells for n bits/cell Corresponding reference cells for program Count R1 P1 R2 P2 R3 P3 Jan Genoe: Geheugen 26 Geheugen 26

27 Multi-Level Cell Design Why do MLC? Cost Effectively cuts cell area per bit in half Provides the same cost improvement from an array area perspective as a litho generation Three Key MLC Considerations Precise Charge Placement (Programming) Cell programming must be accurately controlled, which requires a detailed understanding of cell physics, voltage control and timing Precision voltage generation for stable wordline and drain voltage Precise Charge Sensing (Read) MLC read operation is an analog to digital conversion of the charge stored in the cell Device and capacitance matching, Collapsing sources of variation, Precision wordline and drain voltage generation, Low current sensing Stable Charge Storage Jan Genoe: Geheugen 27 Geheugen 27

28 Oppervlak vergelijking Jan Genoe: Geheugen 28 Geheugen 28