DESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET TRANSISTORS

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1 DESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET TRANSISTORS Prof. Dr. João Antonio Martino Professor Titular Departamento de Engenharia de Sistemas Eletrônicos Escola Politécnica da Universidade de São Paulo, Brasil

2 DESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET TRANSISTORS FAPESP Thematic Project 3 Universities: USP, UNICAMP, FEI Group leaders: Prof. Dr. João Antonio Martino (USP) Prof. Dr. Sebastião G. dos Santos Filho (USP) Prof. Dr. Antonio Carlos Seabra (USP) Prof. Dr. José Alexandre Diniz (UNICAMP) Prof. Dr. Marcelo Antonio Pavanello (FEI)

3 Keep increase of the number of components. Cost per components decreases! S. Deleonibus, Electronics Device Architectures for the Nano-CMOS Era, Pan Standford Publ., 2009 MOORE S LAW (Gordon Moore Intel) G.E. Moore, Cramming more components onto integrated circuits, Electronics Mag., vol. 38, pp , 1965.

4 Microelectronic Revolution Example Intel 8008 (1972) 200 KHz transistors 13 mm 2 30 year X Intel Pentium 4 (2002) 2,2 GHz transistors 146 mm 2 Double each 2 years MOORE S LAW

5

6 Microelectronic Laboratory at USP Clean Room Facilities

7 Microelectronic Laboratory at USP Measurements Rooms Microwave Measurement Systems Optical Measurements Systems Devices Characterization Laboratory

8 Bulk MOSFET Transistor (Standard) Gate Source Metal Oxide Drain N+ N+ P Circuit Cell = Transistor I DS V DS =Low Bulk I DS V Tn V GS G I DS D V DS Triode Saturation V GS2 V GS1 V GS3 >V GS2 V GS S V DS

9 Circuit Cell = Transistor Bulk MOSFET Transistor ( Polysilicon Gate ) Source Gate Metal Oxide N+ N+ Drain Gate (G) P Bulk Source (S) Drain (D) Fabricated at Polytechnic School University of São Paulo Master Degree João Antonio Martino (1984)

10 Polysilicon Gate NMOS Technology Brazil (USP) Dimensions: 3mm x 3mm 4 Resistors 5 Capacitors 8 Transistors nmos 1 Diode 1 Ring Oscilator (31 stages) 2 Inverters 2 Adders (Full and Half) (J.A.Martino Master degree - USP ) Transistor

11 CMOS Technology - Brazil (USP) Dimensions: 3mm x 3mm 7 Van der Pauw structures e 2 Resistors 3 Kelvin structures 5 Capacitors 20 Transistors nmos 20 Transistors pmos 6 Diodes 1 Ring Oscilator(31 stages) 3 Inverters (J.A.Martino Ph.D - USP ) Transistors

12 SOI CMOS Technology (0.5 µm) University of Sao Paulo IMEC/Belgium Dimension:10mm x 10mm 221 structures more than 1000 terminals Transistor array from L=10µm to 0.4µm (J.A.Martino - Livre Docência - USP/IMEC-Belgium )

13 SOI CMOS Technology Submic. (0.1 µm) - IMEC/Belgium Gate (V GF ) Source (V S ) Drain (V D ) N+ N P+ P P+ N N+ Buried Oxide Substrate Substrate (V GB ) Dimensions: 10mm x 10mm Transistor arrays from L=10µm to 0,08µm

14 Evolution of MOS Transistors G Gate Gate S D Gate Source Drain Gate Gate Source N+ N+ Source Drain Drain I D P BOX Buried Oxide Bulk 1 Gate Single Gate Bulk - Planar (1966) 1 Gate Single Gate SOI - Planar (IBM ) 2 Gates FinFET Vertical-3D (Intel )

15 Double Gate Transistors (FinFET or 3D) Gate Drain I D Source Buried Oxide

16 Standard MOSFET versus FinFET(3D) Key Features of FinFET devices: SOI substrate; W Fin < 100nm; H Fin < 100nm; ADVANTAGES: Better control of short channel effects High current density (Higher conduction current per unit area of substrate) Quasi-ideal subthreshold slope

17 DESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET (3D) TRANSISTORS FAPESP Thematic Project ( ) 3 Universities: USP, UNICAMP, FEI Goal of this work: Development of new step process First Fabrication of SOI FinFET in Brazil Characterization (Electrical and Physical) Formation of qualified Human resource (Micro/Nanoelectronics)

18 Step by Step Step 1: Design of the fabrication process of SOI FinFET transistor (USP e UNICAMP). Step 2: Development of new step process (USP and UNICAMP). Step 3: Fabrication of SOI FinFET : (USP and UNICAMP). Step 4: Electrical Characterization of SOI FinFET.: (USP, UNICAMP and FEI) Step 5: Simulation of Numerical 3D SOI FinFET: (USP and FEI) Step 6: Modeling of SOI FinFET: (FEI) Step 7: Electrical Characterization of SOI FinFET as a function of temperature : (USP e FEI) Step 8: Reports: (USP, UNICAMP and FEI)

19 Special Characterizations (FEI and USP) DUV 193 nm lithography with resist and oxide hard mask trimming H fin =65 nm 1 nm interfacial oxide 2.3 nm HfSiON ALD deposition 5 nm TiN ALD deposition SOI wafer with t oxb =145 nm 100 nm polysilicon Undoped channel *N. Collaert et al., Symp. VLSI Tech., p. 108, NiSi in all electrodes

20 Special Characterizations (FEI and USP) Electrical Characterization of SOI FinFET as a function of temperature Digital performance Analog performance Radiation effects Noise analysis Modeling (only FEI) University of Sao Paulo

21 Special Characterizations (FEI and USP)

22 FinFET Fabrication with 3 masks First Mask (Active Region Definition): 1. E-beam lithography in a modified SEM (definition source/drain and fin line max space resolution: 30nm); 2. Mask transfer for Si layer by RIE Plasma processing; SiO 2 Si

23 FinFET Fabrication with 3 masks Mask 1 (Active Region Definition) SiO 2 Si

24 3. Gate oxidation (4.5nm); FinFET Fabrication with 3 masks Second Mask (Gate Definition): 4. Polycrystalline Silicon Deposition (500nm); 5. Poly-Si Phosphorous Doping; 6. E-beam lithography: Definition of Polycrystalline Silicon; Poly-Si Si SiO 2

25 FinFET Fabrication with 3 masks Poly-Si Si gate SiO 2 SOI SiO 2 Gate Definition Mask 2

26 FinFET Fabrication with 3 masks Third Mask (Metal Definition): 7. Ionic Implantation (Source/Drain); 8. Annealing (Doping Activation); 9. Aluminum Deposition; 10. E-beam Lithography: Metal Definition; Si Al Poly-Si SOI SiO 2

27 First FinFET Transistor (E-beam) Si Al Poly-Si SOI SiO 2 Metal definition Mask 3 Drain Gate Source

28 Electrical Characterization W FIN = 100nm, H FIN = 100nm, t ox = 4.5nm, t box = 200nm, L = 3.5µm, Gate electrode: Si-Poli I D (A) 1.6µ 1.4µ 1.2µ 1.0µ 800.0n 600.0n 400.0n 200.0n 0.0 V = 0V GB V = -5V GB V = -10V GB V = -15V GB V = -20V GB V GS (V) I D (A) 1µ 100n 10n 1n 100p 10p 1p 100f V GS (V) V = 0V GB V = -5V GB V = -10V GB V = -15V GB V = -20V GB First FinFET Transistor (E-beam)

29 Electrical Characterization W FIN = 100nm, H FIN = 100nm, t ox = 4.5nm, t box = 200nm, L = 3.5µm, Gate electrode: Si-Poli Drain Source Gate I D (A) 10.0µ V GS = -0,5V V GB =-15V V GS = -0,25V 8.0µ V GS = 0,0V V GS = 0,25V 6.0µ V GS = 0,5V V GS = 0,75V 4.0µ V GS = 1,0V 2.0µ V DS (V) First FinFET Transistor (E-beam)

30 Fin Obtained by FIB Narrowing W with FIB

31 Focused Ion Beam (FIB) FAPESP PROJECT

32 Fin Obtained by FIB Lithography + RIE etch Narrowing W FIN with FIB

33 Fin Obtained by FIB W Fin ~ 100 nm

34 FinFET Transistor (FIB) Al Al Si Al Buried Oxide Buried Oxide Al TiN SiO 2 Si p Si bulk

35 First FinFET Transistor (FIB) W FIN = 50nm, H FIN = 300nm, t ox = 10nm, t box = 400nm, L = 15 µm Gate electrode: TiN 1µ I DS (A) 100n 10n V GS (V) V DS = 0.5 V V DS = 1.0 V V DS = 1.5 V V DS = 2.0 V

36 First FinFET Transistor (FIB) W FIN = 50nm, H FIN = 300nm, t ox = 10nm, t box = 400nm, L = 15 µm Gate electrode: TiN 3.0µ V GS = 2 V I DS (A) 2.0µ 1.0µ 0.0 V GS = 0 V V DS (V)

37 First FinFET (3D) Transistors Drain Gate Source USP (E-Beam) UNICAMP (FIB)

38 EXPECTED RESULTS (OBTAINED) Publication of at least 16 journal papers Real: 2009: 4; 2010: 9; 2011: 16; 2012: 14 (total = 43) Publication of at least 64 full paper in a Conference proceedings Real: 2009: 27; 2010: 34; 2011: 34; 2012: 46 (total = 141) Formation of at least 4 Ph.D students. Real: 2009: 1; 2010: 3; 2011: 1; 2012: 2 (total= 7) Formation of at least 8 Master students Real: 2009: 6; 2010: 3; 2011: 3; 2012: 0 (total = 12)

39 João Antonio Martino (LSI/USP) Sebastião Gomes dos Santos Filho (LSI/USP) José Alexandre Diniz (CCS/UNICAMP) Marcelo Antonio Pavanello (FEI) Antonio Carlos Seabra (LSI/USP) Victor Sonnenberg (LSI/USP) Paula G. D. Agopian (LSI/USP/FEI) Milene Galeti (LSI/USP) Michele Rodrigues (LSI/USP) Ricardo Rangel (LSI/USP) Mariana Pojar (LSI/USP) Pos-Doc Ioshiaki Doi (CCS/UNICAMP) Stanislav Moshkalev (CCS/UNICAMP) Renato Giacomini (FEI) Michelly de Souza (FEI) Pos-Doc Rodrigo Doria (FEI) Pos-Doc

40

41 Acknowledgements

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