29.1 Introduction. Rashid Ch /10/5 1:57 Page 1 #1

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1 Rashid Ch /0/5 :57 Page # 29 High-Frequecy Iverters: From Photovoltaic, Wid, ad Fuel-Cell-Based Reewable- ad Alterative-Eergy ER/G Systems to Eergy-Storage Applicatios S.K. Mazumder, Sr. Member IEEE, Associate Professor, epartmet of Electrical ad Computer Egieerig, irector, Laboratory for Eergy ad Switchig-Electroics Systems (LESES), Uiversity of Illiois, Chicago, USA 29. Itroductio Low-Cost Sigle-Stage Iverter [2] Operatig Modes Aalysis esig Issues 29.3 Ripple-Mitigatig Iverter [3, 4] Zero-Ripple Boost Coverter (ZRBC) HF Two-Stage C AC Coverter 29.4 Uiversal Power Coditioer [] Operatig Modes esig Issues 29.5 Hybrid-Modulatio-Based Multiphase HFL High-Power Iverter [5 8] Priciples of Operatio [3] Refereces Itroductio Photovoltaic (PV), wid, ad fuel-cell (FC) eergy are the frot-ruer reewable- ad alterate-eergy solutios to address ad alleviate the immiet ad critical problems of existig fossil-fuel-eergy systems: evirometal pollutio as a result of high emissio level ad rapid depletio of fossil fuel. The framework for itegratig these zero-emissio alterateeergy sources to the existig eergy ifrastructure has bee provided by the cocept of distributed geeratio (G) based o distributed eergy resources (ERs), which provides a additioal advatage: reduced reliace o existig ad ew cetralized power geeratio, thereby savig sigificat capital cost. ERs are parallel ad stadaloe electric geeratio uits that are located withi the electric distributio system ear the ed user. ER, if properly itegrated, ca be beeficial to electricity cosumers ad eergy utilities, providig eergy idepedece ad icreased eergy security. Each home ad commercial uit with ER equipmet ca be a micropower statio, geeratig much of the electricity it eeds o-site ad sell the excess power to the atioal grid. The projected worldwide market is aticipated to be $50 billio by 205. A key aspect of these reewable- or alterative-eergy systems is a iverter (ote: for wid, a frot-ed rectifier is eeded) that feeds the eergy available from the eergy source to applicatio load ad/or grid. Such power electroics for ext-geeratio reewable- or alterative-eergy systems have to address several features icludig () cost, (2) reliability, (3) efficiecy, ad (4) power desity. Covetioal approach to iverter desig is typically based o the architecture illustrated i Fig. 29.a. A problematic feature of such a approach is the eed for a lie-frequecy trasformer (for isolatio ad voltage step-up), which is bulky, takes large footprit space, ad is becomig progressively more expesive because of the icreasig cost of copper. As such, recetly, there has bee sigificat iterest i high-frequecy (HF) trasformer-based iverter AQ: Copyright c 20, Elsevier Ic. All rights reserved.

2 Rashid Ch /0/5 :57 Page 2 #2 2 S.K. Mazumder Fuel-cell stack ad balace of plat cdc coverter cac coverter Applicatio load Lie trasformer Eergy bufferig uit Fuel-cell stack ad balace of plat cdc coverter cac coverter with high-frequecy trasformer Applicatio load Eergy bufferig uit Fuel-cell stack ad balace of plat cdc coverter with high-frequecy trasformer cac coverter Applicatio load Eergy bufferig uit (c) Fuel-cell stack ad balace of plat Isolated cac coverter Applicatio load Eergy bufferig uit (d) FIGURE 29. Iverter power-coditioig schemes [] with lie-frequecy trasformer; HF trasformer i the dc ac stage; (c) HF trasformer i the dc dc stage; ad (d) sigle-stage isolated dc ac coverter. approach to address some or all of the above-refereced desig objectives. I such a approach, a HF trasformer (istead of a lie-frequecy trasformer) is used for galvaic isolatio ad voltage scalig, resultig i a compact ad low-footprit desig. As show i Fig. 29.b,c, the HF trasformer ca be iserted i the dc dc or dc ac coverter stages for multistage

3 Rashid Ch /0/5 :57 Page 3 #3 29 High-Frequecy Iverters 3 AQ:2 power coversio. For sigle-stage power coversio, the HF trasformer is icorporated ito the itegrated structure. I the subsequet sectios, based o HF architectures, we describe several high-frequecy-lik (HFL) topologies [ 8], beig developed at the Uiversity of Illiois at Chicago, which have applicatios ecompassig photovoltaics, wid, ad fuel cells. Some have applicability for eergy storage as well Low-Cost Sigle-Stage Iverter [2] Low-cost iverter that coverts a reewable- or alterativeeergy source s low-voltage output ito a commercial ac output is critical for success, especially for the low-power applicatios ( 5 kw). Figure 29.2 shows oe such sigle-stage isolated iverter, which was origially proposed i [0] as a push pull amplifier. It achieves direct power coversio by coectig load differetially across two bidirectioal dc dc Ĉuk coverters ad modulatig them, siusoidally, with 80 phase differece. Because oly four mai switches are used, it would potetially reduce system complexity, costs, improve reliability, ad icrease efficiecy. Furthermore, the commo source coectio betwee two devices both at primary (Q a ad Q c ) ad secodary sides (Q b ad Q d ) makes the gate-drive circuit relatively simple. I additio, the possibility of couplig iductors or itegrated magetics will further reduce the overall volume ad weight, thereby achievig lesser material ad space usage. Aother advatage of this iverter is the reductio of turs ratio of the step-up trasformer, which is usually required to achieve rated ac from low dc voltage. The iheret voltage boostig capability of the Ĉuk iverter ca reduce the trasformer turs-ratio requiremet by at least half. Low trasformer turs-ratio yields less leakage iductace ad secodary widig resistace, which reduces the loss of duty cycle ad secodary copper losses, respectively Operatig Modes I order to uderstad how the curret flows ad eergy trasfers durig the switchig ad to help select the device ratig, four differet modes of the iverter are aalyzed ad show i Fig It shows the directio of the curret whe the load curret flows from the top to the bottom. Mode : Figure 29.3a shows the curret flow for the case whe switch Q a, Q d are ON ad Q b, Q c are OFF. urig this time, the curret flowig through the iput iductor La icreases ad the iductor stores the eergy. At the same time, the capacitor Ca discharges through Q a, ad thus, there is trasfer of eergy from the primary side to the secodary side through the trasformer T. The capacitor Cb is discharged to the circuit formed by Lb, C, ad the load R. Meawhile, the iductor Ld stores eergy, ad its curret icreases. The capacitor Cd discharges through Q d. The power flows i opposite directio i the Module 2 from the secodary side to the primary side. The capacitor Cc is also discharged to provide the power. Mode 2: Whe Q a, Q d are tured OFF, ad Q b, Q c are ON (Fig. 29.3b); Ca, Cd, Cb, ad Cc are charged usig the eergy, which was stored i the iductors La ad Ld, while Q a, Q d were ON. urig this time, Lb ad Lc will release their eergy. Figure 29.3c,d shows the curret directio whe the load curret flows i the opposite directio. The descriptio for these two modes is omitted due to the similarity with Fig. 29.3a,b Aalysis Although the oisolated iverter has already bee proposed [0], detailed aalysis ad desig of the isolated versio AQ:3 La Ca Module T Cb Lb Q a Q b C V i Vo Q c Q d C 2 Lc Cc Module 2 T2 Cd Ld FIGURE 29.2 Schematic of the sigle-stage dc ac differetial-isolated Ĉuk iverter [2].

4 Rashid Ch /0/5 :57 Page 4 #4 4 S.K. Mazumder V i La Q a Ca T Cb Lb C Vo Q d C 2 R Lc Cc T2 Cd Ld La Ca T Cb Q d Lb C V i Vo Q c Lc Cc T2 Cd Ld C 2 R V i La Q a Ca T Cb Lb C Vo Q d C 2 R Lc Cc Cd T2 (c) Ld La Ca T Cb Q b Lb C V i Vo Q c Lc Cc T2 (d) Cd Ld C 2 R FIGURE 29.3 irectio of the curret flow [2]: ad for positive load curret ad (c) ad (d) for egative load curret. Mode, whe Q a, Q d are ON ad Q b, Q c are OFF; Mode 2, whe Q a, Q d are OFF ad Q b, Q c are ON; ad (c) ad (d) are Modes 3 ad 4 correspodig to egative load curret.

5 Rashid Ch /0/5 :57 Page 5 #5 29 High-Frequecy Iverters 5 have ot appeared i ay literature. The output of the iverter is the differece betwee two sie-wave modulated PWM cotrolled isolated Ĉuk iverters (Module ad Module 2), with their primary sides coected i parallel. The two diagoal switches of two modules are triggered by a same sigal (Q a = Q d ad Q b = Q c ), while the two switches i each module have complemetary gate sigals (Q a = /Q b ad Q c = /Q d ). As we kow, the output voltage of a isolated Ĉuk iverter ca be expressed as follows: V o = V i N ( ), (29.) where is the duty ratio, N is the trasformer turs ratio, ad V i is the iput voltage. Because duty ratios for Modules ad 2 are complemetary, the output differece betwee the two modules is ( V o = V c V c2 = V i N ( ) N ). (29.2) The curves correspodig to the terms i (Eq. 29.2) with respect to the duty ratio (assumig N = ) are plotted i Fig The figure shows that although the gai-duty ratio curves of Modules ad 2 are ot liear, their differece is almost liear. Therefore, if a sie-wave-modulated duty ratio is used as a cotrol sigal for the iverter, the its output voltage will be a sie wave with small distortio esig Issues A kw sigle-stage isolated dc ac Ĉuk iverter prototype was desiged ad tested to verify its performace for fuel cell applicatio, where stack voltage is 36 V. Some desig issues are discussed later Choice of Trasformer Turs-Ratio ad uty-ratio Calculatio A iverter, ormally, if operatig at lower rage of duty ratio (i.e., lower modulatio idex) with output power ad iput dc voltage fixed will produce lower output voltage, i.e., a higher curret. This results i higher coductio losses ad lower efficiecy. Therefore, from the efficiecy poit of view, a iverter should usually operate at wide rage of duty ratio. However, there is a duty-ratio limitatio for proper operatio o the dc ac Ĉuk iverter. Ulike dc dc, the duty ratios of the cotrol PWM sigals are ot costat but sie-wave modulated. For a give iput voltage (36, for istace) ad output voltage (0 V ac, 60 Hz), the shape ad magitude of duty ratio () for dc ac Ĉuk iverter will vary accordig to trasformer turs ratio (N) [2]: V o V i = V m si(wt) 2 = V i N ( ). (29.3) Solvig, we obtai [2] = (α si(wt) 2) ± 4 (α si(wt)) 2 2α si(wt) = A ± B C, (29.4) where α = V m N/V i. It is a costat value. V m represets the amplitude of the desired output sie wave. The umerical calculatio shows that term B i (Eq. 29.4) is always larger tha A. Thus, A B is always positive while A B is egative. Therefore, oly (AB)/C is cosidered because has to be a positive value. Note, whe si(wt) 0, C 0, ad A B 0. I this case, is calculated usig L Hospital s rule as [2] = A B d(a B)/d(si(wt)) lim = = si(wt) 0 C d(c)/d(si(wt)) 2. (29.5) V out /V i FIGURE Voltage gai versus [2] for Modules ad 2 (top ad bottom), ad their differece (middle).

6 Rashid Ch /0/5 :57 Page 6 #6 6 S.K. Mazumder (c) FIGURE 29.5 The plotted waveforms [2] of = (A B)/C for variable trasformer turs ratio (solid). N = 2:; N = :2; ad (c) N = :5, as compared with a stadard sie wave (dash).

7 Rashid Ch /0/5 :57 Page 7 #7 29 High-Frequecy Iverters 7 AQ:4 TABLE 29. Shape ad rage of for differet trasformer turs ratio Turs ratio Shape of Magitude of Figure umber 2: Not a sie wave a :3 Close to a sie wave b :5 Very close to a sie wave c Figure 29.5 shows the plot of = (A B)/C for three differet trasformer turs ratios. The results are summarized i Table 29.. It is clearly show that, there is a trade-off betwee output voltage distortio ad duty-ratio rage. A optimal trasformer turs ratio, N = 3, is selected with correspodig varyig from 0.34 to Lossless Active-Clamp Circuit to Reduce Tur-Off Losses There will be severe voltage spikes ad rigig across the switches durig tur-off. They are caused by the trasformer ad other parasitic leakage iductaces combied with a very high curret reverse goig through the trasformer primary side. The spike problem is more serious at the poit where the output sie wave is at its peak because of the highest istataeous curret value at that poit. The circuit iside the dotted block of Modules ad 2 i Fig shows a lossless activeclamp circuit, which ca achieve zero-voltage tur-off, thereby reducig the tur-off losses ad limitig the maximum voltage across the mai switches. The circuit for each module cotais two auxiliary diodes, oe capacitor, oe iductor, ad oe switch. The auxiliary switches S s ad S s2 are triggered usig the same gate sigals as their correspodig mai switches. The equatios to calculate capacitace C s ad iductace L s are listed as follows [2]: ( ) V i (wt) 2 C s L lk, (29.6) f (V c max (wt) N V o (wt) Le) Le = (/N)2 La Lb La Lb (/N) 2, (29.7) 2 (wt) L s f 2 C s [ar cos( r(wt) ) r 2 (wt) ], (29.8) r(wt) = V c max(wt) V i, (29.9) where (wt) is the sie wave modulated duty ratio, V o (wt) is the sie wave output, V c max is the maximal clamped voltage, ad Le is the effective iductace. With referece to Fig. 29.6, whe the switch Q a turs OFF, the clamp circuit will create a alterate path formed by diode s ad capacitor C s to divert the tur-off curret from the primary switch Q a. After switch Q a ad S s are tured ON, the eergy stored i capacitor C s will evetually be fed back to the capacitor Ca as useful power. The performace of the active-clamp circuit alog with iverter performace is provided i detail i [] Ripple-Mitigatig Iverter [3, 4] The iverter (see Fig. 29.7) described i this sectio comprises a dc dc zero-ripple boost coverter (ZRBC), which geerates a high-voltage dc at its output followed by a soft-switched, trasformer isolated dc ac iverter, which geerates a 0 V ac. The HF-iverter switches are arraged i a multilevel fashio La Ca s L lk T V i Q a S s L s s C s S s2 C s2 Q c L s2 s2 Lc Cc s2 L lk2 T2 FIGURE 29.6 The sigle-stage Ĉuk iverter with lossless active-clamp circuit at the primary side [2].

8 Rashid Ch /0/5 :57 Page 8 #8 8 S.K. Mazumder ad are modulated by a fully rectified sie wave to create a HF, three-level ac voltage as show i Fig Multilevel arragemet of the switches is particularly useful whe the itermediate dc voltage >500 V. The HF iverter is followed by the ac ac coverter, which coverts the three-level ac to a voltage that carries the lie-frequecy siusoidal iformatio Zero-Ripple Boost Coverter (ZRBC) The ZRBC is a stadard oisolated boost coverter with the covetioal iductor replaced by a hybrid zero-ripple filter (ZRF). The ZRF (show i Fig. 29.8) is viewed as a combiatio of a coupled iductor (show i Fig. 29.7) ad a half-bridge active power filter (APF) (show i Fig. 29.7). Such a hybrid structure serves the dual purpose of reducig the HF curret ripples ad the low-frequecy curret ripples. The coupled iductor miimizes the HF ripple from the source curret (I C i 2 = i ) ad the APF miimizes the low-frequecy ripple from the source curret (I C i ac = i i ). I C is the dc supplied by the source, i 2 is the HF ac supplied by the series combiatio of idetical capacitors C ad C 2 (i Fig. 29.7), ad i ac is the low-frequecy ac supplied by the APF storage reactor L r. For effective reductio of the HF curret from the source output, the value of the capacitors C ad C 2 should be as large as possible. However, the series combiatio should be small eough to provide a high-impedace path to the low-frequecy curret i ac. Therefore, for a chose value of capacitor, the values of the followig expressio hold true [3]: C = C 2 = 2C, f HF = L2 C, f LF = 4Lr C, (29.0a) (29.0b) (29.0c) where f HF is the switchig frequecy of the coverter ad f LF is the lowest frequecy compoet i i ac. Assumig the switchig frequecy is approximately 20 times the lowest frequecy compoet, the value of ZRF passive ZRBC HF Iverter AC/AC Filter I FC Fuel cell stack N 2 Zero ripple filter L r 2 N I ac C C 2 I i S V C C3 C4 f f2 C fly S S 3 I L pri lk V pri :N o Q Q 3 a 2 3 L f I out C f V out V C V pri 0.5 NV C V ao (c) FIGURE 29.7 Schematic of the ripple-mitigatig iverter [3]. The source ca PV/battery/rectified wid as well.

9 Rashid Ch /0/5 :57 Page 9 #9 29 High-Frequecy Iverters 9 Coupled Iductor Half-Bridge Active Power Filter Zero Ripple Filter I FC i I FC I i I FC I I i N N V FC N 2 N 2 I ac I ac I 2 i 2 V FC C V FC C N 2 C L r 2 C 2 L r 2 C 2 (c) FIGURE 29.8 Schematic diagrams [3] ad [4] of coupled iductor structure for reducig the HF curret ripple; half-bridge active filter, which compesates for the low-frequecy harmoic-curret-ripple demad by the iverter; ad (c) the proposed hybrid ZRF structure. compoets L 2 ad L r ca be determied as follows [3]: L ihf i 2HF i 2HF L 2 f HF 20f LF, L2 C 0 Lr C, (29.0d) (29.0e) v FC i M L M l : v C L r 00L 2. (29.0f) AQ:5 Therefore, the value of L 2 should be small i order to limit the value of L r ad also to miimize the phase shift i the ijected low-frequecy curret i ac. I the followig subsectios, the HF ad low-frequecy acreductio mechaisms ad the coditios to achieve the same are discussed. I additio to this, the effect of coupled iductor parameters o the badwih of the ope-loop system will be discussed. For the purpose of aalysis, the value of the capacitors C ad C 2 is assumed to be large. Hece, the dyamics of the APF is assumed to have miimal effect o the coupled-iductor aalysis HF Curret-Ripple Reductio I this sectio, the iductace offered by the coupled iductor ad the ripple reductio achievable is discussed. For that purpose, we eed to derive a expressio for the effective iductace of the coupled iductor. Because the value of the capacitors C ad C 2 is large ad that of L 22 is small, the dyamics of the APF is assumed to have miimal effect o the coupled-iductor aalysis. The pi-model for the zero-ripple coupled iductor ad the excitatio voltage ad the curret for the primary ad the secodary widigs are show i Fig The currets i HF ad i 2HF are, respectively, the primary ad the secodary ac show i Fig. 29.9: FIGURE 29.9 Ac model for the coupled iductor show i Fig. 29.8a [3]. = N 2 N = L 22 L, (29.c) where L is the self iductace of the primary widig with N turs. Solvig (Eqs. 29.a) ad (29.b), the expressios for di HF ad di 2HF di HF di 2HF are obtaied usig = (L 2 L M )v FC L M v C (L L M )L 2 = v FC (L L M ) L M(v FC v C ) (L L M )L 2, (29.2a) = v FC v C L 2. (29.2b) By substitutig Eq. (29.2a) i Eq. (29.2b), we obtai the followig expressio: v FC = (L L M ) di HF v C = (L L M ) di HF di 2HF L M, (29.a) (L 2 L M ) di 2HF, (29.b) di HF = (L 2 L M )v FC L M v C (L L M )L 2 = v FC (L L M ) L M (L L M ) di 2HF. (29.2c)

10 Rashid Ch /0/5 :57 Page 0 #0 0 S.K. Mazumder Normalized effective iductace (L eff /L ) 0 9 k = k = 0.7 k = k = 0.3 k = Normalized ripple curret (di HtF /) k = 0. k = k = k = k = Turs ratio () Turs ratio () FIGURE 29.0 Normalized effective iductace ad ripple curret of the coupled iductor [3]. To reduce the ac compoet of the source curret to zero, the followig coditio should hold: di HF = di 2HF. (29.3) Therefore, usig the above coditio ad Eq. (29.2c), oe obtais [3] di HF = L [ v FC ( ) k ] = V FC. (29.4) L eff The deomiator of Eq. (29.4) is the effective iductace L eff offered by the coupled-iductor structure of the hybrid filter. The effective iductace depeds o the turs ratio, the couplig coefficiet k, ad the self iductace L of the primary widig. For very small values of turs ratio ( ), sigificatly large values of effective iductaces ca be obtaied. Figure 29.0 shows the effective iductace curves ad the correspodig reductio i the ripple. Figure 29.0a shows the depedece of ormalized L eff o as a fuctio of k. For the values of effective iductace show i Fig. 29.0a, the correspodig values of achievable ripple curret i both the coupled-iductor widigs are show i Fig. 29.0b. Usig Fig. 29.0b, a desiger ca decide o a value of HF curret ripple, ad usig the correspodig values of ad k the ormalized effective iductace ca be chose from Fig. 29.0a. While decidig the value of HF ripple, oe should choose a small value for (<0.25) to esure that L 22 is small eough to prevet sigificat variatios i the voltage across capacitors C ad C 2. Also, the effective iductace should be chose to meet the badwih requiremets of the ZRBC. Icrease i the effective iput iductace has a two-proged effect o the ope-loop frequecy respose of the ZRBC. First, the badwih is reduced, ad secod, the RHP zero is draw closer to the imagiary axis resultig i a reductio i the available phase margi ad thereby the ZRBC stability Active Power Filter The iput curret of the iverter comprises a dc compoet ad a 20-Hz ac compoet ad is expressed as [3] I dc I ac = V outi out where, V out are iverter output voltage cos(θ) V outi out cos (2ωt θ), (29.5) I out are iverter output curret is the average value of voltage across the series capacitors C ad C 2 θ is the load power factor agle. Here, we derive the coditio for low-frequecy curret ripple elimiatio from the PCS iput curret. For the APF show i Fig. 29.8, the voltage across the storage reactor L r of the APF is expressed as V ab = V a V ( dc 2 = S a ), (29.6) 2 where S a is the modulatig sigal. The reactor curret i r is i r = V ( dc Sa 2), (29.7) jωl r where, S a = 0.5 B si((ωt φ)) ad i r = jωl r B = si ( ( ωt φ π )) 2 (Cosiderig oly the fudametal compoet.)

11 Rashid Ch /0/5 :57 Page # 29 High-Frequecy Iverters The curret ijected by the APF is ( i ac = S a ) 2 i r, (29.8a) i ac = B (ωt 2 ωl si(ωt φ) si φ π r 2 [ ( π ) cos cos 2 i ac = 2ωL r B 2 ( 2ωt 2φ π 2 ), (29.8b) )]. (29.8c) I order to reduce the secod harmoic i the iput curret to zero, i ac = I ac [3] i ac = B (2ωt 2 2ωL cos 2φ π ) = V oi o cos(2ωt θ). r 2 This yields B = (29.9a) 2ωLr V o I o, (29.9b) φ = π 4 θ HF Two-Stage C AC Coverter (29.9c) The two-stage dc ac coverter (show i Fig. 29.7) comprises a soft-switched, phase-shifted SPWM, multilevel HF coverter (o the primary side of the trasformer) ad a liefrequecy-switched ac ac coverter (o the secodary side of the trasformer) followed by output low-pass filter. The multilevel arragemet of the HF coverter switches reduces the voltage stress ad the cost of the HF semicoductor switches. The ac ac coverter has two bidirectioal switch pairs Q ad, ad Q 3 ad for a sigle-phase output. To achieve a 60-Hz sie-wave ac at the output, a sie-wave modulatio is performed either o the HF dc ac coverter or o the ac ac coverter. Therefore, two differet modulatio strategies are possible for the dc ac coverter. Both schemes result i the soft switchig of the HF coverter, while the ac ac coverter is hard-switched. I the first modulatio scheme, the ac ac coverter switches follow SPWM, while the HF coverter switches are switched at fixed 50% duty ratio. The HF coverter switches i this scheme udergo zero-voltage tur-o. I the secod modulatio scheme, the switches of the multilevel HF coverter follow SPWM, ad the ac ac coverter switches are switched based o the power-flow iformatio. Ulike the first modulatio scheme, which modulates the ac ac coverter switches at HF, i the secod modulatio scheme, ac ac coverter operates at lie frequecy. The switches are commutated at HF oly whe the polarities of output curret ad voltage are differet. Usually this duratio is very small, ad therefore the switchig loss of the ac ac coverter is cosiderably reduced compared with the covetioal cotrol method. Therefore, the heat-sikig requiremet of the ac ac coverter switches is sigificatly reduced. The HF coverter switches i this scheme udergo zero-curret tur-off. Cotrol sigals for the secod modulatio scheme are show i Fig Uiversal Power Coditioer [] This approach achieves a direct power coversio ad does ot use ay frot-ed dc dc coverter. As show i Fig. 29.2, this approach has a HF dc ac coverter followed by a HF trasformer ad a forced ac ac coverter. Switches (Q ) o the primary side of the HF trasformer are sie-wave modulated to create a HF three-level bipolar ac voltage. The threelevel ac at the output of the HF trasformer is coverted to 60/50-Hz lie-frequecy ac by the ac ac coverter ad the output LC filter. For a iput of 30 V, the trasformatio ratio of the HF trasformer is calculated to be N = 3. Fabricatio of a :3 trasformer is relatively difficult. Furthermore, high turs-ratio yields ehaced secodary leakage iductace ad secodary widig resistace, which result i measurable loss of duty cycle ad secodary copper losses, respectively. Higher leakage also leads to higher voltage spike, which added to the high omial voltage of the secodary ecessitate the use of high-voltage power devices. Such devices have higher o-resistace ad slower switchig speeds. Therefore, a combiatio of two trasformers ad two ac ac coverters o the secodary side of the HF trasformer is idetified to be a optimum solutio. For a iput voltage i the rage of V, we use N = 6.5, while for a iput voltage of more tha 42 V, we use N = 4.3. To chage the trasformatio ratio of the HF trasformer, we use a sigle-pole double-throw (SPT) relay, as show i Fig. 29.2a,b. Such a arragemet ot oly improves the efficiecy of the trasformer but also sigificatly improves the utilizatio of the ac ac coverter switches for operatio at 20/240 V ac ad 60/50 Hz. For 20-V ac output, the two ac ac-coverter filter capacitors are paralleled (as show i Fig. 29.2a), while for 240-V ac output, the voltage of the filter capacitor are coected i oppositio (as show i Fig. 29.2b). Fially, Fig shows the closedloop cotrol mechaism of the iverter for grid-parallel ad grid-coected modes. It is described i detail i [] ad ot repeated here Operatig Modes I this sectio, we discuss the modes of operatio of the iverter i Fig for 20-V ad 240-V ac output ad for a iput voltage i the rage of V (i.e., N = 4.3). The modes of operatio less tha 42 V (i.e., N = 6.5) remai the same. Figures 29.4 ad 29.5 show the waveforms of the five operatig modes of the phase-shifted HF iverter ad a positive primary ad a positive filter-iductor curret. Modes 2 ad 4 show the zero-voltage switchig (ZVS) tur-o mechaism

12 Rashid Ch /0/5 :57 Page 2 #2 2 S.K. Mazumder Q Q 3 Modulatig sigal for the HF iverter Iverter output voltage Iverter output curret S S 3 Q Q 3 V pri I pri S S 3 Q Q 3 UC3895 J C lk K q q Logic Operator p C p V ZC ZC i 0 Q Q 3 Logic operator q q p V p C G c = K p K i /s V 0 V ref (c) FIGURE 29. ad Schematic waveforms [3] for the HF dc ac coverter o the primary side of the trasformer ad the ac ac coverter o the secodary side of the trasformer. (c) Overall cotrol scheme for the two-stage HF iverter. for switches Q 3 ad, respectively. Ulike covetioal cotrol scheme for ac ac coverter [2], which modulates the switches at HF, the outlied ac ac coverter operates at lie frequecy. The switches are commutated at HF oly whe the polarities of the output curret ad voltage are differet [2]. For uity-power-factor operatio, this duratio is egligibly small, ad therefore, the switchig loss of the ac ac coverter is cosiderably reduced compared with the covetioal cotrol method [3]. Five modes of the iverter operatio are discussed for positive primary curret. A set of five modes exists for a egative primary curret as well. A similar set of five modes of operatio for the 240 V ac exists for iput voltage of more tha 42 V (N = 4.5). Agai, the mode of operatio for iput voltage of less tha 42 V (N = 6.5) remais the same. Mode (Fig. 29.4a): urig this mode, switches Q ad of the HF iverter are ON, ad the trasformer

13 Rashid Ch /0/5 :57 Page 3 #3 29 High-Frequecy Iverters 3 c ac coverter Ac ac coverter Filter S S 3 L f Q Q 3 S S 3 C f C L f2 C f2 c ac coverter Ac ac coverter Filter S S 3 L f Q Q 3 S S 3 C f C L f2 C f2 FIGURE 29.2 Circuit diagrams [] of the proposed fuel-cell iverter for 20 V/60 Hz ac outputs ad 240 V/50 Hz ac outputs. A sigle-poledouble-throw (SPT) switch eables adaptive tappig of the trasformer. primary curret I p ad I p2 is positive. The load curret splits equally betwee the two cyclocoverter modules. For the top cyclocoverter module, the load curret I out /2 is positive ad flows through the switches pair S ad S, the output filter L f ad C f, switches ad, ad the trasformer secodary. Similarly, for the bottom cyclocoverter module, the load curret 0.5 I out is positive ad flows through the switches pair ad, the output filter L f2 ad C f2, switches ad, ad the trasformer secodary. Mode 2 (Fig. 29.4b): At the begiig of this iterval, the gate voltage of the switch Q udergoes a high-to-low trasitio. As a result, the output capacitace of Q begis to accumulate charge ad, at the same time, the output capacitace of switch begis to discharge. Oce the voltage across goes to zero, it is ca be tured o uder ZVS. The trasformer primary currets I p ad I p2 ad the load curret I out cotiue to flow i the same directio. This mode eds whe the switch Q is completely tured OFF ad its output capacitace is charged to V C.

14 Rashid Ch /0/5 :57 Page 4 #4 4 S.K. Mazumder HF iverter switches Cyclocoverter switches V FC O PCB V Cf UC3895 Phase-shift cotroller AC Logical operatios Voltage sesor gai Voltage sesor gai Zero-crossig detectio Adaptive K p selector Compesator G c = K p K i /s Filter AC SP V ref HF iverter switches Cyclocoverter switches UC3895 Phase-shift cotroller AC Logical operatios y FC Voltage sesor gai V grid Voltage sesor gai i LF Curret sesor gai Zero-crossig detectio Adaptive K p selector P o AC Filter Compesator G c = K p K i /s Filter AC FIGURE 29.3 ad Schematics for coverter operatio [], respectively, at 20 V ac ad 60 Hz ad 240 V ac ad 50 Hz. (c) ad (d) Cotrol schemes of the iverter i grid-parallel ad grid-coected modes. Mode 3 (Fig. 29.4c): This mode iitiates whe Q turs OFF. The trasformer primary currets I p ad I p2 are still positive, ad free wheels through as show i Fig. 29.4c. Also the load curret cotiues to flow i the same directio as i Mode 2. Mode 3 eds at the commecemet of tur off. Mode 4 (Fig. 29.4d): At the begiig of this iterval, the gate voltage of udergoes a high-to-low trasitio. As a result, the output capacitace of begis to accumulate charge ad, at the same time, the output capacitace of switch Q 3 begis to discharge as show i the Fig. 29.4d. The chargig curret of ad the dischargig curret of Q 3 together add up to the primary currets I p ad I p2. The trasformer curret makes a trasitio from positive to egative. Oce the voltage across Q 3 goes to zero, it is tured ON uder ZVS. The load curret flows i the same directio as i Mode 3 but makes a rapid trasitio from the bidirectioal switches S ad S ad ad to S 3 ad S 3 ad ad, ad durig this process I out /2 splits

15 Rashid Ch /0/5 :57 Page 5 #5 29 High-Frequecy Iverters 5 c ac coverter Mode Ac ac coverter c ac coverter Mode 2 Ac ac coverter C Q Q 3 V pri i pri S S i sec S3 S 3 v a C f L f va i out C Q Q 3 V pri i pri S S i sec S 3 S 3 v a C f L f v a i out i sec i sec2 i sec i sec2 i pri2 v a C f2 L f2 i pri2 S 7 v a C f2 L f2 i sec2 i sec2 c ac coverter Mode 3 Ac ac coverter c ac coverter Mode 4 Ac ac coverter i sec i sec S S 3 S S 3 C Q Q 3 V pri i pri S L f S 3 v a C f v a i out C Q Q 3 Q4 V pri i pri S S 3 v a C f L f v a i out i sec i sec2 i sec i sec2 i pri2 S L f2 S 7 v a C f2 i pri2 S 7 v a C f2 L f2 i sec2 i sec2 (c) (d) Gatig Pulses Q Q Q 3 c ac coverter Mode 5 Ac ac coverter i sec ν pri Q Q 3 V i dc pri V C pri S S S 3 S 3 v a C f L f v a i out i pri i sec i sec2 i pri2 L f2 v a Cf2 i sec i sec i sec2 Mode Mode 2 ad 3 Mode 3 Mode 4 ad 5 (e) (f) FIGURE 29.4 Modes of operatio [] for 20 V ac for iput voltage i the rage of V (N = 4.3): (a e) topologies correspodig to the five operatig modes of the overall dc ac coverter for positive primary curret ad for power flow from the iput to the load. (f) Schematic waveforms show the operatig modes of the HF iverter whe primary currets are positive. The modes of operatio of less tha 42 V (i.e., N = 6.5) remai the same.

16 Rashid Ch /0/5 :57 Page 6 #6 6 S.K. Mazumder c ac coverter Mode Ac ac coverter c ac coverter Mode 2 Ac ac coverter C Q Q 3 V pri i pri S S i sec S3 S 3 v a C f L f νa i out C Q Q 3 V pri i pri S S i sec S 3 S 3 v a C f L f ν a i out i sec i sec2 i sec i sec2 i pri2 v a C f2 L f2 ν b i pri2 L f2 S 7 v a C f2 ν b i sec2 i sec2 c ac coverter Mode 3 Ac ac coverter c ac coverter Mode 4 Ac ac coverter i sec i sec C Q Q 3 V pri i pri S S 3 S S 3 v a C f L f ν a i out C Q Q 3 V pri i pri S S S 3 S 3 v a C f L f ν a i out i sec i sec2 i sec i sec2 i pri2 S 7 v a C f2 L f2 ν b i pri2 S 7 v a C f2 L f2 ν b i sec2 i sec2 (c) (d) Gatig pulses Q Q Q 3 c ac coverter Mode 5 Ac ac coverter v pri i sec C Q Q 3 V pri i pri S S S 3 S 3 v a C f L f ν a i out i pri i sec i sec2 i sec i pri2 L f2 S 7 v a C f2 ν b i sec i sec2 Mode Mode 2 ad 3 Mode 3 Mode 4 ad 5 (e) (f) FIGURE 29.5 Modes of operatio [] for 240 V/50 Hz ac output for a iput-voltage rage of V (correspodig to N = 4.3): (a e) topologies correspodig to the five operatig modes of the iverter for positive primary ad positive filter-iductor currets. (f) Schematic waveforms show the operatig modes of the dc ac coverter whe primary currets are positive. The modes of operatio of less tha 42 V (correspodig to N = 6.5) remai the same.

17 Rashid Ch /0/5 :57 Page 7 #7 29 High-Frequecy Iverters 7 betwee the two legs of the cyclocoverter modules as show i Fig. 29.4d. Mode 4 eds whe the switch is completely tured OFF, ad its output capacitace is charged to V C. At this poit, it is ecessary to ote that because S ad are OFF simultaeously, each of them support a voltage of V C. Mode 5 (Fig. 29.4e): This mode starts whe is completely tured OFF. The primary currets I p ad I p2 are egative, while the load curret is positive as show i Fig. 29.4e esig Issues uty-ratio Loss As show i Fig. 29.6, the fiite slope of the risig ad fallig edges of the trasformer primary curret because of the leakage iductace (L lk ) will reduce the duty cycle (d). This duty-ratio loss is give by [] d = L lk N T2 ( 2i out v out ( d) T ), (29.20) L f 2 where N is the trasformer turs ratio, L f is the output filter iductace, i out is the filter curret, v out is the output voltage, ad T is the switchig period. Assumig that L f is large eough, the secod term i Eq. (29.20) ca be omitted. Thus, the duty-ratio loss has a siusoidal shape ad is proportioal to N ad L lk. Oe ca deduce from Eq. (29.20) that, due to the high turs-ratio ad low-iput voltage, eve a small leakage iductace will cause a big duty-ratio loss. Figure 29.7 shows (for a -kw iverter) the calculated dutyratio loss for a iput voltage of 30 V ad for N = 6.5. Four parametric curves correspod to four leakage iductaces of 0.5,,.5, ad 2 µh are show. Figure 29.7 shows that, for a L lk of 2 µh, the duty-ratio loss is more tha 25%. Cosequetly, a trasformer with eve higher turs-ratio is required to compesate for this loss i the duty ratio, which icreases the coductio loss ad evetually decreases the efficiecy. i i i 2 t t 2 t 4 slope = /L lk t 5 t 6 0 t 3 d eff T/2 t v pri d T/2 d T/2 T/2 i pri Optimizatio of the Trasformer Leakage Iductace The leakage iductace of the HF trasformer ehaces the ZVS rage of the dc ac coverter but reduces the duty ratio of the coverter, which icreases the coductio loss. Thus, the leakage iductace of each trasformer is desiged to achieve the highest efficiecy, as illustrated i Fig For the siusoidally modulated dc ac coverter, the ZVS capability is lost twice i every lie cycle. The extet of the loss of ZVS is a fuctio of the output curret. The available ZVS rage (t ZVS ) as a percetage of the lie cycle (t LieCycle ) is give by [] t ZVS = 2 t LieCycle π si 4 uty ratio loss Variatio of duty-ratio loss as a fuctio of L lk over half- FIGURE 29.7 a-lie cycle []. ZVS rage (% of lie cycle) V 2 dc ( 4 3 C oss 2 C T 2 uh.5 uh uh 0.5 uh i 2 outl lk ) /2, (29.2) ωt [0, π] Power (W ) L k = 0.3 uh L k = 0.4 uh L k = 0.5 uh L k = 0.6 uh Trasformer primary-side voltage ad curret wave- FIGURE 29.6 forms []. FIGURE 29.8 ZVS rage of the dc ac coverter with variatio i output power [].

18 Rashid Ch /0/5 :57 Page 8 #8 8 S.K. Mazumder 9.9 Switch loss (W ) Leakage iductace (µh) FIGURE 29.9 Variatio of the total switch loss of the dc ac coverter with the leakage iductace of the HF trasformer []. where C oss is the device output capacitace ad C T is the iterwidig capacitace of the trasformer. Whe the dc ac coverter is ot operatig uder ZVS coditio, the devices are hard-switched. A umerical calculatio of the total switchig losses for the -kw iverter, as show i Fig. 29.9, idicates that the optimal primary-side leakage iductace for the HF trasformer should be betwee 0.2 ad 0.7 µh. Clearly, as the leakage iductace of the HF trasformer icreases, the total switchig loss decreases due to a icrease i the rage of ZVS, while the total coductio loss icreases with icreasig leakage iductace Trasformer Tappig The voltage variatio o the secodary side of the HF trasformer ecessitates high-breakdow-voltage ratig for the ac ac-coverter switches ad dimiishes their utilizatio. For a step-up trasformer with N = 6.5, the ac ac-coverter switches have to withstad at least 390 V omial voltage whe iput ramps to the high ed (60 V), while oly 95 V is required whe 30 V is the iput. I additio to the omial voltage, the switches of the ac ac coverter have to tolerate the overshoot voltage (as show i Fig ) caused by the oscillatio betwee the leakage iductace of the trasformer ad the juctio capacitaces of the power MOSFETs durig turoff []. The frequecy of this oscillatio is determied usig f rig = 2π N 2 L lk C eq, where C eq is the equivalet capacitace of the switch output capacitace ad the parasitic capacitace of the trasformer widig. The covetioal passive subber circuit or active-clamp circuits ca be used to limit the overshoot but they will iduce losses, icrease the system complexity, ad compoet costs. Oe simple but effective solutio is to adjust the trasformer turs ratio accordig to the iput voltage. To chage the turs ratio of the HF trasformer, a bidirectioal switch is required. Cosiderig its simplicity ad FIGURE rai-to-source voltage [] across oe of the ac ac coverter power MOSFETs. low coductio loss, a low-cost SPT relay is chose for the iverter, as show i Fig For this prototype, for a iput voltage i the rage of V, N equals 6.5. Hece, 500 V devices are used for the highest iput voltage cosiderig a 80% overshoot i the drai-to-source voltage that was observed i experimets. For a iput voltage of more tha 42 V, N equals 4.3, ad hece the same 500 V devices ca still be used to cover the highest voltage as the magitude of the voltage oscillatio is reduced. The relay is activated ear the zero-crossig poit (where power trasfer is egligible) to reduce the irush curret. Such a arragemet improves the efficiecy of the trasformer ad sigificatly icreases the utilizatio of the ac ac-coverter switches for the full rage of the iput voltage. However, without adaptive trasformer tappig, the miimal voltage ratig for the devices is give by max N (80%) = = 702 V. I practice, power MOSFETs with 800 V or higher breakdow-voltage ratigs are, therefore, required because of the lack of 700 V ratig devices. The so-called rule of silico limit (i.e., R o BV 2.5, where BV is the breakdow voltage) idicates that, i geeral, highervoltage-ratig power MOSFETs will have higher R o ad hece higher coductio losses. Furthermore, for the same curret ratig, the switchig speed of a power MOSFET with higher breakdow-voltage ratig is usually slower. As such, coverter efficiecy is expected to degrade further as a result of ehaced power loss Effects of Resoace betwee the Trasformer Leakage Iductace ad the Output Capacitace of the AC AC-Coverter Switches Resoace betwee the trasformer leakage iductace ad the output capacitace of the ac ac-coverter devices causes the peak device voltage to exceed the omial voltage (obtaied

19 Rashid Ch /0/5 :57 Page 9 #9 29 High-Frequecy Iverters 9 AQ:6 Peak secodary voltage (V ) Iput voltage (V ) FIGURE 29.2 Peak voltage across the ac ac coverter [] with varyig iput voltage for a trasformer primary leakage iductace of 0.7 µh, output capacitace of 240 pf (for the devices of the ac ac coverter), ad output filter iductace ad capacitace of mh ad 2.2 µf, respectively. i the absece of the trasformer leakage iductace). This is demostrated i Fig Cosiderig N = 6.5, oe ca observe that the peak secodary voltage ca be aroud twice the omial secodary voltage. Cosequetly, the breakdowvoltage ratig of the ac ac-coverter switches eeds to be higher tha the omial value. As power MOSFETs are used as switches, higher breakdow voltage etails icreased oresistace that yields higher coductio loss. So, the leakage affects the coductio loss ad the selectio of the devices for the ac ac coverter. The resoace begis oly after the secodary curret completes chagig its directio ad the ac ac-coverter switches iitiate tur-o or tur-off. urig this resoace period, eergy is trasferred back ad forth betwee the leakage ad filter iductaces ad the device ad filter capacitaces i a almost-lossless maer. The curret through the switch that supports the oscillatig voltage is almost zero. Thus, practically, o switchig loss is icurred because of this resoace pheomeo although it may have a impact o the electromagetic-emissio profile Hybrid-Modulatio-Based Multiphase HFL High-Power Iverter [5 8] Recet high-voltage SiC MOSFETs, with X lower oresistace, ad SiC JBS diodes, with superior reverse recovery ad with projected >3X thermal susteace ad coductivity alog with advaced high-permeability ad high-efficiecy aocrystallie core (e.g., with > T flux desity) trasformers pave way for isolated high-power ad HFL iverters. They have attaied sigificat attetio with regard to wide applicatios ecompassig high-power reewable- ad alterative-eergy systems (e.g., photovoltaic, wid, ad fuel-cell eergy systems), G/ER applicatios, active filters, eergy storage, compact defese power-coversio modules for defese, as well as commercial electric/hybrid vehicles because of potetial for sigificat reductio i materials ad labor cost without much compromise i efficiecy. Alog that lie, a ew iovatio i the form of a hybrid modulatio (HM) [5, 6] has bee put forward by the author recetly that sigificatly reduces the switchig loss of HFL topologies (e.g., Fig [5 8]). The HM scheme is ulike all reported discotiuous-modulatio (M) schemes where the iput to the fial stage of the iverter is a dc ad ot a pulsatig-dc; further, i the HM scheme, switches i two legs of the ac ac coverter do ot chage state i a 60 cycle, ad switches i ay oe leg do ot chage state for a overall 240. I cotrast, for a covetioal M scheme, most switches of oe leg of the ac ac coverter do ot chage stage i a 60 or 20 cycle. The preset three-phase HM scheme is also differet from earlier reported modulatio schemes for sigle-phase, direct-power-coversio systems. The primary role of the modulatio scheme for the sigle-phase ac ac coverter is to demodulate the rectifier output o a half-lie-cycle basis to geerate the output sie-wave-modulatio patter by switchig all the ac ac coverter devices uder low-frequecy coditio Priciples of Operatio [3] Three-Phase C AC Iverter Figure illustrates the geeratio of switch-gate sigals for the proposed coverter. The bottom switches are cotrolled complimetarily to the upper oes, hece they are ot described further. Three gate-drive sigals UT, VT, ad WT for primary side devices are obtaied by phase shiftig a square wave with respect to a 0-kHz square wave sigal Q (show i Fig b). Q is sychroous with a 20-kHz saw-tooth carrier sigal, show i Fig a. The phase differeces are modulated siusoidally usig three 60 Hz refereces a, b, ad c, respectively. Two gate sigals for phase U ad V are plotted i Fig c ad d. Because carrier frequecy is much higher tha the referece frequecy, UT, VT, ad WT will be square wave with the frequecy of 0 khz, ad their phases are modulated. The obtaied output lie lie voltages at the primary side of the trasformers are bipolar waveforms. V uv is plotted i Fig e as a example. After passig through HF trasformers, they are rectified by a three-leg diode bridge at the secodary side to obtai a uipolar PWM waveform, which has six-pulse as evelop. Its waveform is show i Fig g, ad the mathematic expressios are: V rec = N Max ( UT VT, VT WT, WT UT ), (29.22) UT = Q PWM a VT = Q PWM b WT = Q PWM c, (29.23)

20 Rashid Ch /0/5 :57 Page 20 #20 20 S.K. Mazumder UT C AC coverter AC C coverter AC AC coverter VT WT Naocrystalie HF trasformer UUT VVT WWT UUT VVT WWT G G G G G G S S S S S S G G G S S S a C Pulsatig C V rec b AC c UB VB WB G G S G S S N2 UUB VVB WWB G G G S S S UUB VVB WWB G G G S S S SiC MOSFET SiC MOSFET SiC MOSFET FIGURE Schematic of the HM-based HFL topology. A covetioal fixed-dc-lik (FCL) topology has the same architecture except that it has a filter capacitor after the ac dc rectifier stage, ad hece, the output ac ac coverter is fed with a dc voltage rather tha a pulsatig dc voltage (V rec ) for the HFL scheme. The HM scheme is implemeted for the ac ac coverter stage. For the FCL topology, the output stage is a voltage source iverter (VSI), which is operated usig SVM scheme. Ref_a Ref_b Ref_c Carrier 2 PWMa PWMb PWMc Q UT VT WT UB VB WB ab ba bc cb ca ac mod HF UUT VVT WWT UUB VVB WWB Ramp 0 FIGURE iagram of gate-drive-sigal geeratio for the HFL iverter [3]. where PWM x (x = a, b, or c) deotes the biary comparator output betwee referece ad carrier for phase x. Symbol stads for XNOR operatio. N is the trasformer turs ratio. ivide the six-pulse rectified waveform ito six segmets amed P P6 as show i Fig g. The risig ad fallig edges of V rec are differet for differet segmets. Figure 29.24a f show a particular time iterval withi segmet 2, where the risig ad fallig edges of V rec (marked as V rec ad V rec ) are determied by the edges of UT ad VT, respectively. Other cases are summarized i Table Switchig Strategy for the AC AC Coverter Similar to the case of three-phase ac dc rectifier, the rectified PWM output is cotributed respectively by V wv, V uv, V uw, V vw, V vu, ad V wu at each segmet from P to P6. The bottom part of the Fig shows the diagram of geeratig switchig sigals for three upper switches of secodary-side ac ac iverter. urig each segmet, every switch will be either: permaetly ON (), permaetly OFF (0), or togglig with 20 khz. The switchig patter for the upper three switches i each segmet for oe cycle period is summarized i Table 29.3.

21 Rashid Ch /0/5 :57 Page 2 #2 29 High-Frequecy Iverters 2 (c) (d) (e) (f) (a ) FIGURE Key waveforms [3] of the primary-side dc ac coverter i oe cycle ad elarged view of the iterval betwee two dot lies; three-phase sie-wave refereces ad carrier sigal; Q: square ware with half frequecy of the carrier; (c) UT: gate sigal for the upper switch of phase U; (d) VT: gate sigal for the upper switch of phase V; (e) V uv : output of phase U ad V; ad (f) V rec : output waveform of the rectifier. (b ) (c ) (d ) (e ) (f ) TABLE 29.2 The edge depedece of the rectifier output o gate sigals P P2 P3 P4 P5 P6 V rec wt ut ut vt vt wt V rec vt vt wt wt ut ut TABLE 29.3 Switchig patter for upper switches of the ac ac iverter P P2 P3 P4 P5 P6 V rec V wv V uv V uw V vw V vu V wu UUT HF ON ON HF OFF OFF VVT OFF OFF HF ON ON HF WWT ON HF OFF OFF HF ON Mod ab cb bc ac ca ba The switch positios illustrated i Fig are for the case of segmet P2. Because the rectifier output has the same shape as V uv withi this iterval, the lie lie voltage V ab at the output side of the ac ac iverter ca be directly obtaied by keepig switches UUT ad VVT at ON ad OFF status, respectively. Aother lie lie voltage V cb, however, eeds to be achieved by operatig switches o the third leg WWT ad WWB uder HF coditio, where modulated sigal (mod) is the differece betwee refereces c ad b ad the carrier sigal (ramp) is a 20-kHz saw-tooth waveform sychroized with the PWM output of the rectifier. The key waveforms are show i Fig The mathematical expressio for three lie lie voltages is give as follows: V ab = V rec (UUT VVT) V cb = V rec (WWT VVT) V ca = V cb V ab (29.24) A illustratio of the ac ac coverter s HM scheme (as compared with several other SVM ad SPWM schemes) is show i Fig The outlied switchig strategy is the best optio for resistive load because the peaks of the currets follow the peaks of the fudametal voltages. Therefore, each phase leg does ot switch just whe the curret is at its maximum value, thereby miimizig switchig losses. For uity-power-factor load, the HM scheme for the ac ac coverter ca be adjusted accordigly for miimizig the losses.

22 Rashid Ch /0/5 :57 Page 22 #22 22 S.K. Mazumder P P2 P3 P4 P5 P6 P (g) ab cb bc ac ca ba ab (h) (i) (j) (k) (l) (g ) (h ) (i ) (j ) (k ) (l ) FIGURE Key waveforms [3] of the secodary-side ac ac iverter i oe cycle ad elarged view of the iterval betwee two dot lies; (g) V rec : output PWM waveform of rectifier with six-pulse evelop; (h) mod: modulated sigal ad ramp: the carrier which is sychroous with (g); (i) UUT: gate sigal for the top switch of phase a; (j) VVT: gate sigal for the top switch of phase b; (k) WWT: gate sigal for the top switch of phase c; ad (l) PWM output of the lie lie voltage V ab ad its evelop. Sie wave ad /6th third harmoic V V0 V7 Hybrid modulatio FIGURE Modulatio fuctios correspodig to sie wave (with /6th third harmoic), V0, V0 V7 SVMs, ad HM schemes. Blue ad red traces represet zero sequece ad siusoidal sigals. Black trace is the modulatig sigal.