Study on the application of the software phase-locked loop in tracking and filtering of pulse signal

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1 Advaced Sciece ad Techology Letters, pp Study o the applicatio of the software phase-locked loop i trackig ad filterig of pulse sigal Sog Wei Xia 1 (College of Electrical ad iformatio,northeast Agricultural Uiversity,Harbi, Abstract. This paper discusses the mathematical model of software phase locked loop (PLL) accordig to the characteristics of PLL ad the lik betwee the digital system ad simulatio system. The simulatio model of two order based o MATLAB platform is developed to aalyze the properties of PLL ad effects from the dampig coefficiet ad the atural resoat frequecy i differet sigal oise effects. The work realizes the trackig filterig o pulse sigal. Keywords: sigal-to-oise ratio; Software radio; dampig coefficiet; atural resoat frequecy. 1 Itroductio The techique of phase lockig is oe of the importat methods for sigal tracig filter. The method is applied i commuicatio, aerospace, ad measurig widely [1]~ [3]. Narrow-bad filter ca improve the sigal-to-oise ratio ad acquire detected sigal of differet time ad differet frequecies i sigal processig [4]~ [6]. However, it is difficult to realize tracig filter for C-W pulses usig arrow-bad filter, sice the ceter frequecy chages costatly i C-W pulses. At preset, may researchers pay attetio to the techique of tracig filter i sigal. Some results have bee achieved i this aspect, but it is ot eough for C-W pulses. The trouble is that C-W pulses ca be traced whe it appears while C-W pulses ca t be traced whe it disappears. The priciple of software PLL was itroduced ad the method of phase lockig ad tracig C-W pulses usig PPL was proposed i this paper. Fially, the fuctio of PPL based o software was proposed, ad the tracig procedure was simulated usig MATLAB. 1 Sog Wei Xia is a Ph.D. studet i the Agricultural Electrificatio ad Automatio School at College of Electrical ad iformatio, Northeast Agricultural Uiversity. His fields of research are Weak Sigal Detectio, Agricultural Products Detectio ad Sigal Processig. ISSN: ASTL Copyright 2014 SERSC

2 Advaced Sciece ad Techology Letters 2 The simulatio aalysis 2.1. The effect of atural resoat frequecy o the phase-locked loop performace The maximum of doppler frequecy offset is f khz whe the sigal ceter frequecy is 35.5 Hz. The 35 KHz referece sigal is used for trackig. At this poit the frequecy offset is 0.5KHz f 4716 max max, so that whe ,the simulatio results are show from Fig.1 to Fig.3. Fig. 1. Phase locked trackig simulatio diagram, 4200 Fig. 2. Phase locked trackig simulatio diagram, 5000 Fig. 3. Phase locked trackig simulatio diagram, Copyright 2014 SERSC

3 Advaced Sciece ad Techology Letters Simulatio diagrams above have show that i the reasoable greater mas the faster capture speed ad the smaller trackig precisio. rage the meas the higher 2.2. The effect of SNR o the phase-locked loop performace The 35KHz referece sigal is used for the phase-locked trackig of the 35.3KHz iput sigal, at this poit the frequecy deviatio is 0.3KHz. The samplig rate is 300KHz, ad the dampig coefficiet is Whe the SNR is 40dB, the output phase displacemet of phase discrimiator is show i Fig.4. Fig.4. The output phase displacemet of phase discrimiator, SNR=40dB The measured iput sigal frequecy is Hz, ad the error is Hz. Whe the SNR is 10dB, the output phase displacemet of phase discrimiator is show i Fig.5. Fig.5. The output phase displacemet of phase discrimiator, SNR=10dB The measured iput sigal frequecy is Hz, ad the error is Through the simulatio aalysis, we ca see that higher SNR meas higher measuremet accuracy, the lower SNR meas lower measuremet accuracy. Uder low SNR(10dB) coditios, whe f 0.3 k H z,the PLL ca still accomplish capture i a relatively short period of time. Phase error fluctuates up ad dow i the Copyright 2014 SERSC 33

4 Advaced Sciece ad Techology Letters zero poit because of the high oise. The SNR is greatly improved through PLL, this illustrates that the phase-locked loop has a high ability to filter out the oise Phase-locked trackig for CW pulse sigal The simulatio is show i Fig. 6. I the figure the iput sigal is show i dotted lie, ad the output sigal after phase-locked loop trackig is show i solid lie. Fig.6. Phase-locked trackig for CW pulse sigal The errors of three pulse frequecy measured through simulatio respectively is Hz Hz Hz. The simulatio results show that CW pulse sigal ca be well tracked by phaselocked loop, ad the measuremet precisio of the iput CW pulse frequecy is high. 3 Coclusio Based o the theory of Phase-locked loop, the PLL simulatio algorithm is researched through Matlab i this paper. The simulatio results show that CW pulse sigal ca be well tracked by phase-locked loop model, ad the measuremet precisio of the iput CW pulse frequecy is high. Refereces 1. Tia Hua hua ad Zhag Haiyig, All digital phase-locked loop o digital module aalysis ad build simulatio model. Microelectroics ad computer. 2011(11). 2. Che Guo dog,zhu Miao, Cai Xu, LI Rui ad so o, a software phase locked loop ad voltage sag detectio algorithm.joural of Chia motor.2014(25). 3. Sha Chag hog,deg Guo yag,research o a e kid of Digital PLL. Joural of System Simulatio.15(4), Karimi Ghartemai,M Ziarai K, A Noliear Adaptive Filter for Olie Sigal Aalysis i Power Systems. IEEE Tras Power Delivery,2002,2(17). 34 Copyright 2014 SERSC

5 Advaced Sciece ad Techology Letters 5. Padmaabha, M. Marti,K. A CMOS aalog multi-siusoidal phase locked loop. IEEE Joural of Solid-State Circuits.vol Kurita Kozaburo, Hotta Takashi, Nakao Tetsuo, et al. PLL-based BiCMOS o-chip clock geerator for very high-speed microprocessor. IEEE Joumal of Solid-State Cicuits YamazakiM,Ohtsubo J.Optimizatio of ecrypted holograms i optical security systems.opteg. 40(1), M.Karimi-Ghartemai,M.R.Iravai.A method for sychroizatio of power electroic coverters i polluted ad variable-frequecy eviromets. IEEE Trasactios o Power Systems Kaura V,Blasko V.Operatio of a Phase Locked Loop System uder Distorted Utility Coditios. IEEE Trasactios o Idustry Applicatios Zha Chagjiag,Fitzer C,Ramachadaramurthy V K,et al.software phase-locked loop applied to dyamic voltage restore(rdvr). Proc.IEEE Power Eg Soc Witer Meetig. 11. L. Su,ad T. Kwasiewski."A 1.25-GHz 0.35-um moolithic CMOS PLL based o a multiphase rig oscillator,". IEEE Joural of Solid-State-Circuits M.Lee,M.E.Heidari,A.A.Abidi.A low-oise widebad digital phase-locked loop based o a coarse-fie time-to-digital coverter with subpico-secod resolutio. IEEE Joural of Solid State Circuits Copyright 2014 SERSC 35

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