CHAPTER 3 DIGITAL CODING OF SIGNALS


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1 CHAPTER 3 DIGITAL CODING OF SIGNALS Computers are ofte used to automate the recordig of measuremets. The trasducers ad sigal coditioig circuits produce a voltage sigal that is proportioal to a quatity we wish to measure. This sigal may be costat or it may be varyig with time. We caot directly iput this voltage ito a computer, so we use a aalog to digital coverter (ADC) to tur the voltage we wish to measure ito a iteger code which ca be hadled by the computer. Oce iside the computer the iteger code ca be used to produce a estimate of the measured voltage. This i tur ca be coverted ito the quatity that we wish to measure, e.g., temperature, acceleratio, flow rate, by usig the results of a static calibratio. I this chapter we will cocetrate o how this voltage to iteger codig is doe. We will ot go ito ay details o the hardware structure of a ADC, there are may types available from suppliers; your choice of ADC will deped o cost, speed requiremets, compatibility with the computer you are usig ad the software available to maipulate the ADC from your computer. Here, all we are iterested i is the result of the aalog to digital coversio ad how it should be iterpreted. The codigdecodig that takes place i the ADC ad computer gives rise to errors, which may be small or large compared to the true voltages depedig o how well the aalog to digital coverter is beig utilized. Below is a descriptio of some of the compoets of aalog to digital coversio; this should give you some ideas o how to use these devices effectively. A aalog to digital coverter coverts a voltage ito a bit iteger code which ca the be stored o a computer. May ADC's are set up to sample a sigal at equally spaced time itervals ad store a iteger code each time the sigal is sampled. There are may issues here. For example: Clippig Ca we covert the iteger code back to the voltage we sampled? Do we have eough iformatio to recostruct the origial sigal? What happes if the sigal voltage chages while the ADC is calculatig the iteger code? A aalog to digital coverter has a iput rage, e.g volts (uipolar), or 5 to +5 volts (bipolar). Differet ADC's have differet iput rages. You must make sure your sigal lies withi this rage. For example, for a iput rage of ± 5V, sigals greater tha 5 volts have the same codes as 5 volt sigals ad sigals less tha 5 volts will have the same codes as
2 volt sigals. That is, the ADC perceives sigal A i Figure 1 to be sigal B show i Figure 1. This pheomeo is kow as clippig. This is a highly oliear effect. Figure 1: A illustratio of sigal clippig. Voltages to Iteger Codes Havig esured that clippig will ot take place we ow eed to sample the sigal ad geerate iteger code. Sice a computer uses biary codig (1's ad 0's), oly a fiite umber of bits (biary digits) are available to represet the iput voltage. At this poit let's assume that the iteger coversio happes istataeously. So we are measurig the sigal at itervals T secods apart ad covertig the voltage to a code. Figure 2: Sigal beig sampled
3 33 The ADC subdivides the iput rage VADC mi VADC max ito ( 2 1) itervals, where is the umber of bits. Each bi is Q (VADCmax VADC mi ) /(2 1) volts wide. This is called the quatizatio iterval or resolutio of the ADC. Now some ADC's oly code positive VADC mi is coded as 0 ad VADC max is coded as 2 1. Other ADC's may code with both positive ad egative itegers so oe possible codig scheme may result i: VADC mi is coded as ( 1) 2 ad VADC max is coded as ( 1) 2 1 where is the umber of bits. Note that with this scheme 0 Volts gets coded as 0, egative voltages are coded with egative itegers ad positive voltages are coded with positive itegers. The code geerated for a particular voltage, positive itegers is: Vi comig i, for a bit ADC that oly codes (Vi VADC mi ) (2 1) code earest iteger to (1) (VADC VADC ) max mi For a bit ADC that codes both positive ad egative itegers, V i (2 1) code earest iteger. (VADC VADC ) max mi (2) Results of a static calibratio of a ADC would look like the graph show i Figure 3. This is a 4 bit uipolar ADC with a true iput rage of 0 to 7.5 volts. Notice that ay voltage betwee 0 ad 7.5 volts could be icomig to the ADC, but the computer will oly geerate 16 possible voltages correspodig to the 16 iteger codes it is possible to geerate with 4 bits. I geeral, the umber of itegers that ca be coded is 2, where is the umber of bits.
4 34 Figure 3: Static calibratio curve for a ideal aalog to digital coverter: iput rage Volts, 4 bits, positive iteger codes oly. Q = 7.5/(161) = 0.5 Volts. Max quatizatio error = Q/2 = 0.25 Volts. Codes to Voltages Oce o the computer, this code ca be tured ito a estimate of the icomig voltage, ˆV i code Q offset, where offset is the voltage correspodig to a code of 0. So for a 16 bit ADC with a true iput rage of ± 10 volts that codes oly positive itegers 20 ˆV i code 10 volts, 16 (2 1) ad for a ADC with the same characteristics except that it codes both positive ad egative itegers 20 ˆV i code, 16 (2 1) i.e., offset = 0 because a zero code correspods to 0 volts. Q Q Now ay voltage betwee Vˆ ˆ i ad Vi 2 2 would get the same code. So Q 2 is the maximum quatizatio error. Therefore we ca say that V i lies i the followig iterval. Q Vˆ i V ˆ i Vi Q/2 2
5 35 So we kow the true iput withi ± Q/2 volts. True Iput Rage vs Nomial Iput Rage I may practical ADC's the iput rage is quoted as beig ± R Volts but i fact the true iput rage is R to RQ Volts. To have +R as well as R coded would require 2 1 codes. Sice we oly have 2 codes, +R does ot get coded ad the highest voltage to be correctly coded is RQ volts. Whe calculatig Q we ca take the true spa ad divide by ( 2 1) or we ca take the omial spa ad divide by 2. Q true spa omial spa, i.e. Q 2R Q 2R (2 1) 2 (2 1) 2 Note that both calculatios give the same value for Q. Recall that the true spa equals maximum iput voltage  miimum iput voltage, ad thus the omial spa equals the omial maximum iput voltage  miimum iput voltage. (3) A 16 bit aalog to digital coverter has a omial iput rage of ±15 Volts ad codes with positive itegers oly. (a) (b) (c) What will the iteger code be if the icomig voltage is 2 Volts? What is the estimated icomig voltage calculated by the computer from the iteger code? What is the rage of icomig voltages that would receive the same code? Solutio (a) Icomig voltage VADC mi ( 2) ( 15) omial spa 30 28, where we use the omial spa of eq. (3) istead of true spa as i eq. (1). Code is the 28,399. (b) (c) Estimated voltage is: Code x Quatizatio Iterval + Offset = volts. 2 Maximum quatizatio error is half the quatizatio iterval (Q)
6 Q 30/ ad the rage of voltages with a code is: ± volts. Repeat the previous example but ow assume that the aalog to digital coverter codes positive ad egative itegers, ad the rage of iteger codes is to 2 1, where is the umber of bits i the ADC. Solutio (a) Icomig voltage omial spa 30 Code is the (b) (c) Estimated voltage is: Code Quatizatio Iterval + Offset = This is the same as i part (c) above Volts Samplig ad Aliasig Whe you sample a sigal, do you lose iformatio? If, the umber of bits i the ADC, is large, the quatizatio error will be small. So let's igore the quatizatio error, assumig that there are a large umber of bits i the ADC ad we have utilized the iput rage well whe we acquired the sigal. If we sample the sigal fast eough it is possible to use the samples to drive a digital to aalog coverter (DAC) ad, with the use of filters, recostruct the origial sigal. We eed to sample the sigal so that o iformatio is lost durig the samplig process. If this is the case the we ca recostruct the origial sigal. The recostructio process is illustrated i Figure 4a. iteger codes from the computer Digital to Aalog Coverter ZeroOrder Hold Low Pass Recostructio Filter fc 1 f 2 s Figure 4a: Sigal recostructio. So what do we mea by fast eough? It turs out that samplig the sigal at a rate over twice the highest frequecy i the sigal will esure that o iformatio is lost. Deotig the sample rate by f s ad the highest frequecy i the sigal by f highest,
7 37 sample rate,f 2 f. s highest I may cotrols applicatios, where sigals are sampled i order to use digital cotrollers, because of the characteristics of the zeroorder hold digital to aalog coverter (DAC) ad other cosideratios, people ofte choose a sample rate greater tha te times the highest frequecy i the sigal. However, here we will cocetrate o the aliasig problem, which is caused by ot samplig fast eough ad thus losig iformatio i the samplig process. If you do ot sample fast eough, you ca get a result (set of samples) that is idetical to the result of samplig aother sigal of a differet frequecy. Hece, whe you oly have the samples, you do ot kow which of the may possible sigals was sampled to produce this result. To avoid this problem you eed oly sample at a rate above twice the highest frequecy i the sigal. aalog sigal Low Pass (atialiasig) Filter Cutoff frequecy fc e.g., fc 1 f 4 s 1 f 2 s Aalog to Digital Coverter Samplig frequecy = f Hz bit iteger codes Figure 4b: Data acquisitio with atialiasig filters. s Storage Medium e.g. Computer Disk To esure that the highest frequecy i the sigal is kow, ad therefore the sample rate ca be chose correctly, lowpass filters are ofte used to filter out high frequecies before the sigal is sampled. A block diagram of this part of the measuremet system is show i Figure 4b. The lowpass filter will remove frequecies well above its cutoff frequecy ad pass frequecies well below the cutoff frequecy without affectig them greatly (see the chapter o filters ad opamps for a more detailed descriptio of filters). Whe you do ot have these filters, ofte referred to as atialiasig filters, you eed to do some checks o whether you are aliasig or ot. A typical check is to repeat the data acquisitio at differet samplig frequecies, to see if the frequecy cotet chages. This is illustrated i Figure 5a. Figure 5a: Seeig higher frequecies appear i the sigal as the sample rate is icreased. Sigal is x(t) = 10 si 187tt + 2 si 200t.
8 38 Notice that whe the samplig frequecy reaches 400 Hz, a additioal higher iput frequecy appears. A ifiite set of sie waves at differet frequecies (e.g., f 1, fs f 1, fs f 1, 2fs f 1, 2fs f 1, etc.) ca all produce the same set of samples. The pheomeo is illustrated i Figure 5b. Figure 5b: A illustratio of aliasig: two sigals producig the same samples. You ca see this mathematically: A siewave sigal, Asi 1t, sampled every T secods gives samples: Asi( 1T) = 0,1,2,... 1 The samplig rate, i.e., the umber of samples take per secod, is f s. T Now add 2 K to the argumet, for ay iteger K. This does ot alter the sample value because all you have doe is add a iteger multiple (K) of 2 to the siewave argumet. 2 Asi( 1T) Asi( 1T 2 K) Asi 1 T, T which is A si ( 1 2 Kf s)t sampled every T secods. You ca show that you get the same result if you sample Asi K2 s 1 t. Whe you plot the samples the wave will appear to be the oe with the lowest frequecy, so we say that the high frequecy compoets appear to be at a lower frequecy. I Figure 6 is show the frequecy the sigal appears to be after samplig, versus the frequecy of the origial sigal prior to samplig. So as you icrease the frequecy ad keep the sample rate costat, frequecies i the rage 0 f s/2 appear i the rage 0 f s/2, frequecies i the rage f s /2 f s appear i the rage f s /2 0, frequecies f s 3f s /2 appear as 0 f s/2 etc.
9 39 Figure 6: Relatioship betwee apparet sigal frequecy ad true sigal frequecy. If fs 100 Hz or 100 samples/secod what is the apparet frequecy of the sampled sigal, if the icomig sigal is cos(2 f2t) ad f 2 = 30 Hz, 60 Hz, 90 Hz, 140 Hz? 30 lies i the rage 0 f s/2 50 Hz, therefore sigal frequecy appears to be 30 Hz. 60 is > 50, 60 = ad therefore this sigal frequecy will appear to be 40 Hz. 90 > 50, 90 = , therefore sigal frequecy appears to be 10 Hz. 140 > 50, 140 = therefore sigal frequecy appears to be 40 Hz. Geeral rule: Express sigal's true frequecy, ftrue as: ftrue Kfs f appear f where appear f s /2 ad K is a iteger. Sigal frequecy will appear at appear f. After a sigal was sampled ad stored o a computer, a aalysis of frequecy cotet was performed. The sigal was foud to cotai compoets at 20, 40 ad 90 Hertz. The sample rate was 200 samples per secod, but ufortuately o atialiasig filters were used prior to samplig. However, it is kow that the origial sigal oly had frequecies up to 320 Hertz. List the cadidates for the origial frequecies i the sigal.
10 310 Solutio Let's take the compoets oe by oe. 20 Hz. ftrue K fs f appear ftrue K Therefore for K = 0 we have f true = 20 Hz, for K = 1 we have f true = 180 Hz or 220 Hz. For K larger tha 1 we have frequecies that are too large. So the 20 Hz compoet could have bee a 20 Hz, 180 Hz or a 220 Hz. compoet. 40 Hz. Similar logic to above, the 40 Hz compoet could have bee a 40 Hz, a 160 Hz (= ) or a 240 Hz (= ) compoet. 90 Hz. Agai the 90 Hz compoet could have bee a 90 Hz, a 110 Hz (= ) or a 290 Hz (= ) compoet. Additioally, by settig K = 2 ad takig the mius sig i the formula, this compoet could also have origially bee = 310 Hz, which is still i the rage of possible frequecies. Aperture Time A ADC takes time to come up with the correct code. The ADC geerates a biary code, coverts it to a voltage ad compares it to the voltage comig i. Whe the differece betwee the icomig voltage ad the voltage geerated from the biary code is less tha Q/2 the code is stored. Whe the differece is outside this rage, a ew biary code is geerated, coverted to a voltage ad compared with the icomig voltage. Codes are geerated util the correct oe is foud. There are may ways to come up with a sequece of codes to try, some ca be very slow. While the coversio takes place the sigal chages. This leads to a error i the code. This is illustrated i the Figure below. Figure 7: Aperture Time Errors We wish a t, the aperture time, to be small eough so that the error caused by it is less tha the quatizatio iterval. There is o poit i makig the aperture time errors much smaller tha this because the quatizatio errors will be much larger, ad reducig the aperture time error will
11 311 have little effect o the overall error. Let's assume we have a bit ADC with a omial iput rage of ±R Volts. A siewave sigal V(t) = R si 2πft is iput to the ADC, i.e., we are maximizig our usage of the ADC rage. The V, the chage i the sigal durig the coversio, is give by V dv which is approximately 2 fr cos 2 t ad so Vmax 2 frt a. ta dt 2R Also we wish V max, so that the aperture time is less tha the ADC resolutio. 2 2R 1 Hece we require, 2 frt a, which simplifies to, t a, where f is the highest 2 f 2 frequecy i the icomig sigal, ad is the umber of bits i the ADC. Note: If t a is large there will be large errors ad ot all the bits will be sigificat. Similarly, if f is very high. I questios that ask, how may bits will be sigificat if the aperture time is... ad the highest frequecy is..., you may calculate to be a umber greater tha the umber of bits i the ADC. Your aswer will the be the umber of bits i the ADC. s (1) A 12 bit ADC coverts voltages to itegers i 3 s. What is the highest icomig frequecy that you should have? f 1 1 ta Hz. (2) What is the maximum allowable aperture time for a 8 bit ADC if the maximum icomig frequecy is 1000 Hz? 1 1 ta 1.24 s. 8 f (3) If t a 10 s, f max 2Hz ad it is a 12 bit ADC. How may bits are sigificat? tf 5 a 10.2 However we oly have 12 bits, therefore all 12 bits are sigificat. (4) As above with fmax 200
12 tf 5 a , therefore, 7.3 bits are sigificat. Note: we do ot roud here to a whole umber of bits. It is traditioal to keep it as a fractio. Sample ad Hold Devices You will otice that eve for fairly low frequecies the aperture time eeds to be very small. These aperture times are difficult to achieve i practice, so we use a sample ad hold circuit. This holds the sigal costat at the desired voltage while the coversio takes place. The effect o the sigal is illustrated below: The circuitry to do this is illustrated below: Figure 8a: The effect of the sample ad hold circuit. Figure 8b: A sample ad hold circuit. Whe the switch is i positio (1), Vout follows the iput sigal. The capacitor esures that, whe the switch is i positio (2), Vout remais at a costat voltage. With a sample ad hold the aperture time errors become egligible. Always remember, whe purchasig data acquisitio boards, to ask if the ADC boards come with sample ad hold devices. It is especially importat whe you wish to make simultaeous acquisitio o a umber of chaels. Multichael acquisitio is ofte doe with a sigle ADC ad a multiplexer is used
13 313 to cycle through the chaels i sequece. If you wish to have simultaeous acquisitio o all chaels, the sample ad holds for each chael must be sychroized, so that all chaels are held costat while the iteger codes are calculated for each chael i tur. Represetatio of Itegers i Biary Itegers are stored i a computer or i digital istrumetatio as a series of 1's ad 0's. You have to uderstad which codig scheme has bee used before you ca iterpret the biary code. Let s first cosider the case whereby oly positive itegers are used. We will describe two types of code here. Positive Itegers (a) Straight biary I the base 10 system that you are familiar with, we write 175 to mea or I the biary system the colums represet powers of two: 2 0, 2 1, 2 2, 2 3,... so 175 = = ad hece Represet (31) 10 i 8 bit biary 31 = = (31) 10 ( ) 2 Note that we filled i the "blaks" with zeros. (b) Biary Coded Decimal  BCD I digital istrumets with LED's itegers are ofte stored i BCD where each digit i base 10 is stored as a 4 bit biary umber e.g. (175) 10 = ( ) BCD Sice 1 10 (0001) (0111) 2
14 314 Negative Numbers ad 510 (0101) 2 (a) Sig bit covetio Here the most sigificat bit is used to deote the sig, 0 sigifyig + ad 1 sigifyig . Note that sice we have lost oe bit to a sig oly half the umber of positive itegers ca be coded. Code 125 i 8 bit biary usig sig bit covetio. (+125) 10 = = ( ) 2 therefore (125) 10 = ( ) 2 sig bit covetio. I BCD we ca add a extra bit so that we would have 13 bits (125) 10 =( ) BCD (b) 2's complemet Whe the computer does additio ad subtractio with egative umbers the logic becomes very complicated with sig bit covetio. So umbers are ofte stored usig other covetios e.g. 2's complemet. So say we wish to store (128) 10 to (127) 10 with 8 bit biary. We store (0 127) 10 i the usual way for positive itegers usig the last 7 bits ad 0 i the most sigificat bit. We the store (1281) 10 as (128 to 255) 10 or, if you like, q gets stored as (2 8  q) so 20 gets coded as = 236. (236) 10 = = = ( ) 2 2's comp. Iterestigly eough, the most sigificat bit is still 1 if the umber is egative but the rest of the code is differet to that for sig bit covetio. Positive itegers are idetical i both covetios. A quick way of doig 2's complemet is illustrated below. (20) 10 (+20) 10 = = = ( ) 2 Startig from the least sigificat bit (the right most bit), copy dow each digit up util ad icludig the 1 st 1, givig here
15 Now switch the 1's to 0's ad 0's to 1's to get ( ) 2 as before. Usig the 2's complemet represetatio all subtractios become additios = 20 i base 10 (+12) 10 = ( ) 2 ( 32) 10 = ( ) 2 Add ( ) 2 which ideed equals (20) = 11 i base 10 (1) 10 = ( ) 2 (10) 10 = ( ) 2 Add ( ) 2 To covert back to base 10 use the same short cut. Start with the right most bit ad write dow all the digits up to ad icludig the first 1. The switch 1's to 0's ad 0's to 1's. ( ) 2  ( ) 2 =  ( ) 10 = (11) 10 Note, whe we did the additio a bit "fell off the ed". Do't worry about this. The oly cause for cocer is whe the correct aswer lies outside the rage of itegers that ca be coded with the give umber of bits. See the followig example = 132 i base 10. Note 132 caot be coded with 8 bit biary usig two's complemet for egative umbers. (127) 10 = ( ) 2 (5) 10 = ( ) 2 Add ( ) 2 Covert back to base 10. Note this is a positive umber as idicated by the leadig 0. The base 10 umber is ( ) = 124 which is ot 132, the correct aswer.
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