12. A B C A B C A B C 1 A B C A B C A B C JK-FF NETr

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2..,.,.. Flip-Flops :, Flip-Flops, Flip Flop. ( MOD)... -8 8, 7 ( ).. n Flip-Flops. n Flip-Flops : 2 n. 2 n, Modulo. (-5) -4 ( -), (-) - ( -).. / A A A 2 3 4 5 MOD-5 6 MOD-6 7 MOD-7 8 9 / A A A 2 3 4 5 6 7 8 MOD-8 9 MOD-9 MOD-.. :. (-). 2. n ( 2 n ) FF.. SR PETr / NETr ( ) ( ). 3. ( ) FF ( ). 4. FF,,,. (, FF). 5. () FF. 2. -8 -FF NETr -8 -FF NETr (,

FF ).. :. -8 ( -7). 2. 2 n = 8 n = 3 FF ( -FF NETr). 3. FF. / (..) A A + (..) + + A A FF 2 3 4 5 6 7 2. -8. FF FF ( ). (L) FF : A =, A =X A-FF =, =X -FF =, =X -FF..,,. (, ).... FF. :. A A X X X X X X X X A =. A =. A A X X X X X X X X = = A A X X X X X X X X = = 5. (...) FF. ( ). and H P A Q 4 2 P Q H P Q 2 4. FF. P Q Q Q

3. - 8 -FF. 3.,7,4,2,5,3 ( ) -FF NETr,7,4,2,5,3 ( ) -FF NETr.. /.... FF A A + + + 7 4 2 5 3 X X D D D D D D 6 D D D D D D 3.,7,4,2,5,3..,,7,4,2,5,3. 2. 2 n 7 ( 2 n ) n = 3 FF ( -FF NETr). 3. FF. 4. FF.,.,6. ( ).... FF. A A FF. A A D X X X D D X D D X A = A = A A X D X D X D X X D = = A A D X X D X D X X X D = A = 5. (...) FF. ( ). 4..,7,4,2,5,3 FLIP-FLOP 2. mod- Flip-Flops. 3., 6, 3, 7,, 2, 5 Flip- Flops. 4. MOD-8 --, State Editor..

Finite State Machine (FSM) Editor. FSM.. FileNew, 2.. L reset. q 3bits. 2. 3. FSM Editor, (S,,S8), 3. FSM Editor, VHDL,. vhd, File Export (VHDL code). -- Generated : /6/23 5:5:49 PM library IEEE use IEEE.std_logic_64.all use IEEE.std_logic_arith.all use IEEE.std_logic_unsigned.all entity SAMPLE is port ( reset: in std_logic L: in std_logic q: out std_logic_vector ( 2 downto )) end architecture SAMPLE_arch of SAMPLE is -- SYMOLI ENODED state machine: SMachine type SMachine_type is (S,S2,S3,S4,S5,S6,S7,S8) signal SMachine: SMachine_type := S begin -- concurrent signals assignments -------------------------------------------------- ----- -- Machine: SMachine -------------------------------------------------- ----- SMachine_machine: process (L) begin if reset='' then SMachine <= S elsif L'event and L = '' then -- Set default values for registered outputs/signals and for variables case SMachine is when S => q<="" if reset='' then SMachine <= S2 end if when S2 => q<="" if reset='' then SMachine <= S elsif reset=''then SMachine <= S3 end if when S3 => q<="" if reset='' then SMachine <= S elsif reset=''then SMachine <= S4 end if when S4 => q<="" if reset='' then SMachine <= S elsif reset=''then SMachine <= S5 end if when S5 => q<="" if reset='' then SMachine <= S elsif reset=''then SMachine <= S6 end if when S6 => q<="" if reset='' then SMachine <= S elsif reset=''then 4

5 SMachine <= S7 end if when S7 => q<="" if reset='' then SMachine <= S elsif reset=''then SMachine <= S8 end if when S8 => q<="" if reset='' then SMachine <= S elsif reset=''then SMachine <= S end if when others => null end case end if end process end SAMPLE_arch. Tools New Macro Wizard. 4. Macro Name, ounter. From File counter.vhd, VHDL. 5. Next, 5 TSM. Save. 6. Insert, 7. 4. U ounter 6. reset clk ounter q 7. 8. Pin us Pin Meters Voltage Pin, q 3bits.

6 H L clk k Reset 8. U ounter reset clk ounter q q. VHDL ounterb.vhd, Tools New Macro VHDL. Analysis Digital VHDL Simulation,. VHDL. bit. FSM Editor ounter File Edit Ports. 9, bits q2, q, q.. H L T H q2 q clk k L H Reset. U2 ounterb reset clk ounterb q2 q q q2 q q q2 q q L H q L. 2.m 4.m 6.m 8.m Time (s). VHDL. IF q2<='' q<='' q<='' 9. S S2 S3 S4 q2<='' q2<='' q<='' q<='' q<='' q<='' q2<='' q<='' q<='' q2<='' q<='' q<='' S5 S6 S7 S8 q2<='' q2<='' q<='' q<='' q<='' q<='' q2<='' q<='' q<='' - (-->9-->). bit (clk) 4-bit (digit). IF. temp 4 Flip-Flops 4-bit. LIRARY ieee USE ieee.std_logic_64.all

7 ENTITY counter IS PORT (clk : IN STD_LOGI digit : OUT INTEGER RANGE TO 9) END counter, 7 segment display (SSD) ARHITETURE counter OF counter IS count: PROESS(clk) VARIALE temp : INTEGER RANGE TO IF (clk'event AND clk='') THEN temp := temp + IF (temp=) THEN temp := digit <= temp END PROESS count END counter reset temp ( toy digit). temp 4-bit.. WAIT UNTIL LIRARY ieee USE ieee.std_logic_64.all ENTITY counter IS PORT (clk : IN STD_LOGI digit : OUT INTEGER RANGE TO 9) END counter ARHITETURE counter OF counter IS PROESS -- no sensitivity list VARIALE temp : INTEGER RANGE TO WAIT UNTIL (clk'event AND clk='') temp := temp + IF (temp=) THEN temp := digit <= temp END counter LIRARY ieee USE ieee.std_logic_64.all ENTITY counter IS PORT (clk, reset : IN STD_LOGI digit, digit2 : OUT STD_LOGI_VETOR (6 DOWNTO )) END counter ARHITETURE counter OF counter IS PROESS(clk, reset) VARIALE temp: INTEGER RANGE TO VARIALE temp2: INTEGER RANGE TO IF (reset='') THEN temp := temp2 := ELSIF (clk'event AND clk='') THEN temp := temp + IF (temp=) THEN temp := temp2 := temp2 + IF (temp2=) THEN temp2 := ---- D to SSD conversion: -----

ASE temp IS WHEN => digit <= "" --7E WHEN => digit <= "" --3 WHEN 2 => digit <= "" --6D WHEN 3 => digit <= "" --79 WHEN 4 => digit <= "" --33 WHEN 5 => digit <= "" --5 WHEN 6 => digit <= "" --5F WHEN 7 => digit <= "" --7 WHEN 8 => digit <= "" --7F WHEN 9 => digit <= "" --7 WHEN OTHERS => NULL END ASE ASE temp2 IS WHEN => digit2 <= "" --7E WHEN => digit2 <= "" --3 WHEN 2 => digit2 <= "" --6D WHEN 3 => digit2 <= "" --79 WHEN 4 => digit2 <= "" --33 WHEN 5 => digit2 <= "" --5 WHEN 6 => digit2 <= "" --5F WHEN 7 => digit2 <= "" --7 WHEN 8 => digit2 <= "" --7F WHEN 9 => digit2 <= "" --7 WHEN OTHERS => NULL END ASE END counter FOR/LOOP: FOR i IN TO 5 LOOP x(i) <= enable AND w(i+2) y(, i) <= w(i) END LOOP FOR/LOOP ( GENERATE),... FOR I IN TO HOIE LOOP, HOIE ( ),. WHILE/LOOP: WHILE (i < ) LOOP WAIT UNTIL clk'event AND clk='' (other statements) END LOOP EXIT:, EXIT, (, LOOP ). : FOR i IN data'range LOOP ASE data(i) IS WHEN '' => count:=count+ WHEN OTHERS => EXIT END ASE END LOOP NEXT: NEXT LOOP i=skip: FOR i IN TO 5 LOOP NEXT WHEN i=skip -- jumps to next iteration (...) END LOOP arry Ripple Adder generic, bits. 8bit. FOR/LOOP, IF. --Solution : Generic, with VETORS LIRARY ieee USE ieee.std_logic_64.all ENTITY adder IS GENERI (length : INTEGER := 8) PORT ( a, b: IN STD_LOGI_VETOR (length- DOWNTO ) cin: IN STD_LOGI s: OUT STD_LOGI_VETOR (length- DOWNTO ) cout: OUT STD_LOGI) END adder ARHITETURE adder OF adder IS PROESS (a, b, cin) 8

9 VARIALE carry : STD_LOGI_VETOR (length DOWNTO ) carry() := cin FOR i IN TO length- LOOP s(i) <= a(i) XOR b(i) XOR carry(i) carry(i+) := (a(i) AND b(i)) OR (a(i) AND carry(i)) OR (b(i) AND carry(i)) END LOOP cout <= carry(length) END adder --Solution 2: non-generic, --with INTEGERS LIRARY ieee USE ieee.std_logic_64.all ENTITY adder IS PORT ( a, b: IN INTEGER RANGE TO 255 c: IN STD_LOGI s: OUT INTEGER RANGE TO 255 c8: OUT STD_LOGI) END adder ARHITETURE adder OF adder IS PROESS (a, b, c) VARIALE temp : INTEGER RANGE TO 5 IF (c='') THEN temp:= ELSE temp:= temp := a + b + temp IF (temp > 255) THEN c8 <= '' temp := temp---256 ELSE c8 <= '' s <= temp END adder (ad clocking) () ( ). (.. PLDs) flip-flop. «signal does not hold value after clock edge». ( ). : PROESS (clk) IF(clk'EVENT AND clk='') THEN counter <= counter + ELSIF(clk'EVENT AND clk='') THEN counter <= counter +...,, counter.,. EVENT. IF(clk'EVENT AND clk=''), IF(clk'EVENT), (.. AND clk=') : clock not locally stable.,. : PROESS (clk) IF(clk'EVENT) THEN counter := counter +... PROESS clk,.,,.,,.,., PROESS,... : PROESS (clk) counter := counter +...

counter clk ( ), «ignored unnecessary pin clk».,,.,. PROESS (clk) IF(clk'EVENT AND clk='') THEN x <= d ---------------------- PROESS (clk) IF(clk'EVENT AND clk='') THEN y <= d VARIALE SIGNAL -7. VARIALE. SIGNAL. : --Solution : With a VARIALE ENTITY counter IS PORT ( clk, rst: IN IT count: OUT INTEGER RANGE TO 7) END counter ARHITETURE counter OF counter IS PROESS (clk, rst) VARIALE temp: INTEGER RANGE TO 7 IF (rst='') THEN temp:= ELSIF (clk'event AND clk='') THEN temp := temp+ count <= temp END counter VARIALE. (clk). : -- Solution 2: With SIGNALS only ENTITY counter IS PORT ( clk, rst: IN IT count: UFFER INTEGER RANGE TO 7) END counter ARHITETURE counter OF counter IS PROESS (clk, rst) IF (rst='') THEN count <= ELSIF (clk'event AND clk='') THEN count <= count + END counter 2, SIGNALS.,, count UFFER, ( ). SIGNAL VARIALE. std_logic_64 STD_LOGI. flipflops ( 3bit count). 4bit 4bit..

IF lear = '' THEN value <= (OTHERS => '') -- 4-bit vector of, same as "" ELSIF (lock'event AND lock='') THEN IF ount = '' THEN value <= value + Q <= value END ehavioral - lear ount VHDL. USE IEEE.STD_LOGI_UNSIGNED.ALL STD_LOGI_VETOR. value. clear, value OTHERS =>., count, value. count Q Q<=value, PROESS. LIRARY IEEE USE IEEE.STD_LOGI_64.ALL USE IEEE.STD_LOGI_UNSIGNED.ALL -- need this to -- add STD_LOGI_VETORs ENTITY counter IS PORT ( lock: IN STD_LOGI lear: IN STD_LOGI ount: IN STD_LOGI Q : OUT STD_LOGI_VETOR(3 DOWNTO )) END counter ARHITETURE ehavioral OF counter IS SIGNAL value: STD_LOGI_VETOR(3 DOWNTO ) PROESS (lock, lear) -.. lear ount Down VHDL. LIRARY IEEE USE IEEE.STD_LOGI_64.ALL ENTITY udcounter IS PORT ( lock: IN STD_LOGI

lear: IN STD_LOGI ount: IN STD_LOGI Down: IN STD_LOGI Q: OUT INTEGER RANGE TO 5) END udcounter ARHITETURE ehavioral OF udcounter IS PROESS (lock, lear) VARIALE value: INTEGER RANGE TO 5 IF (lear = '') THEN value := ELSIF (lock'event AND lock='') THEN IF (ount = '') THEN IF (Down = '') THEN value := value + ELSE value := value - Q <= value END ehavioral 2 lear Load ount Down VHDL. - -...

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