Step : Create Dependency Graph for Data Path Step b: 8-way Addition? So, the data operations are: 8 multiplications one 8-way addition Balanced binary

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1 RTL Design RTL Overview Gate-level design is now rare! design automation is necessary to manage the complexity of modern circuits only library designers use gates automated RTL synthesis is now almost universal RTL = Register Transfer Level The design is perceived as a number of registers with transfer functions which transform data as it passes from one register to another this is a synchronous methodology chosen as the methodology for input to synthesis fn load sel Controller Transfer Function Register Data Path ELEC07 - RTL ELEC07 - RTL RTL Design Steps Example There are typically 8 steps in the RTL design process. Create a Dependency Graph for the Data Path. Determine the widths of the data paths. Decide what resources to provide. Allocate operations to resources and schedule them. Allocate registers to intermediate results 6. Share registers 7. Design the controller 8. Design the reset/initialisation mechanism The order of these steps may vary and may be iterated Scalar-product calculator Not a realistic design, but shows the elements of RTL design The example will work on 8 element vectors. ELEC07 - RTL ELEC07 - RTL

perceived as a number of registers with transfer functions which transform data as it passes from one register to another this is a synchronous methodology chosen as the methodology for input to

2 Step : Create Dependency Graph for Data Path Step b: 8-way Addition? So, the data operations are: 8 multiplications one 8-way addition Balanced binary tree Skewed binary tree ELEC07 - RTL ELEC07 - RTL 6 Step c: Identify and Make Unique Data Paths Create what is known as the Single Assignment Form p0 := a0 b0; p := a b; p := a b;... z := p0 p; z := z p; z := z p;... z := z6 p7; Each variable assigned only once Each statement uses just one operator Create new intermediate variables to achieve this Step : Determine Data Path Widths In most cases, this is defined for I/O as part of the specification. The designer typically then has to decide on internal data path widths. In this case we ll assume the specification: Input is 8-bit s-complement Output is 6-bit s-complement To achieve this precision, internal paths must be 6-bit s-complement Precision of Operations: all multiplications are 8-bit input, 6-bit the addition is 6-bit input, 6-bit ELEC07 - RTL 7 ELEC07 - RTL 8

as the Single Assignment Form p0 := a0 b0; p := a b; p := a b;... z := p0 p; z := z p; z := z p;.

3 Step : Choose Resources to Provide Step : Allocate/Schedule Operations As a first solution, target a minimum-area implementation one multiplier, 8-bit inputs, 6-bit one adder, 6-bit inputs, 6-bit These resources will be shared remember that the original algorithm requires the following operations: eight multiplications seven additions This stage of the design determines which operations are to be performed by which resources at which time Allocation which resource Scheduling what time (i.e. which clock cycle) Allocation for this example is trivial all additions are allocated to the adder all multiplications are allocated to the multiplier Scheduling has many permutations it doesn t matter what order multiplications are performed it doesn t matter what order additions are performed addition is associative and commutative ELEC07 - RTL 9 ELEC07 - RTL 0 Step b: Allocate/Schedule Operations Step c: Simplify Schedule mult add mult add a0 b0 p0 - a0 b0 p0 0 p0 z0 a b p p0 p z a b p z0 p z a b p z p z a b p z p z a b p z p z a b p z p z a b p z p z a b p z p z 6 a b p z p z 6 a b p z p z 7 a6 b6 p6 z p6 z6 7 a6 b6 p6 z p6 z6 8 a7 b7 p7 z6 p7 z 8 a7 b7 p7 z6 p7 z ELEC07 - RTL ELEC07 - RTL

4 Step : Allocate registers to intermediate results Every variable in the scheduling that is generated in one cycle and used in another must be registered. The schedule proposed only requires s z0 z to be registered, not the products: Step 6: Share Registers A register can be shared between variables if their lifetimes do not intersect. z0 z a0 b0 p0 0 p0 z0 z a b p z0 p z z However, the schedule does assume that a multiply-accumulate can be done in one clock cycle z 6 z 7 z6 8 z ELEC07 - RTL ELEC07 - RTL Step 6b: Simplify Registers Design so Far mult add The data path design is now complete: a0 b0 p0 0 p0 z a b p z p z a b p z p z a b p a b p z p z z p z mult add z 6 a b p z p z 7 a6 b6 p6 z p6 z 8 a7 b7 p7 z p7 z ELEC07 - RTL ELEC07 - RTL 6

z0 z a0 b0 p0 0 p0 z0 z a b p z0 p z z However, the schedule does assume that a multiply-accumulate can be done in one clock cycle z 6 z 7 z6 8 z ELEC07 - RTL ELEC07 - RTL Step 6b:

5 Step 7: Design the controller Step 7b: Design the Controller The controller is responsible for: routing operation inputs to resource inputs at the scheduled cycle enabling registers to store intermediate results In this case the controller becomes a simple -bit counter to control the muxes The register is always enabled a mux b mux zero mux register select a0 select b0 select 0 load add select a select b load add =0 select a select b load add select a select b load add select a select b load add 6 select a select b load add 7 select a6 select b6 load add 8 select a7 select b7 load add ELEC07 - RTL 7 ELEC07 - RTL 8 Step 8: Design Reset Mechanism VHDL Description Most systems require a reset mechanism This may be synchronous or asynchronous this will be in the specification Most RTL designs are reset by resetting the controller The controller then resets the data path (as in this example) In this example, the reset simply puts the counter in its start state (count = 0) reset clear library ieee; use ieee.std_logic_6.all; use ieee.numeric_std.all; package cross_product_types is subtype sig8 is signed (7 downto 0); subtype sig6 is signed ( downto 0); type sig8_vector is array (natural range <>) of sig8; end; library ieee; use ieee.std_logic_6.all; use ieee.numeric_std.all; use work.cross_product_types.all; entity cross_product is port (a, b : in sig8_vector(7 downto 0); ck, reset: in std_logic; z : out sig6); end; architecture RTL of cross_product is signal i : unsigned( downto 0); signal ai, bi : sig8; signal product, add_in, sum, accumulator : sig6; begin control: process (ck) begin if ck'event and ck = '' then if reset = '' then i <= "000"; else i <= i ; end if; end if; end process; a_mux: ai <= a(i); b_mux: bi <= b(i); z_mux: add_in <= X"0000" when i = 0 else accumulator; multiply: product <= ai bi; add: sum <= product add_in; process (ck) begin if ck'event and ck = '' then accumulator <= sum; end if; end process; : z <= accumulator; end; ELEC07 - RTL 9 ELEC07 - RTL 0

select a select b load add =0 select a select b load add select a select b load add select a select b load add 6 select a select b load add 7 select a6 select b6 load add 8 select a7 select b7 load

6 More Complex Schedules Single Assignment Form e.g. Zwolinski p97 (simplified) for order = input_sum := input; for j in 0 to order- loop input_sum := input_sum delay(j) ceoffb(j); end loop; _sum := input_sum coeffa(order); for k in 0 to order loop _sum := _sum delay(k) coeffa(k); end loop; := _sum; input_sum := input; input_sum := input_sum delay(0) ceoffb(0); _sum := input_sum coeffa(); _sum := _sum delay(0) coeffa(0); _sum := _sum delay() coeffa(); := _sum; ELEC07 - RTL input_sum := input; input_sum := input_sum delay(0) ceoffb(0); _sum := input_sum coeffa(); _sum := _sum delay(0) coeffa(0); _sum := _sum delay() coeffa(); := _sum; adds multiplies p0 := delay(0) ceoffb(0); s0 := input p0; s := s0 coeffa(); p := delay(0) coeffa(0); s := s p; p := delay() coeffa(); := s p; ELEC07 - RTL Data Dependency Graph ASAP Schedule delay(0) coeffb(0) input coeffa() coeffa(0) delay() delay(0) coeffb(0) input coeffa() coeffa(0) delay() p0 p p adder multipliers s0 s s ELEC07 - RTL ELEC07 - RTL

7 ALAP Schedule Resource Constrained Schedule delay(0) coeffb(0) input coeffa() coeffa(0) delay() delay(0) coeffb(0) input coeffa() coeffa(0) delay() adder multipliers adder multiplier ELEC07 - RTL ELEC07 - RTL 6 Allocation Allocate Registers delay(0) coeffb(0) input coeffa() coeffa(0) delay() delay(0) coeffb(0) input coeffa() coeffa(0) delay() mpy mpy adder multipliers R R R R R add R6 R7 R8 R9 R0 R ELEC07 - RTL 7 ELEC07 - RTL 8

Allocation Allocate Registers delay(0) coeffb(0) input coeffa() coeffa(0) delay() delay(0) coeffb(0) input

8 Share Registers Data Path delay(0) coeffb(0) input coeffa() coeffa(0) delay() delay(0) R coeffb(0) coeffa() delay(0) coeffa(0) coeffa() delay() R R6 R9 input R7 R0 R R Registers mux mpy mux mux mpy mux mux add mux6 R R R R/R6 R/R R/R9/ R R6 R7 R8 R/R8 R9 R0 R7/R0 R ELEC07 - RTL 9 ELEC07 - RTL 0 Controller State Machine mux = 0 mux = 0 mux = 0 mux = 0 enable R enable R mux = 0 mux6 = 0 mux = mux = enable R enable R enable R mux = mux = enable R6 enable R7 enable R8 mux = mux6 = enable R9 enable R0 mux = mux6 = enable R ELEC07 - RTL

R7/R0 R ELEC07 - RTL 9 ELEC07 - RTL 0 Controller State Machine mux = 0 mux = 0 mux = 0 mux = 0 enable R enable R mux = 0 mux6 = 0 mux

ECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)

ECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process) ECE 3401 Lecture 7 Concurrent Statements & Sequential Statements (Process) Concurrent Statements VHDL provides four different types of concurrent statements namely: Signal Assignment Statement Simple Assignment