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1 Section 8. Counters HOW MUCH Once you understand the capabilities of different Ps, you might ask, Why not ES I COS? just always use the most capable P available? For example, even if a circuit fits in a 0-pin V8, why not specify the slightly larger, -pin 0V8 so that spare inputs are available in case of trouble? And, once you ve specified a 0V8, why not use the somewhat more capable V0 which comes in the same -pin package? In the real world of product design and engineering, the constraint is cost. Otherwise, the argument of the previous paragraph could be extended ad nauseum, using CPs and FPGAs with even more capability (see \chapref{cpsfpgas). Like automobiles and fine wines, digital devices such as Ps, CPs, and FPGAs are not always priced proportionally to their capabilities and benefits. In particular, the closer a device s capability is to the bleeding edge, the higher the premium you can expect to pay. hus, when selecting a devices to realize a design, you must evaluate many trade-offs. For example, a high-density, high-cost CP or FPGA may allow a design to be realized in a single device whose internal functions are easily changed if need be. On the other hand, using two or more lower density Ps, CPs, or FPGAs may save component cost but increase board area and power consumption, while making it harder to change the design later (since the device interconnections must be fixed when the board is fabricated). What this goes to show is that overall cost must always be considered along with design elegance and convenience to create a successful (i.e., profitable) product. And minimizing the cost of a product usually involves a plethora of common-sense economic and engineering considerations that are far removed from the turn-the-crank, algorithmic gate minimization methods of Chapter. 8. Counters he name counter is generally used for any clocked sequential circuit whose counter state diagram contains a single cycle, as in Figure 8-. he modulus of a modulus counter is the number of states in the cycle. A counter with m states is called a modulo-m counter or, sometimes, a divide-by-m counter. A counter with a nonpower-of- modulus has extra states that are not used in normal operation. divide-by-m counter modulo-m counter Figure 8- S S General structure S of a counter s state diagram a single cycle. Sm S S

2 Chapter 8 Sequential Logic Design Practices Q Q0 Q Q Q Q Q Q Q Figure 8- A -bit binary Q Q ripple counter. Q n-bit binary counter Probably the most commonly used counter type is an n-bit binary counter. Such a counter has n flip-flops and has n states, which are visited in the sequence 0,,,, n, 0,,. Each of these states is encoded as the corresponding n-bit binary integer. 8.. Ripple Counters An n-bit binary counter can be constructed with just n flip-flops and no other components, for any value of n. Figure 8- shows such a counter for n =. Recall that a flip-flop changes state (toggles) on every rising edge of its clock input. hus, each bit of the counter toggles if and only if the immediately preceding bit changes from to 0. his corresponds to a normal binary counting sequence when a particular bit changes from to 0, it generates a carry to the ripple counter next most significant bit. he counter is called a ripple counter because the carry information ripples from the less significant bits to the more significant bits, one bit at a time. 8.. Synchronous Counters Although a ripple counter requires fewer components than any other type of binary counter, it does so at a price it is slower than any other type of binary counter. In the worst case, when the most significant bit must change, the output is not valid until time n t pq after the rising edge of, where t pq is the propagation delay from input to output of a flip-flop. synchronous counter A synchronous counter connects all of its flip-flop clock inputs to the same common signal, so that all of the flip-flop outputs change at the same time, after only t pq ns of delay. As shown in Figure 8-8, this requires the use of flip-flops with enable inputs; the output toggles on the rising edge of if and only if EN is asserted. Combinational logic on the EN inputs determines which, if any, flip-flops toggle on each rising edge of.

3 Section 8. Counters CNEN EN Q Q0 EN Q Q EN Q Q Figure 8-8 EN Q Q A synchronous -bit binary counter with serial enable logic. As shown in Figure 8-8, it is also possible to provide a master countenable signal CNEN. Each flip-flop toggles if and only if CNEN is asserted and all of the lower-order counter bits are. Like the binary ripple counter, a synchronous n-bit binary counter can be built with a fixed amount of logic per bit in this case, a flip-flop with enable and a -input AND gate. he counter structure in Figure 8-8 is sometimes called a synchronous synchronous serial serial counter because the combinational enable signals propagate serially from counter the least significant to the most significant bits. If the clock period is too short, there may not be enough time for a change in the counter s LSB to propagate to the MSB. his problem is eliminated in Figure 8- by driving each EN input with a dedicated AND gate, just a single level of logic. Called a synchronous synchronous parallel parallel counter, this is the fastest binary counter structure. counter CNEN EN Q Q0 Figure 8- A synchronous -bit binary counter with parallel enable logic EN Q Q EN Q Q EN Q Q

4 Chapter 8 Sequential Logic Design Practices 8.. MSI Counters and Applications x he most popular MSI counter is the x, a synchronous -bit binary counter with active-low load and clear inputs, with the traditional logic symbol shown in Figure 8-0. Its function is summarized by the state table in able 8-, and its internal logic diagram is shown in Figure 8-. x he uses D flip-flops rather than flip-flops internally to facilitate the load and clear functions. Each D input is driven by a -input multiplexer consisting of an OR gate and two AND gates. he multiplexer output is 0 if the _L input is asserted. Otherwise, the top AND gate passes the data input (A, B, C, or D) to the output if _L is asserted. If neither _L nor _L is asserted, the 0 bottom AND gate passes the output of an XNOR gate to the multiplexer output. able 8- State table for a x -bit binary counter. D QD Inputs Current State Next State _L _L QD QC QB QA QD QC QB QA Figure 8-0 raditional logic 0 x x x x x x x symbol for 0 x x x x x x D C B A the x. 0 x x x x x QD QC QB QA x 0 x x x x QD QC QB QA

5 Section 8. Counters () () _L () _L () A () D Q QA CK Q () B () D Q QB CK Q () C () D Q QC CK Q () D () D Q QD CK Q () () (0) Figure 8- Logic diagram for the x synchronous -bit binary counter, including pin numbers for a standard -pin dual in-line package.

6 8 Chapter 8 Sequential Logic Design Practices x + V R RPU 0 QA QB QC Figure 8- D QD QD Connections for the x to operate in a free-running mode. U he XNOR gates perform the counting function in the. One input of each XNOR is the corresponding count bit (QA, QB, QC, or QD); the other input is, which complements the count bit, if and only if both enables and are asserted and all of the lower-order count bits are. he ( ripple carry out ) signal indicates a carry from the most significant bit position, and is when all of the count bits are and is asserted. Even though most MSI counters have enable inputs, they are often used in free-running counter a free-running mode in which they are enabled continuously. Figure 8- shows the connections to make a operate in this way, and Figure 8- shows the resulting output waveforms. Notice that starting with QA, each signal has half the frequency of the preceding one. hus, a free-running can be used as a divide-by-, -, -8, or - counter, by ignoring any unnecessary high-order output bits. Note that the is fully synchronous; that is, its outputs change only on the rising edge of. Some applications need an asynchronous clear function, Figure 8- Clock and output waveforms for a free-running divide-by- counter. QA QB QC QD COUN

7 Section 8. Counters QA QB QC QD COUN Figure 8- Clock and output waveforms for a free-running divide-by-0 counter. as provided by the x. he has the same pinout as the, but its x _L input is connected to the asynchronous clear inputs of its flip-flops. he x0 and x are more variations with the same pinouts and x0 general functions as the and, except that the counting sequence is x modified to go to state 0 after state. In other words, these are modulo-0 counters, sometimes called decade counters. Figure 8- shows the output decade counter waveforms for a free-running 0 or. Notice that although the QD and QC outputs have one-tenth of the frequency, they do not have a 0% duty cycle, and the QC output, with one-fifth of the input frequency, does not have a constant duty cycle. We ll show the design of a divide-by-0 counter with a 0% duty-cycle output later in this subsection. Although the is a modulo- counter, it can be made to count in a modulus less than by using the _L or _L input to shorten the normal counting sequence. For example, Figure 8- shows one way of using the as a modulo- counter. he output, which detects state, is used to force x Figure 8- Using the x as RPU a modulo- counter with the counting sequence,,,, 0,,. + V Q0 Q Q R D QD Q x0 CN U CN_L U

8 00 Chapter 8 Sequential Logic Design Practices x RPU + V R 0 Q0 Q Figure 8- Q Using the x as D QD Q a modulo- counter x00 with the counting sequence 0,,, U, 0, 0,,. CN0_L U the next state to, so that the circuit will count from to and then start at again, for a total of states per counting cycle. A different approach for modulo- counting with the is shown in Figure 8-. his circuit uses a NAND gate to detect state 0 and force the next state to 0. Notice that only a -input gate is used to detect state 0 (binary 00). Although a -input gate would normally be used to detect the condition CN0 = Q Q Q Q0, the -input gate takes advantage of the fact that no other state in the normal counting sequence of 0 0 has Q = and Q =. In general, to detect state N in a binary counter that counts from 0 to N, we need to AND only the state bits that are in the binary encoding of N. here are many other ways to make a modulo- counter using a. he choice of approach one of the preceding or a combination of them (as in Exercise 8.) depends on the application. As another example, in Section.0 we promised to show you how to build a circuit that counts in the x Figure 8- A x used as an excess- decimal counter. 0 + V R Q0 RPU Q Q D QD Q x00 U U SXX_L

9 Section 8. Counters 0 Q0 Q Q Q COUN 8 0 Figure 8-8 iming waveforms for the used as an excess- decimal counter. excess- decimal code, shown in able - on page. Figure 8- shows the connections for a to count in the excess- sequence. A NAND gate detects state 00 and forces 00 to be loaded as the next state. Figure 8-8 shows the resulting timing waveforms. Notice that the Q output has a 0% duty cycle, which may be desirable for some applications. A binary counter with a modulus greater than can be built by cascading xs. Figure 8- shows the general connections for such a counter. he, _L, and _L inputs of all the s are connected in parallel, so that all of them count or are cleared or loaded at the same time. A master countenable (CNEN) signal is connected to the low-order. he output is asserted if and only if the low-order is in state and CNEN is asserted; is connected to the enable inputs of the high-order. hus, both the carry information and the master count-enable ripple from the output of one Figure 8- General cascading connections for x-based counters. x x RESE_L LOAD_L CNEN 0 0 D0 Q0 D Q D Q D Q D Q D Q D D QD Q D D QD Q 8 U U

10 0 Chapter 8 Sequential Logic Design Practices -bit counter stage to the next. Like the synchronous serial counter of Figure 8-8, this scheme can be extended to build a counter with any desired number of bits; the maximum counting speed is limited by the propagation delay of the ripple carry signal through all of the stages (but see Exercise 8.). Even experienced digital designers are sometimes confused about the difference between the and enable inputs of the and similar counters, since both must be asserted for the counter to count. However, a glance at the s internal logic diagram, Figure 8- on page, shows the difference quite clearly goes to the ripple carry output as well. In many applications, this distinction is important. For example, Figure 8-0 shows an application that uses two s as a modulo- counter that counts from to. he MAXCN output detects state and stops the counter until GO_L is asserted. When GO_L is asserted, the counter is reloaded with and counts up to again. (Note that the value of GO_L is relevant only when the counter is in state.) o keep the counter x Figure V Using xs as a modulo- counter R with the counting sequence,,, 0,,,. RPU Q0 Q Q D QD Q U RESE_L x00 GO_L CNEN x U x00 RELOAD_L U 0 Q Q Q D QD Q MAXCN U

11 Section 8. Counters 0 stopped, MAXCN must be asserted in state even while the counter is stopped. herefore, the low-order counter s input is always asserted, its output is connected to the high-order input, and MAXCN detects state even if CNEN is not asserted (compare with the behavior of 8 in Figure 8-). o enable counting, CNEN is connected to the inputs in parallel. A NAND gate asserts RELOAD_L to go back to state only if GO_L is asserted and the counter is in state. Another counter with functions similar to x s is the x, whose x logic symbol is shown in Figure 8-. One difference in the is that its carry output and enable inputs are active low. More importantly, the is an up/ up/down counter down counter; it counts in ascending or descending binary order depending on the value of an input signal, UP/DN. he counts up when UP/DN is and x down when UP/DN is 0. UP/DN 8.. Decoding Binary-Counter States A binary counter may be combined with a decoder to obtain a set of -out-of-mcoded signals, where one signal is asserted in each counter state. his is useful 0 when counters are used to control a set of devices where a different device is enabled in each counter state. In this approach, each output of the decoder enables a different device. D QD Figure 8- shows how a x wired as a modulo-8 counter can be combined with a x8 -to-8 decoder to provide eight signals, each one representing a counter state. Figure 8- shows typical timing for this circuit. Figure 8- Each decoder output is asserted during a corresponding clock period. Logic symbol for the x up/down Notice that the decoder outputs may contain glitches on state transitions counter. where two or more counter bits change, even though the outputs are glitch free and the 8 does not have any static hazards. In a synchronous counter like the, the outputs don t change at exactly the same time. More important, decoding glitches + V RPU Figure 8- x R x8 A modulo-8 binary counter and decoder. Y0 S0_L G Y S_L GA Y S_L GB 0 Y S_L Q Y S_L A 0 Q Y S_L B Q Y S_L C Y S_L D QD U U

12 0 Chapter 8 Sequential Logic Design Practices _L S0_L S_L S_L S_L S_L S_L S_L S_L COUN 0 0 Figure 8- iming diagram for a modulo-8 binary counter and decoder, showing decoding glitches. multiple signal paths in a decoder like the 8 have different delays; for example, the path from B to Y_L is faster than the path from A to Y_L. hus, even if the input changes simultaneously from 0 to 00, the decoder may behave as if the input were temporarily 00, and the Y_L output may have a glitch. In the present example, it can be shown that the glitches can occur in any realization of function hazard the binary decoder function; this problem is called a function hazard. In most applications, the decoder output signals portrayed in Figure 8- would be used as control inputs to registers, counters, and other edge-triggered devices (e.g., EN_L in a x, _L in a x, or _L in a x). In such a case, the decoding glitches in the figure are not a problem, since they occur after the clock tick. hey are long gone before the next tick comes along, when the decoder outputs are sampled by other edge-triggered devices. However, the glitches would be a problem if they were applied to something like the S_L or R_L inputs of an S-R latch. Likewise, using such potentially glitchy signals as clocks for edge-triggered devices is a definite no-no. If necessary, one way to clean up the glitches in Figure 8- is to connect the 8 outputs to another register that samples the stable decoded outputs on the next clock tick, as shown in Figure 8-. Notice that the decoded outputs have been renamed to account for the -tick delay through the register. However, once you decide to pay for an 8-bit register, a less costly solution is to use an 8-bit ring counter, which provides glitch-free decoded outputs directly, as we ll show in Section 8...

13 Section 8. Counters 0 RPU + V x x R x8 OE S0_L Y0 D Q RS_L G S_L Y D Q RS_L GA S_L Y D Q RS_L GB S_L 8 0 Y D Q RS_L S_L Q Y D Q RS_L A 0 S_L Q Y D Q RS_L B S_L Q Y D Q RS_L C S_L 8 Y 8D 8Q RS0_L D QD U U U Figure 8- A modulo-8 binary counter and decoder with glitch-free outputs. 8.. Counters in ABEL and Ps Binary counters are good candidates for ABEL- and P-based design, for several reasons: A large state machine can often be decomposed into two or more smaller state machines where one of the smaller machines is a binary counter that keeps track of how long the other machine should stay in a particular state. his may simplify both the conceptual design and the circuit design of the machine. Many applications require almost-binary-modulus counters with special requirements for initialization, state detection, or state skipping. For example, a counter in an elevator controller may skip state. Instead of using an off-the-shelf binary counter and extra logic for the special requirements, a designer can specify exactly the required functions in an ABEL program. Most standard MSI counters have only bits, while a single -pin P can be used to create a binary counter with up to 0 bits. he most popular MSI counter is the x -bit binary counter, shown in Figure 8- on page. A glance at this figure shows that the excitation logic for this counter isn t exactly simple, especially considering its use of XNOR gates. Nevertheless, ABEL provides a very simple way of defining counter behavior, which we describe next. Recall that ABEL uses the + symbol to specify integer addition. When two sets are added with this operator, each is interpreted as a binary number; the rightmost set element corresponds to the least significant bit of the number. hus, the function of a x can be specified by the ABEL program in able 8-. When the counter is enabled, is added to the current state.

14 0 Chapter 8 Sequential Logic Design Practices able 8- ABEL program for a x-like -bit binary counter. module ZX title '-bit Binary Counter' " Input pins,!,!,, pin; A, B, C, D pin; " Output pins QA, QB, QC, QD pin istype 'reg'; pin istype 'com'; " Set definitions INPU = [D, C, B, A]; COUN = [QD, QC, QB, QA]; equations COUN. = ; COUN :=! & ( & INPU #! & ( & ) & (COUN + ) #! &!( & ) & COUN); = (COUN == [,,,]) & ; end ZX able 8- MInimized equations for the -bit binary counter in page 0. QA := ( & & & &!QA QD := ( & & & &!QD & QC & QB & QA # & &! & QA # &! & D # & &! & QA # & & QD &!QB # &! & A); # & & QD &!QC # & &! & QD QB := ( & & & &!QB & QA # & &! & QD # & & QB &!QA # & & QD &!QA); # & &! & QB # & &! & QB = ( & QD & QC & QB & QA); # &! & B); QC := ( & & & &!QC & QB & QA # & & QC &!QA # & & QC &!QB # & &! & QC # & &! & QC # &! & C);

15 Section 8. Counters 0 able 8- shows the minimized logic equations that ABEL generates for the -bit counter. Notice that each more significant output bit requires one more product term. As a result, the size of counters that can be realized in a V8 or even a 0V8 is generally limited to five or six bits. Other devices, including the X-series Ps and some CPs, contain an XOR structure that can realize larger counters without increasing product-term requirements. Designing a specialized counting sequence in ABEL is much simpler than adapting a standard binary counter. For example, the ABEL program in able 8- can be adapted to count in excess- sequence (Figure 8-8 on page 0) by changing the equations as follows: COUN :=! & ( & INPU #! & ( & ) & ((COUN==) & ) # ((COUN!=) & (COUN + )) #! &!( & ) & COUN); = (COUN == ) & ; Ps can be cascaded to obtain wider counters, by providing each counter stage with a carry output that indicates when it is about to roll over. here are two basic approaches to generating the carry output: Combinational. he carry equation indicates that the counter is enabled combinational carry and is currently in its last state before rollover. For a -bit binary up output counter, we have COU = CNEN & Q & Q & Q & Q & Q0; Since CNEN is included, this approach allows carries to be rippled through cascaded counters by connecting each COU to the next CNEN. Registered. he carry equation indicates that the counter is about to enter registered carry output its last state before rollover. hus, at the next clock tick, the counter enters this last state and the carry output is asserted. For a -bit binary up counter with load and clear inputs, we have COU :=! &! & CNEN & Q & Q & Q & Q &!Q0 #! *! *!CNEN & Q & Q & Q & Q & Q0 #! & & D & D & D & D & D0; he second approach has the advantage of producing COU with less delay than the combinational approach. However, external gates are now required between stages, since the CNEN signal for each stage should be the logical AND of the master count-enable signal and the COU outputs of all lower-order counters. hese external gates can be avoided if the higher-order counters have multiple enable inputs.

16 08 Chapter 8 Sequential Logic Design Practices 8.. Counters in VHDL Like ABEL, VHDL allows counters to be specified fairly easily. he biggest challenge in VHDL, with its strong type checking, is to get all of the signal types defined correctly and consistently. able 8- is a VHDL program for a x-like binary counter. Notice that the program uses the IEEE.std_logic_arith.all library, which includes the UNSIGNED type, as we described in Section.. on page 8. his library includes definitions of + and - operators that perform unsigned addition and subtraction on UNSIGNED operands. he counter program declares the counter input and output as UNSIGNED vactors and uses + to increment the counter value as required. In the program, we defined an internal signal IQ to hold the counter value. We could have used Q directly, but then we d have to declare its port type as buffer rather than out. Also, we could have defined the type of ports D and Q to be SD_LOGIC_VECOR, but then we would have to perform type conversions inside the body of the process (see Exercise 8.). able 8- VHDL program for a x-like -bit binary counter. library IEEE; use IEEE.std_logic_.all; use IEEE.std_logic_arith.all; entity Vx is port (, _L, _L,, : in SD_LOGIC; D: in UNSIGNED ( downto 0); Q: out UNSIGNED ( downto 0); : out SD_LOGIC ); end Vx; architecture Vx_arch of Vx is signal IQ: UNSIGNED ( downto 0); begin process (,, IQ) begin if ('event and ='') then if _L='0' then IQ <= (others => '0'); elsif _L='0' then IQ <= D; elsif ( and )='' then IQ <= IQ + ; end if; end if; if (IQ=) and (='') then <= ''; else <= '0'; end if; Q <= IQ; end process; end Vx_arch;

17 Section 8. Counters 0 able 8- VHDL architecture for counting in excess- order. architecture Vxs_arch of Vx is signal IQ: UNSIGNED ( downto 0); begin process (,, IQ) begin if 'event and ='' then if _L='0' then IQ <= (others => '0'); elsif _L='0' then IQ <= D; elsif ( and )='' and (IQ=) then IQ <= ('0','0','',''); elsif ( and )='' then IQ <= IQ + ; end if; end if; if (IQ=) and (='') then <= ''; else <= '0'; end if; Q <= IQ; end process; end Vxs_arch; As in ABEL, specialized counting sequences can be specified very easily using behavioral VHDL code. For example, able 8- modifies the x- like counter to count in excess- sequence (,,,, ). Unfortunately, some VHDL synthesis engines do not synthesize counters particularly well. In particular, they tend to synthesize the counting step using a binary adder with the counter value and a constant as operands. his approach requires much more combinational logic than what we ve shown for discrete counters, and is particularly wasteful in CPs and FPGAs containing flipflops, XOR gates, or other structures optimized for counters. In this case, a useful alternative is to write structural VHDL that is targeted to the cells available in a particular CP, FPGA, or ASIC technology. For example, we can construct one bit-cell for a x-like counter using the circuit in Figure 8-. his circuit is designed to use serial propagation for the carry bits, so the same circuit can be used at any stage of an arbitrarily large counter, subject to fanout constraints on the common signals that drive all of the stages. he signals in the bit-cell have the following definitions: (common) he clock input for all stages. NO (common) Asserted if the counter s input is asserted and is negated. NOOR (common) Asserted if the counter s and inputs are both negated. CN (common) Asserted if the counter s input is asserted. Di (per cell) Load data input for cell i.

18 0 Chapter 8 Sequential Logic Design Practices NO Ai Di DINi NOOR D Q Qi CN CEi CDAi CDi CK Q CNENi Q_Li CNEN_Li CNENi+ Figure 8- One bit-cell of a synchronous serial, x-like counter. CNENi (per cell) Serial count enable input for cell i. CNENi+ (per cell) Serial count enable output for cell i. Qi (per cell) Counter output for cell i. able 8- is a VHDL program corresponding to the bit-cell in the figure. In the program, the D flip-flop component Vdffqqn is assumed to be already defined; it is similar to the D flip-flop in able 8- with the addition of a QN (complemented) output. In an FPGA or ASIC design, a flip-flop component type would be chosen from the manufacturer s standard cell library. able 8- VHDL program for counter cell of Figure 8-. library IEEE; use IEEE.std_logic_.all; entity syncsercell is port(, NO, NOOR, CN, D, CNEN: in SD_LOGIC; CNENO, Q: out SD_LOGIC ); end syncsercell; architecture syncsercell_arch of syncsercell is component Vdffqqn port(, D: in SD_LOGIC; Q, QN: out SD_LOGIC ); end component; signal A, CDA, DIN, Q_L: SD_LOGIC; begin A <= NO and D; CDA <= NOOR and ((CN and CNEN) xor not Q_L); DIN <= A or CDA; CNENO <= (not Q_L) and CNEN; U: Vdffqqn port map (, DIN, Q, Q_L); end syncsercell_arch;

19 Section 8. Counters A MAER Note that able 8- uses a combination of dataflow and structural VHDL styles. It OF SYLE could have been written completely structurally, for example using an ASIC manufacturer s gate component definitions, to guarantee that the synthesized circuit conforms exactly to Figure 8-. However, most synthesis engines can do a good job of picking the best gate realization for the simple signal assignments used here. able 8- shows how to create an 8-bit synchronous serial counter using the cell defined previously. he first two assignments in the architecture body synthesize the common NO and and NOOR signals. he next two statements handle boundary condition for the serial count-enable chain. Finally, the generate statement (introduced on page ) instantiates eight -bit counter cells and hooks up the count-enable chain as required. It should be clear that a larger or smaller counter can be created simply by changing a few definitions in the program. You can put VHDL s generic statement to good use here to allow you to change the counter s size with a one-line change (see Exercise 8.). able 8- VHDL program for an 8-bit x-like synchronous serial counter. library IEEE; use IEEE.std_logic_.all; entity Vxs is port(, _L, _L,, : in SD_LOGIC; D: in SD_LOGIC_VECOR ( downto 0); Q: out SD_LOGIC_VECOR ( downto 0); : out SD_LOGIC ); end Vxs; architecture Vxs_arch of Vxs is component syncsercell port(, NO, NOOR, CN, D, CNEN: in SD_LOGIC; CNENO, Q: out SD_LOGIC ); end component; signal NO, NOOR: SD_LOGIC; -- common signals signal SCNEN: SD_LOGIC_VECOR (8 downto 0); -- serial count-enable inputs begin NO <= (not _L) and _L; -- create common load and clear controls NOOR <= _L and _L; SCNEN(0) <= ; -- serial count-enable into the first stage <= SCNEN(8); -- is equivalent to final count-enable output g: for i in 0 to generate -- generate the eight syncsercell stages U: syncsercell port map (, NO, NOOR,, D(i), SCNEN(i), SCNEN(i+), Q(i)); end generate; end Vxs_arch;