Lenguaje VHDL. Diseño de sistemas digitales secuenciales

Transcription

1 Lenguaje VHDL Diseño de sistemas digitales secuenciales

2 Flip-Flop D 1 entity d_ff is clk: in std_logic; d: in std_logic; q: out std_logic 2 end d_ff; P3 P1 5 Q D Q Q(t+1) architecture arch of d_ff is process(clk) P2 3 if (clk'event and clk='1') then q <= d; end 4 if; P4 end arch; 6 Q Clock D Q Q

3 Flip-flop con reset asíncrono entity d_ff_reset is clk, reset: in std_logic; d: in std_logic; q: out std_logic end d_ff_reset; architecture arch of d_ff_reset is process(clk,reset) if (reset='1') then q <='0'; elsif (clk'event and clk='1') then q <= d; end arch;

4 Flip-flop con enable síncrono entity d_ff_en is clk, reset: in std_logic; en: in std_logic; d: in std_logic; q: out std_logic end d_ff_en; architecture arch of d_ff_en is process(clk,reset) if (reset='1') then q <='0'; elsif (clk'event and clk='1') then if (en='1') then q <= d; end arch;

5 Quiz Diseñe un flip-flop RS, la tabla de verdad se muestra a continuación. U1 CLK R S FFSR Q QN S R Q Qt X X

6 Registros U1 clk q(7:0) d(7:0) reset reg_reset entity reg_reset is clk, reset: in std_logic; d: in std_logic_vector(7 downto 0 q: out std_logic_vector(7 downto 0) end reg_reset; architecture arch of reg_reset is process(clk,reset) if (reset='1') then q <=(others=>'0' elsif (clk'event and clk='1') then q <= d; end arch;

7 U1 clk ctrl(1:0) d(n-1:0) reset Registro de corrimiento q(n-1:0) univ_shift_reg entity univ_shift_reg is generic(n: integer := 8 clk, reset: in std_logic; ctrl: in std_logic_vector(1 downto 0 d: in std_logic_vector(n-1 downto 0 q: out std_logic_vector(n-1 downto 0) end univ_shift_reg; architecture arch of univ_shift_reg is signal r_reg: std_logic_vector(n-1 downto 0 signal r_next: std_logic_vector(n-1 downto 0 -- register process(clk,reset) if (reset='1') then r_reg <= (others=>'0' elsif (clk'event and clk='1') then r_reg <= r_next; -- next-state logic with ctrl select r_next <= r_reg when "00", --no op r_reg(n-2 downto 0) & d(0) when "01", --shift left; d(n-1) & r_reg(n-1 downto 1) when "10", --shift righ d when others; -- load -- output q <= r_reg; end arch;

8 Contadores use ieee.numeric_std.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is generic (N:integer:=4 clk: in std_logic; q: inout std_logic_vector(n-1 downto 0) end counter; architecture arch of counter is process(clk) if (clk'event and clk='1') then q <= q+1; end arch;

9 Ejercicio Diseñe un circuito que muestre la cuenta de 0 a F (a un Hertz) en uno de los cuatro displays, la selección se realiza empleando las señales de entrada sel. Clk Reset Sel0 Sel1 Contador a 1 Hz 8 2 an

10 Contador up/down use ieee.numeric_std.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter_ud is generic (N:integer:=4 clk, reset, up: in std_logic; q: inout std_logic_vector(n-1 downto 0) end counter_ud; architecture arch of counter_ud is process(clk,reset,up) if (reset='1') then q<=(others=>'0' if (clk'event and clk='1') then if (up='1') then q <= q+1; else q <= q-1; end arch;

11 Máquinas de Mealy y Moore

12 Diagramas de estado Definición de tipos y señales type estados is (s0, s1, s2, s3 signal edo_presente, edo_futuro:estados; El proceso que define el comportamiento del sistema, debe considerar que el estado_futuro depende del estado_presente y de las entradas. process(edo_presente,a,b)

13 Diagramas de estado entity fsm is clk, reset: in std_logic; a, b: in std_logic; y0, y1: out std_logic end fsm;

14 process(edo_presente,a,b) architecture two of fsm is type estados is (s0, s1, s2 signal edo_presente, edo_futuro: estados; process(clk,reset) if (reset='1') then edo_presente <= s0; elsif (clk'event and clk='1') then edo_presente <= edo_futuro; y0 <= '0'; -- default 0 y1 <= '0'; -- default 0 case edo_presente is when s0 => y1 <= '1'; if a='1' then if b='1' then edo_futuro <= s2; y0 <= '1'; else edo_futuro <= s1; when s1 => y1 <= '1'; if (a='1') then edo_futuro <= s0; when s2 => edo_futuro <= s0; end case; end two;

15 Mejor implementación entity fsm is clk, reset: in std_logic; a, b: in std_logic; y0, y1: out std_logic end fsm; architecture two_seg_arch of fsm is type estados is (s0, s1, s2 signal edo_presente, edo_futuro: estados; process(clk,reset) if (reset='1') then edo_presente <= s0; elsif (clk'event and clk='1') then edo_presente <= edo_futuro; process(edo_presente,a,b) y0 <= '0'; -- default 0 y1 <= '0'; -- default 0 case edo_presente is when s0 => 001 y1 <= '1'; if a='1' then if b='1' then 011 edo_futuro <= s2; else 010 edo_futuro <= s1; -- no else branch when s1 => y1 <= '1'; if (a='1') then edo_futuro <= s0; else edo_futuro <= s1; when s2 => y0 <= '1'; edo_futuro <= s0; end case; end two_seg_arch;

16 Ejercicio

17 Circuito anti-rebote Diseñar el código en VHDL para un circuito anti-rebotes. F library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity antirebote is port ( clk, reset,pbsync: in STD_LOGIC; pulse: out STD_LOGIC end antirebote; architecture cartasm of antirebote is type estados is (s0,s1 signal edo_presente, edo_futuro: estados; process (clk, reset) if (reset='1') then edo_presente<=s0; elsif (clk'event and CLK = '1') then edo_presente<=edo_futuro; process (edo_presente, pbsync) pulse<='0'; case edo_presente is when s0 => if (pbsync='0') then edo_futuro<=s0; else edo_futuro<=s1; pulse<='1'; when s1=> pulse<='0'; if (pbsync='1') then edo_futuro<=s1; else edo_futuro<=s0; end case; end cartasm; T F T