# CS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on

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1 CS 61C: Great Ideas in Computer Architecture Finite State Machines Instructors: Krste Asanovic & Vladimir Stojanovic hbp://inst.eecs.berkeley.edu/~cs61c/sp15 1 Levels of RepresentaKon/ InterpretaKon High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g., MIPS) Machine Interpreta4on Assembler Machine Language Program (MIPS) Hardware Architecture DescripCon (e.g., block diagrams) Architecture Implementa4on Logic Circuit DescripCon (Circuit SchemaCc Diagrams) temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw \$t0, 0(\$2) lw \$t1, 4(\$2) sw \$t1, 0(\$2) sw \$t0, 4(\$2) Anything can be represented as a number, i.e., data or instruckons ! 2 Type of Circuits Synchronous Digital Systems consist of two basic types of circuits: CombinaKonal Logic (CL) circuits Output is a funckon of the inputs only, not the history of its execukon E.g., circuits to add A, B (ALUs) SequenKal Logic (SL) Circuits that remember or store informakon aka State Elements E.g., memories and registers (Registers) Uses for State Elements Place to store values for later re- use: Register files (like \$1- \$31 in MIPS) Memory (caches and main memory) Help control flow of informa;on between combina;onal logic blocks State elements hold up the movement of informakon at input to combinakonal logic blocks to allow for orderly passage 3 4 Accumulator Example First Try: Does this work? Why do we need to control the flow of informakon? X i SUM S Want: S=0; for (i=0;i<n;i++) S = S + X i Assume: Each X value is applied in succession, one per cycle Afer n cycles the sum is present on S 5 Feedback No! Reason #1: How to control the next iterakon of the for loop? Reason #2: How do we say: S=0? 6 1

2 Second Try: How About This? Register is used to hold up the transfer of data to adder Model for Synchronous Systems Square wave clock sets when things change Rough Kming High (1) Low (0) High (1) Low (0) High (1) Low (0) Time Rounded Rectangle per clock means could be 1 or 0 Xi must be ready before clock edge due to adder delay 7 CollecKon of CombinaKonal Logic blocks separated by registers Feedback is opkonal Clock signal(s) connects only to clock input of registers Clock (CLK): steady square wave that synchronizes the system Register: several bits of state that samples on rising edge of CLK (posikve edge- triggered) or falling edge (negakve edge- triggered) 8 Register Internals n instances of a Flip- Flop Flip- flop name because the output flips and flops between 0 and 1 D is data input, Q is data output Also called D- type Flip- Flop 9 Flip- Flop OperaKon Edge- triggered d- type flip- flop This one is posikve edge- triggered On the rising edge of the clock, the input d is sampled and transferred to the output. At all other Kmes, the input d is ignored. Example waveforms: Fall Lecture #23 Flip- Flop Timing Edge- triggered d- type flip- flop This one is posikve edge- triggered On the rising edge of the clock, the input d is sampled and transferred to the output. At all other Kmes, the input d is ignored. Example waveforms (more detail): Camera Analogy Timing Terms Want to take a portrait Kming right before and afer taking picture Set up ;me don t move since about to take picture (open camera shuber) Hold ;me need to hold skll afer shuber opens unkl camera shuber closes Time click to data Kme from open shuber unkl can see image on output (viewscreen) 12 2

3 Hardware Timing Terms Setup Time: when the input must be stable before the edge of the CLK Hold Time: when the input must be stable a?er the edge of the CLK CLK- to- Q Delay: how long it takes the output to change, measured from the edge of the CLK Accumulator Timing 1/2 Reset input to register is used to force it to all zeros (takes priority over D input). S i- 1 holds the result of the i th - 1 iterakon. Analyze circuit Kming starkng at the output of the register. 13 Accumulator Timing 2/2 reset signal shown. Also, in prackce X might not arrive to the adder at the same Kme as S i- 1 S i temporarily is wrong, but register always captures correct value. In good circuits, instability never happens around rising edge of clk. Maximum Clock Frequency What is the maximum frequency of this circuit? Hint: Frequency = 1/Period Max Delay = CLK- to- Q Delay + CL Delay + Setup Time 16 CriKcal Paths Pipelining to improve performance Timing! Timing! Note: delay of 1 clock cycle from input to output." Clock period limited by propagation delay of adder/shifter." Insertion of register allows higher clock frequency." More outputs per second (higher bandwidth)" But each individual result takes longer (greater latency)" 3

4 Recap of Timing Terms Clock (CLK) - steady square wave that synchronizes system Setup Time - when the input must be stable before the rising edge of the CLK Hold Time - when the input must be stable afer the rising edge of the CLK CLK- to- Q Delay - how long it takes the output to change, measured from the rising edge of the CLK Flip- flop - one bit of state that samples every rising edge of the CLK (posikve edge- triggered) Register - several bits of state that samples on rising edge of CLK or on LOAD (posikve edge- triggered) Clickers/Peer InstrucKon Clock What is maximum clock frequency? A: 5 GHz B: 200 MHz C: 500 MHz D: 1/7 GHz E: 1/6 GHz Clock- >Q 1ns Setup 1ns Hold 1ns AND delay 1ns Administrivia Project 1-1 due 3/01 Midterm is next Thursday 2/26, in class Covers up to and including the previous lecture 1 handwriben, double sided, 8.5 x11 cheat sheet We ll give you MIPS green sheet Review Sessions: TA: Monday 2/23, 7-9pm, 10 Evans HKN: Saturday 2/21, 1-4pm, 100 GeneKcs Plant Biology Finite State Machines (FSM) Intro You have seen FSMs in other classes." Same basic idea." The function can be represented with a state transition diagram." With combinational logic and registers, any FSM can be implemented in hardware." 21 FSM Example: 3 ones FSM to detect the occurrence of 3 consecutive 1 s in the input." Draw the FSM! Hardware ImplementaKon of FSM Therefore a register is needed to hold the a representation of which state the machine is in. Use a unique bit pattern for each state." +! Assume state transitions are controlled by the clock:" on each clock cycle the machine checks the inputs and moves to a new state and produces a new output " Combinational logic circuit is used to implement a function maps from present state and input to next state and output.! =!?! 4

5 FSM CombinaKonal Logic Specify CL using a truth table." Truth table! PS" Input" NS" Output" 00" 0" 00" 0" 00" 1" 01" 0" 01" 0" 00" 0" 01" 1" 10" 0" 10" 0" 00" 0" 10" 1" 00" 1" Moving between Representations" Use this table and techniques we learned last time to transform between alternative views of same logic function" Building Standard Functional Units" Data multiplexers" Arithmetic and Logic Unit" Adder/Subtractor" Data Multiplexer ( Mux ) (here 2-to-1, n-bit-wide)" N instances of 1-bit-wide mux" How many rows in TT? How do we build a 1-bit-wide mux?" 5

6 4-to-1 multiplexer?" How many rows in TT? Another way to build 4-1 mux?" Hint: NCAA tourney! Ans: Hierarchically! Arithmetic and Logic Unit" Our simple ALU" Most processors contain a special logic block called the Arithmetic and Logic Unit (ALU)" We ll show you an easy one that does ADD, SUB, bitwise AND, bitwise OR" In the News: Microsof, Google beat Humans at Image RecogniKon (EE Times) How to design Adder/Subtractor?" Truth-table, then determine canonical form, then minimize and implement as we ve seen before" Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer" On ImageNet benchmark image database, systems from Microsof and Google performed beber than humans at recognizing images Both companies used deep arkficial neural networks to train on image database 35 6

7 Adder/Subtractor One-bit adder LSB " Adder/Subtractor One-bit adder (1/2) " Adder/Subtractor One-bit adder (2/2)" N 1-bit adders 1 N-bit adder" b 0 " What about overflow? Overflow = c n? Extremely Clever Subtractor " In Conclusion Finite State Machines have clocked state elements plus combinakonal logic to describe transikon between states Standard combinakonal funckonal unit blocks built hierarchically from subcomponents XOR serves as condiconal inverter! x! y! XOR(x,y)! 0! 0! 0! 0! 1! 1! 1! 0! 1! 1! 1! 0! 42 7

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