Samar Abdi. (slides courtesy of A. Gerstlauer, D. Gajski and R. Doemer)

COEN 691B: Embedded System Design Lecture 1: Introduction, Course Logistics Samar Abdi (slides courtesy of A. Gerstlauer, D. Gajski and R. Doemer) Assistant Professor Electrical and Computer Engineering Concordia University http://www.ece.concordia.ca/~samar

Lecture Outline What are Embedded Systems and why should we care? Course organization/policies ES modeling ES design methodologies Languages Case study for the programming assignments Intro to Real-Time Systems 2

Embedded Systems Systems that are part of a larger system Application-specific Diverse application areas Tight constraints Real-time, performance, power, size Cost, time-to-market, reliability Ubiquitous Far bigger market than generalpurpose computing (PCs, servers) $46 billion in 04, >$90 billion by 2010, 14% annual growth 4 billion devices in 04 98% of processors sold [Turley02, embedded.com] COEN 691B: Embedded System Design 3

System Design is hard COEN 691B: Embedded System Design 4

Logic transistors per chip (in millions) Productivity (K) Trans./Staff-Mo. and getting harder Growing system complexities Increasing application demands Networked and distributed Cyber-physical integration Increasingly programmable & customizable Technological advances Multi-Processor System-On-Chip (MPSoC) 10,000 100,000 1,000 10,000 100 10 IC capacity Gap 1000 100 1 0.1 0.01 Productivity 10 1 0.1 0.001 0.01 Source: SEMATECH; Courtesy of: T. Givargis, F. Vahid. Embedded System Design, Wiley 2002. COEN 691B: Embedded System Design 5

General-Purpose Computing Reaching physical limits of technology scaling Power/utilization/ walls and dark silicon Efficiency/optimality vs. flexibility/generality Opportunity and need for specialization Heterogeneous multi-core / Asynchronous CMP GP-GPUs COEN 691B: Embedded System Design 6

Processor Implementation Options Source: T. Noll, RWTH Aachen, via R. Leupers, From ASIP to MPSoC, Computer Engineering Colloquium, TU Delft, 2006 COEN 691B: Embedded System Design 7

Multi-Processor System-on-Chip (MPSoC) System Memory Memory Controller CPU GPU Local RAM Frontside Bus DSP DSP RAM Hardware Accelerator Bridge DSP Bus Shared RAM Hardware Accelerator Video Front End Local Bus COEN 691B: Embedded System Design 8

MPSoC Challenges Complexity High degree of parallelism at various levels High degree of design freedom Multiple optimization objectives design constraints Applications Programming Model? Heterogeneity Of components Processors, memories, busses Of design tasks Architecture, mapping, scheduling COEN 691B: Embedded System Design 9

Abstraction Accuracy Abstraction Levels Move to higher levels of abstraction [ITRS07, itrs.net] Electronic system-level (ESL) design Level Number of components System level Algorithm 1E0 1E1 1E2 RTL Gate Transistor 1E3 1E4 1E5 1E6 1E7 Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 10

Arbiter1 TX System-Level Design From specification Functionality, behavior Application algorithms Constraints To implementation Architecture Spatial and temporal order Components and connectivity Across hardware and software Design automation at the system level Modeling and simulation Synthesis Verification ARM MP3 IP Bridge DCTBus DCT DCT Jpeg BUS1 (AHB) M1 Requirements, constraints Proc Proc stripe MBUS M1Ctrl DMA Proc Proc System Design DSP I/O1 Enc Dec I/O2 Proc BUS2 (DSP) I/O3 HW Codebk I/O4 SI BO BI SO Implementation (HW/SW synthesis) COEN 691B: Embedded System Design 11

Course Logistics Course website: http://www.ece.concordia.ca/~samar/coen691b Lectures: F, 17:45 20:15, MB-S2.285 Office hours: M, W 15:00 16:00, EV 5.183 All lectures slides will be made available on course website Immediately after the class COEN 691B: Embedded System Design 13

No Final Exam Midterm (20%) November 11, in class Grading Fixed and no make-up test offered Programming assignments(40% total) Project (40%) All submissions must be made on EAS Login with ENCS account to https://fis.encs.concordia.ca/eas COEN 691B: Embedded System Design 14

Programming Assignments Total four programming assignments To be done independently or in teams of two First assignment will be posted by next class SystemC modeling for embedded system specification Digital camera example (JPEG encoder) Original C model will be posted on course website this weekend All SystemC models will be refined stepwise from the original C model All models must be validated for functional correctness against the C model COEN 691B: Embedded System Design 15

Project Teams of 2-3 students allowed Possible project ideas will be listed on course website by next class Project goals Independent research or development project ES design example/case study for an application ES design automation tool Literature review, proposal, implementation Final report and presentation in publishable quality Project timeline Abstract (Submit by Sept. 30) Detailed problem definition and review of related work (present on October 28) Demonstration and final presentation (December 2) Final report (Submit by December 7) COEN 691B: Embedded System Design 16

Plagiarism Midterms, Programming Assignment and Projects require original work Strictly enforced All plagiarism cases will be reported Please refer to Concordia s code of conduct: http://provost.concordia.ca/academicintegrity/code/ COEN 691B: Embedded System Design 17

Textbooks Main textbook D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Springer, 2009 ( orange book ) SystemC Reference T. Groetker, S. Liao, G. Martin, S. Swan, System Design with SystemC, Kluwer, 2002 ( black book") Several online tutorials and examples available Additional reading material (papers) will be posted on the webpage as the course progresses COEN 691B: Embedded System Design 18

Modeling A model: Abstraction of physical reality Mathematical formula, drawing/blueprint, data Core of any design process Specification Define (formally!) desired characteristics, golden reference Exploration Validate design choices Analysis and evaluation Static analysis Simulation/experiments Predict before the system is built Contract of what to build Detect problems early (and cheaply) Stimuli Model Simulator Results Correctness of model? Accuracy vs. simplicity COEN 691B: Embedded System Design 20

System Specification Capture requirements (what) Functional Free of any implementation details (not how) Non-functional Quality metrics Performance constraints Formal representation Models of computation Objects and compositions Concurrency and time Executable Analysis or simulation Application development Precise description of desired system behavior Complete and unambiguous P1 P2 d d Natural language Ambiguous Incomplete P3 P4 C1 C2 P5 COEN 691B: Embedded System Design 21

Arbiter Bridge System Architecture Processing elements (PEs) Processors General-purpose, programmable Digital signal processors (DSPs) Application-specific instruction set processor (ASIP) Custom hardware processors Intellectual property (IP) Memories CPU P1 CPU Bus P2 HW P3 P4 C1, C2 Mem C1, C2 IP P5 IP Bus Communication elements (CEs) Transducers, bus bridges I/O peripherals Busses Communication media Parallel, master/slave protocols Serial and network media Application mapping Allocation Partitioning Scheduling COEN 691B: Embedded System Design 22

System Implementation Hardware Microarchitecture Register-transfer level (RTL) Software binaries Application object code Real-time operating system (RTOS) Hardware abstraction layer (HAL) Interfaces Pins and wires Arbiters, muxes, interrupt controllers (ICs), etc. Bus protocol state machines CPU Arbiter Program HW EXE RTOS HAL IC Mem Bridge Specification for further manufacturing Logic synthesis Layout IP COEN 691B: Embedded System Design 23

Instruction-Set Simulator (ISS) Arbiter Bridge C1 System-Level Design Flow CPU Mem B1 B2 v1 Computation & Communication C2 HW Platform library IP System Synthesis Front-End B3 Application specification B4 System-Level Design Languages (SLDLs) Transaction-Level Models TLM n C/C++ code Software / Hardware Synthesis Back-End C-based RTL Software Object Code Hardware VHDL/Verilog COEN 691B: Embedded System Design 24

Models vs. Languages Models Poetry Recipe Story State Sequent. machine program Dataflow Languages English Spanish Japanese C C++ Java Recipes vs. English Sequential programs vs. C Computation models describe system behavior Conceptual notion, e.g., recipe, sequential program Languages capture models Concrete form, e.g., English, C Variety of languages can capture one model E.g., sequential program model C,C++, Java One language can capture variety of models E.g., C++ sequential program model, object-oriented model, state machine model Certain languages better at capturing certain models Source: T. Givargis, F. Vahid. Embedded System Design, Wiley 2002. COEN 691B: Embedded System Design 25

Text vs. Graphics Models versus languages not to be confused with text versus graphics Text and graphics are just two types of languages Text: letters, numbers Graphics: circles, arrows (plus some letters, numbers) X = 1; if (N) Y = X + 1; X =1 N? Y = X + 1 Source: T. Givargis, F. Vahid. Embedded System Design, Wiley 2002. COEN 691B: Embedded System Design 26

Simulation vs. Synthesis Ambiguous semantics of languages 3.415 2.715 -- Finite state machine case X is when X1=>... when X2=> -- Look-up table Controller Memory Simulatable but not synthesizable or verifiable Impossible to automatically discern implicit meaning Need explicit set of constructs Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 27

Design Flow Design methodology Sequence of design models Flow of transformations between models Models Well-defined, rigorous semantics Systematic flow from specification to implementation Languages Representation of models in machine-readable form COEN 691B: Embedded System Design 29

Evolution of Design Flows Capture & Simulate Describe & Synthesize Specify, Explore & Refine Specs Specs Executable Spec Functionality Algorithms Algorithms Algorithms Algorithms System Gap SW? SW? Architecture Network Connectivity Protocols Design Describe Design SW/HW Performance Simulate Logic Simulate Logic Logic Timing Physical Physical Physical Manufacturing Manufacturing Manufacturing 1960's 1980's 2000's Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 30

Models of Computation (MoCs) Y-Chart Behavior (Function) System Structure (Netlist) Processor Specification Algorithm Boolean logic (a v b) Logic Circuit PE,Bus RTL Gates Models of Structure (MoSs) Transfer Physical (Layout) Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 31

C W PC Status Processor Synthesis Software processor Compilation and linking Hardware processor High-level synthesis BB1 N IF Y C M em const B1... RF / Scratch pad B2 BB2 BB3 offset AG status ALU M U L M em ory address N Y IF Algorithm model (program) B3 Microarchitecture model (RTL) Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 32

A rb iter B rid g e Structure Partitioning, mapping System Synthesis Timing Scheduling C P U M em P1 P3 P 1 d P3 C 1 d P5 CPU Bus C 1, C 2 C 1, C 2 IP Bus P 2 P4 C 2 P2 P4 P5 HW IP Specification model (processes) Architecture model (TLM) Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 33

Bottom-Up Methodology Behavior (Function) System Processor Structure (Netlist) Each level generates library for the next higher level Circuit: Standard cells for logic level Logic: RTL components for processor level Processor: Processing and communication components for system level System: System platforms for different applications Floorplanning and layout on each level Start Logic Circuit Physical (Layout) PE,Bus RTL Gates Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 34

Top-down Methodology Behavior (Function) System Structure (Netlist) Start Functional description is converted into component netlist on each level Each component function is decomposed further on the next abstraction level Layout is given only for transistor components Physical (Layout) Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 35

Meet-in-the-Middle Methodology Behavior (Function) System Structure (Netlist) Gate netlist is hand-off Three levels of synthesis System is synthesized with processor components Processor components are synthesized with RTL library RTL components are synthesized with standard cells Two levels of layout System layout is performed with standard cells Standard cells layout with transistors Start Physical (Layout) Gates Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 36

Platform-Based Design Behavior (Function) Start System Processor Logic Circuit Structure (Netlist) Platform Meet-in-the-middle at the system level System platform with standard components System design reduced to mapping of specification onto pre-defined platform Physical (Layout) RTL Gates Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 37

System Modeling Basis of any design flow and design automation Inputs and outputs of design steps Capability to capture complex systems Precise, complete and unambiguous Models at varying levels of abstraction Level and granularity of implementation detail Speed vs. accuracy Design models as an abstraction of a design instance Representation of some aspect of reality Virtual prototyping for validation through simulation or formal analysis Specification for further implementation/synthesis Describe desired functionality Documentation & specification Abstraction to hide details that are not relevant or not yet known Different parts of the model or different use cases for the same model COEN 691B: Embedded System Design 38

Abstraction Levels unstructured High abstraction untimed Structure Implementation Detail Timing physical layout real time Spatial order Low abstraction Temporal order COEN 691B: Embedded System Design 39

Top-Down Design Flow requirements Product planning constraints pure functional Specification untimed System Design bus functional Architecture timing accurate Processor Design RTL / ISA Implementation cycle accurate gates Logic Design gate delays Structure Timing COEN 691B: Embedded System Design 40

Top-Down Design Flow requirements Product planning constraints pure functional Specification model untimed Computation design partitioned Timed model scheduled Communication design bus functional Transaction-level model timing accurate Processor design RTL / IS Implementation model cycle accurate Structure Logic design Timing COEN 691B: Embedded System Design 41

Top-Down Design Flow requirements Product planning constraints Capture Algor. IP pure functional Specification model untimed Computation refinement Comp. IP transaction level Timed model estimated timing Communication refinement Proto. IP bus functional Transaction-level model timing accurate RTL IP Hardware synthesis Interface synthesis Software synthesis RTOS IP RTL / IS Implementation model cycle accurate Structure Logic design Timing COEN 691B: Embedded System Design 42

Design Methodology System design Validation flow Capture Algor. IP Specification model Computation refinement Comp. IP Compilation Validation Analysis Estimation Simulation model Timed model Communication refinement Proto. IP Compilation Validation Analysis Estimation Simulation model Transaction-level model Compilation Validation Analysis Estimation Simulation model RTL IP Hardware synthesis Interface synthesis Software synthesis RTOS IP Backend Implementation model Compilation Validation Analysis Estimation Simulation model COEN 691B: Embedded System Design 43

Languages Represent a model in machine-readable form Apply algorithms and tools Syntax defines grammar Possible strings over an alphabet Textual or graphical Semantics defines meaning Mapping onto an abstract state machine model Operational semantics Mapping into a mathematical domain (e.g. functions) Denotational semantics Semantic model vs. design models Basic semantic models can represent many design models Discrete event model for hardware and system simulation Design models can be represented in different languages COEN 691B: Embedded System Design 45

Evolution of Design Languages Netlists Structure only: components and connectivity Gate-level [EDIF], system-level [SPIRIT/XML] Hardware description languages (HDLs) Event-driven behavior: signals/wires, clocks Register-transfer level (RTL): boolean logic Discrete event [VHDL, Verilog] System-level design languages (SLDLs) Software behavior: sequential functionality/programs C-based, event-driven [SpecC, SystemC, SystemVerilog] COEN 691B: Embedded System Design 46

System-Level Design Languages (SLDLs) Goals Executability Validation through simulation Synthesizability Implementation in HW and/or SW Support for IP reuse Modularity Hierarchical composition Separation of concepts Completeness Support for all concepts found in embedded systems Orthogonality Orthogonal constructs for orthogonal concepts Minimality Simplicity Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 47

System-Level Design Languages Requirements (SLDLs) Behavioral hierarchy Structural hierarchy Concurrency Synchronization Exception handling Timing State transitions Composite data types not supported partially supported supported Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 48

System-Level Design Languages (SLDLs) C/C++ ANSI standard programming languages, software design Traditionally used for system design because of practicality, availability SystemC C++ API and class library Initially developed at UC Irvine, standard by Open SystemC Initiative (OSCI) SpecC C extension Developed at UC Irvine, standard by SpecC Technology Open Consortium (STOC) SystemVerilog Verilog with C extensions for testbench development Matlab/Simulink Specification and simulation in engineering, algorithm design Unified Modeling Language (UML) Software specification, graphical, extensible (meta-modeling) Modeling and Analysis of Real-time and Embedded systems (MARTE) profile IP-XACT XML schema for IP component documentation, standard by SPIRIT consortium Rosetta (formerly SLDL) Formal specification of constraints, requirements SDL Telecommunication area, standard by ITU Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 49

Separation of Concerns Fundamental principle in modeling of systems Clear separation of concerns Address separate issues independently System-Level Description Language (SLDL) Orthogonal concepts Orthogonal constructs System-level Modeling Computation encapsulated in modules / behaviors Communication encapsulated in channels Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 50

Computation vs. Communication Traditional model P1 s1 P2 Processes and signals Mixture of computation and communication Automatic replacement impossible s2 s3 Channel concept (OOP) B1 C1 v1 B2 v2 Tasks and channels Separation of computation and communication Plug-and-play v3 Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 51

Computation vs. Communication Protocol Inlining Specification model Exploration model B1 C1 v1 v2 B2 v3 Computation in behaviors Communication in channels Implementation model B1 v1 B2 v2 v3 Channel disappears Communication inlined Wires exposed Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 52

Intellectual Property (IP) Communication IP: Channel with wrapper C1 v1 v2 v3 replacable at any time C2 IP Virtual channel IP protocol channel in wrapper Protocol inlining with hierarchical channel B1 B2 B1 B2 v1 v1 v2 v2 before after Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 53

Programming Assignment: Digital Camera Specification CCD Sensor SoC CCD Control pixel Jpeg Encoder bytes File I/O Flash Memory JpegEncoder Pixel 8x8 block 8x8 block 8x8 block Read DCT Quant Huff bytes COEN 691B: Embedded System Design 55

Pixel rows Charge-Coupled Device (CCD) Special sensor that captures an image Light-sensitive silicon solid-state device composed of many cells When exposed to light, each cell becomes electrically charged. This charge can then be converted to a 8-bit value where 0 represents no exposure while 255 represents very intense exposure of that cell to light. Some of the columns are covered with a black strip of paint. The light-intensity of these pixels is used for zerobias adjustments of all the cells. Lens area Covered columns Pixel columns Electromechanical shutter Electronic circuitry The electromechanical shutter is activated to expose the cells to light for a brief moment. The electronic circuitry, when commanded, discharges the cells, activates the electromechanical shutter, and then reads the 8-bit charge value of each cell. These values can be clocked out of the CCD by external logic through a standard parallel bus interface. Source: T. Givargis, F. Vahid. Embedded System Design, Wiley 2002. COEN 691B: Embedded System Design 56

Compression JPEG (Joint Photographic Experts Group) Popular standard format for representing digital images in a compressed form Provides for a number of different modes of operation Mode used in this chapter provides high compression ratios using DCT (discrete cosine transform) Image data divided into blocks of 8 x 8 pixels 3 steps performed on each block DCT Quantization Huffman encoding Source: T. Givargis, F. Vahid. Embedded System Design, Wiley 2002. COEN 691B: Embedded System Design 57

Discrete Cosine Transform (DCT) Transforms original 8 x 8 block into a cosinefrequency domain Upper-left corner values represent low frequency components Essence of image Lower-right corner values represent finer details Can reduce precision of these values and retain reasonable image quality FDCT (Forward DCT) formula C(h) = if (h == 0) then 1/sqrt(2) else 1.0 Auxiliary function used in main function F(u,v) F(u,v) = ¼ C(u) C(v) Σx=0..7 Σy=0..7 Dxy cos(π(2u + 1)u/16) cos(π(2y + 1)v/16) Gives encoded pixel at row u, column v Dxy is original pixel value at row x, column y Source: T. Givargis, F. Vahid. Embedded System Design, Wiley 2002. COEN 691B: Embedded System Design 58

Quantization Achieve high compression ratio by reducing image quality Reduce bit precision of encoded data Fewer bits needed for encoding One way is to divide all values by a factor of 2 Simple right shifts can do this Dequantization would reverse process for decompression 1150 39-43 -10 26-83 11 41-81 -3 115-73 -6-2 22-5 14-11 1-42 26-3 17-38 2-61 -13-12 36-23 -18 5 44 13 37-4 10-21 7-8 36-11 -9-4 20-28 -21 14-19 -7 21-6 3 3 12-21 -5-13 -11-17 -4-1 7-4 After DCT Divide each cell s value by 8 144 5-5 -1 3-10 1 5-10 0 14-9 -1 0 3-1 2-1 0-5 3 0 2-5 0-8 -2-2 5-3 -2 1 6 2 5-1 1-3 1-1 5-1 -1-1 3-4 -3 2-2 -1 3-1 0 0 2-3 -1-2 -1-2 -1 0 1-1 After quantization Source: T. Givargis, F. Vahid. Embedded System Design, Wiley 2002. COEN 691B: Embedded System Design 59

Huffman Encoding (ZigZag) Serialize 8 x 8 block of pixels Values are converted into single list using zigzag pattern Perform Huffman encoding More frequently occurring pixels assigned short binary code Longer binary codes left for less frequently occurring pixels Each pixel in serial list converted to Huffman encoded values Much shorter list, thus compression Source: T. Givargis, F. Vahid. Embedded System Design, Wiley 2002. COEN 691B: Embedded System Design 60

Huffman Encoding (2) Pixel frequencies on left Pixel value 1 occurs 15 times Pixel value 14 occurs 1 time Build Huffman tree from bottom up Create one leaf node for each pixel value and assign frequency as node s value Create an internal node by joining any two nodes whose sum is a minimal value This sum is internal nodes value Repeat until complete binary tree Traverse tree from root to leaf to obtain binary code for leaf s pixel value Append 0 for left traversal, 1 for right traversal Huffman encoding is reversible No code is a prefix of another code Pixel frequency -1 15x 0 8x -2 6x 1 5x 2 5x 3 5x 5 5x -3 4x -5 3x -10 2x 144 1x -9 1x -8 1x -4 1x 6 1x 14 1x 1 5 29 1 4 Huffman tree 6 4-1 9 1 1 5 8 0 6 1 1 0-2 4 5 6 5 5 5 5 3 2 2 2 2 2 3 4-10 -5-3 1 1 1 1 1 14 6-4 -8-9 1 8 3 5 1 7 1 144 Huffman codes -1 00 0 100-2 110 1 010 2 1110 3 1010 5 0110-3 11110-5 10110-10 01110 144 111111-9 111110-8 101111-4 101110 6 011111 14 011110 Source: T. Givargis, F. Vahid. Embedded System Design, Wiley 2002. COEN 691B: Embedded System Design 61

Programming Assignments 1. C model to a concurrent SystemC Process Network model 2. Timing measurement for individual tasks and creation of a timed model 3. Modeling the RTOS scheduling layer to determine performance of SW implementation 4. Modeling a HW-SW solution by moving the DCT to a faster HW module COEN 691B: Embedded System Design 62

What will you learn? How to model embedded systems? Models of computations: process and state-based System-level modeling language (SystemC) Concurrency, Timing, Scheduling, Communication How to predict performance of embedded systems? ISS-based, measurements and source-level timing analysis How to do hardware-software co-design? Partitioning and mapping of applications Synthesis of platforms How to ensure correctness of embedded systems? Formal verification and simulation techniques COEN 691B: Embedded System Design 63

Summary Embedded systems are pervasive, difficult to design, and have a huge market! Over $90 billion market for embedded processors Embedded SW deployed in billions of electronic products Embedded SW has become the major cost component in modern cars A model-based approach from specification to implementation is essential for success! COEN 691B: Embedded System Design 64