İSTANBUL AYDIN UNIVERSITY

Transcription

1 İSTANBUL AYDIN UNIVERSITY FACULTY OF ENGİNEERİNG SOFTWARE ENGINEERING THE PROJECT OF THE INSTRUCTION SET COMPUTER ORGANIZATION GÖZDE ARAS B Instructor: Prof. Dr. HASAN HÜSEYİN BALIK DECEMBER 2013

2 Contents 1 Expansions and explanations together with abbreviations 2 Machine language 2.1 Instruction types Data handling and memory operations Arithmetic and logic operations Control flow operations 2.2 Classification of instruction sets CISC RISC 2.3 Complex instructions 2.4 Parts of an instruction 2.5 Instruction length 2.6 Representation 2.7 Design 3 Instruction set implementation 3.1 Code density 3.2 Number of operands Stack Accumulator General Purpose Register 4 References 1

3 Expansions and Explanations Together with Abbreviations Opcode: Operation Code; is the part of a machine language instruction that specifies the operation to be performed. CPU: Central Proccessing Unit; is the hardware within a computer that carries out the instructions of a computer program by performing the basic arithmetical, logical, and input/output operations of the system. ALU: Arithmetic and Logic Unit; is a digital circuit that performs integer arithmetic and logical operations. ROM: Read Only Memory; is a class of storage medium used in computers and other electronic devices. Data stored in ROM cannot be modified. RAM: Random Access Memory; is a form of computer data storage. A random access device allows stored data to be accessed directly in any random order. TOS: Terms of Services; - GPR: General Purpose Register; - PLA: Programmable Logic Array; is a kind of programmable logic device used to implement combinational logic circuits. SIMD: Single Instruction, Multiple Data; is a complex instruction type that has become particularly popular recently and is an operation that performs the same arithmetic operation on multiple pieces of data at the same time. SIMD instructions allow easy parallelization of algorithms commonly involved in sound, image, and video processing. ASIP: Application-Specific Instruction-set Processor; is a component used in system on a chip design. EDGE: Explicit Data Graph Execution; is a type of instruction set architecture which intends to greatly improve computing performance compared to common processors like the Intel x86 line. NISC: No Instruction Set Computing; is a computing architecture and compiler technology for designing highly efficient custom processors and hardware accelerators by allowing a compiler to have low-level control of hardware resources. ZISC: Zero Instruction Set Computer; refers to a computer architecture based on pure pattern matching and absence of instructions in the classical sense. MISC:Minimal Instruction Set Computer; is a processor architecture with a very small number of basic operations and corresponding opcodes. 2

4 OISC: One Instruction Set Computer; it sometimes called URISC: Ultimate Reduced Instruction Set Computer; is an abstract machine that uses only one instruction obviating the need for a machine language opcode. VLIW: Very Long Instruction Word; where the processor receives many instructions encoded and retrieved in one instruction word. It refers to a processor architecture designed to take advantage of instruction level parallelism. NOTE: ASIP, EDGE, NISC, ZISC, MISC, OISC and VLIW are instruction sets that are not implemented in commercial processors. RISC: Reduced Instruction Set Computer; simplifies the processor by only implementing instructions that are frequently used in programs. The RISC has reduced instruction set and addressing modes. Also it has a large number of recorders. CISC: Complex Insturction Set Computer; contains instructions which may only be rarely used in practical programs. Also, instructions are with variable length and complex formed. The CISC saves memory. ISA: Instruction Set Architecture; is the part of the computer architecture that is a set of commands implemented by a particular processor that gives direction to hardware devices. The ISA serves as the boundary between software and hardware. And the ISA includes a specification of the set of opcodes, thus it is only visible to the programmer. 3

5 MACHINE LANGUAGE Machine code or machine language is a set of instructions executed directly by a computer's CPU. The complexity of the instruction set depends on the following factors; - Command and data formats - Addresing modes - General-purpose recorders - Opcode definitions - The flow control mechanisms Instruction Types: 1. Data handling and memory operations: -Set a register to a fixed constant value. -Move data from a memory location to a register, or just the opposite. Used to store the contents of a register, result of a computation, or to retrieve stored data to perform a computation on it later. -Read and write data from hardware devices. 2. Arithmetic and logic operations: -Add, subtract, multiply, or divide the values of two registers, placing the result in a register, possibly setting one or more condition codes in a status register. -Perform bitwise operations -Compare two values in registers 3. Control flow operations: -Branch to another location in the program and execute instructions there. -Conditionally branch to another location if a certain condition holds. -Indirectly branch to another location, while saving the location of the next instruction as a point to return to (a call). 4

6 Classification of Instruction Sets 1. CISC: NOTE: MicroCode: There is a ROM memory includes MicroCode that serves the purpose: when a machine code accesses to processor, the processor executes more simple commands separately parts of the code. Advantages of CISC Architecture; The execution of the microprogram is easy. With each instruction is added to the microcode ROM, the CPU starts to become more skilled and it spends less time to execute a given task. The compiler made with this type of architecture does not have to be complicated Disadvantages of CISC Architecture; CPU structure has become more complex with every generation processors. Specially designed instructions are not used often enough. Decreasing of the performance is observed because different instructions need different number of clock cycles. 5

7 2. RISC: RISC architecture is based on three basic principles; All instructions should be executed in a single cycle. It should be accessed to memory only with 'load' and 'store' commands. All execution units should run from hardware without using microcode. Advantages of RISC Architecture; Speed Simple hardware Short design time Complex Instructions CISC processors include "complex" instructions in their instruction set. Some examples of "complex" instructions include; Saving many registers on the stack at once. Moving large blocks of memory. Complex and/or floating-point arithmetic (sine, cosine, square root, etc.). Performing an atomic test-and-set instruction. Instructions that combine ALU with an operand from memory rather than a register. Parts of an Instruction On traditional architectures, an instruction includes an opcode that specifies the operation to perform, such as add contents of memory to register and zero or more operand specifiers, which may specify registers, memory locations, or literal data. The operand specifiers may have addressing modes determining their meaning or may be in fixed fields. Instruction Length -The size of an instruction varies widely, - Processors used in personal computers, mainframes, and supercomputers have instruction sizes between 8 and 64 bits. -The longest possible instruction on x86 is 15 bytes (120 bits). -Within an instruction set, different instructions may have different lengths. RISCs instructions are a fixed length. In other architectures, instructions have variable length. 6

8 Design The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC, which had many different instructions. The second was the RISC, an architecture that uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory/cache efficiency, or simplify programming. Instruction Set Implementation Any given instruction set can be implemented in a variety of ways. All ways of implementing a particular instruction set provide the same programming model, and all implementations of that instruction set are able to run the same binary executables. The various ways of implementing an instruction set give different compositions between cost, performance, power consumption, size, etc. When designing the microarchitecture of a processor, engineers use blocks of "hard-wired" electronic circuitry (often designed separately) such as registers, ALUs etc. Some kind of register transfer language is then often used to describe the decoding and sequencing of each instruction of an ISA using this physical microarchitecture. There are two basic ways to build a control unit to implement this description: 1. Some computer designs "hardwire" the complete instruction set decoding and sequencing. 2. Other designs employ microcode routines and/or tables to do this- typically as on chip ROMs and/or PLAs. Some CPU designs compile the instruction set to a writable RAM or flash inside the CPU. An ISA can also be emulated in software by an interpreter. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready Code Density In early computers, memory was expensive, so minimizing the size of a programwas often central. Thus the combined size of all the instructions needed to perform a particular task, the code density was an important characteristic of any instruction set. Computers with high code density often have complex instructions for procedure entry, parameterized returns, loops etc. However, more typical, or frequent, "CISC" instructions merely combine a basic ALU operation, such as "add", with the access of one or more operands in memory. Certain architectures may allow two or three operands (including the result) directly in memory. Software-implemented instruction sets may have even more complex and powerful instructions. 7

9 RISC were first widely implemented during a period of rapidly growing memory subsystems. They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers. A single RISC instruction typically performs only a single operation, such as an "add" of registers or a "load" from a memory location into a register. Number of operands Examples of instruction set: ADD - Add two numbers together. COMPARE - Compare numbers. IN - Input information from a device, e.g. keyboard. JUMP - Jump to designated RAM address. JUMP IF - Conditional statement that jumps to a designated RAM address. LOAD - Load information from RAM to the CPU. OUT - Output information to device, e.g. monitor. STORE - Store information to RAM. The three most common types of ISA s are: (a) STACK - The operands are implicitly on top of the stack. Advantages: Simple Model of expression evaluation. Short instructions. Disadvantages: A stack can't be randomly accessed. This makes it hard to generate efficient code. The stack itself is accessed every operation and becomes a bottleneck. (b) ACCUMULATOR - One operand is implicitly the accumulator. Advantages: Short instructions. Disadvantages: The accumulator is only temporary storage so memory traffic is the highest for this approach. (c) GENERAL PURPOSE REGISTER - All operands are explicitely mentioned, they are either registers or memory locations. Advantages: Makes code generation easy. Data can be stored for long periods in registers. Disadvantages: All operands must be named leading to longer instructions. 8

10 Implicit operands on stack Ex. C = A + B Push A Push B Add Pop C Good code density; used in 60 s-70 s; now in Java VM The accumulator provides an implicit input, and is the implicit place to store the result. Ex. C = A + B Load R1, A Add R3, R1, B Store R3, c Used before

11 General Purpose Registers General-purpose registers are preferred by compilers - Reduce memory traffic - Improve program speed - Improve code density Usage of general-purpose registers - Holding temporal variables in expression evaluation - Passing parameters - Holding variables GPR and RISC and CISC - RISC ISA is extensively used for desktop, server, and embedded: MIPS, PowerPC, UltraSPARC, ARM, MIPS16, Thumb - CISC: IBM 360/370, an VAX, Intel 80x86 There is no implicit operand One input operand is register, and one in memory - Ex. C = A + B - Load R1, A - Add R3, R1, B - Store R3, C Processors include VAX, 80x86 10

12 Both operands are registers Values in memory must be loaded into a register and stored back - Ex. C = A + B - Load R1, A - Load R2, B - Add R3, R1, R2 - Store R3, C Processors: MIPS, SPARC Lets look at again the assembly code of A = B + C; in all three architectures: Stack Accumulator GPR PUSH A LOAD A LOAD R1,A PUSH B ADD B ADD R1,B ADD STORE C STORE R1,C POP C - - Not all processors can be neatly tagged into one of the above catagories. The i8086 has many instructions that use implicit operands although it has a general register set. Earlier CPUs were of the first 2 types but in the last 15 years all CPUs made are GPR processors. The 2 major reasons are that registers are faster than memory and the registers are easier for a compiler to use. 11

13 References