(Synchronous) Sequential Circuits

Chapter 6 (Synchronous) Sequential Circuits J.J. Shann

Contents 6-1 Sequential Circuit Definitions 6-2 Latches 6-3 Flip-Flops 6-6 Other Flip-Flop Types 6-4 (Sync.) Sequential Circuit Analysis 6-5 (Sync.) Sequential Circuit Design 6-7 HDL Representation for Sequential Circuits VHDL ( ) 6-8 HDL Representation for Sequential Circuits Verilog ( ) 6-9 Chapter Summary J.J. Shann 6-2

6-1 Sequential Circuit Definitions Combinational circuit: no memory elements (inputs) (outputs) Sequential circuit: storage elements: devices capable of storing binary information (state) (inputs, present state) (outputs, next state) J.J. Shann 6-3

Logic structures for storing information: E.g.s: J.J. Shann 6-4

Types of Sequential Circuits Classification: depends on the timing of their signals. Two main types: 1. Synchronous seq ckt: Its behavior can be defined from the knowledge of its signals at discrete instants of time. Storage elements: e.g., flip-flops 2. Asynchronous seq ckt: ( 補充資料 ) Its behavior depends upon the input signals at any instant of time and the order in which the inputs change. Storage elements: e.g., latches, feedback paths Disadv.: may be unstable & difficult to design J.J. Shann 6-5

Synchronous Sequential Circuits Clocked seq ckts: most commonly used sync seq ckts is syn seq ckts that use clock pulses in the inputs of storage elements has a master-clock generator to generate a periodic train of clock pulses The clock pulses are distributed throughout the system. Storage elements are affected only w/ the arrival of each pulse. Adv.: seldom manifest instability problems Storage elements: flip-flops flip-flop: a binary cell capable of storing one bit of information The state of a flip-flop can change only during a clock pulse transition. The transition from one state to the next occurs only at predetermined time intervals dictated by the clock pulses. J.J. Shann 6-6

Block diagram of a clocked sequential ckt: J.J. Shann 6-7

6-2 Latches Latches: are asynchronous seq ckts are the basic ckts from which all flip-flops are constructed J.J. Shann 6-8

A. SR and SR Latches SR latch SR latch SR latch w/ control input J.J. Shann 6-9

SR Latch SR latch: w/ NOR gates Useful states: Set state: Q = 1, Q = 0 Reset state: Q = 0, Q = 1 Undefined states: Q = Q J.J. Shann 6-10

Logic simulation of SR latch behavior S R Q + 0 0 No change (Q + = Q) 0 1 Reset (Q + = 0) 1 0 Set (Q + = 1) 1 1 Indeterminate Q + : next state of Q J.J. Shann 6-11

S R Latch S R latch: w/ NAND gates J.J. Shann 6-12

S R Q + 1 1 No change (Q + = Q) 1 0 Reset (Q + = 0) 0 1 Set (Q + = 1) 0 0 Indeterminate J.J. Shann 6-13

SR Latch w/ Control Input SR latch w/ control input: The indeterminate condition makes this ckt difficult to manage & it is seldom used in practice. It is an important ckt (other latches & flip-flops are constructed from it) J.J. Shann 6-14

B. D Latch D latch D latch w/ transmission gates J.J. Shann 6-15

D Latch D latch (w/ control input): Disadv. of a latch w/ control input: The state of latch may keep changing for as long as the control input stays in the active level. J.J. Shann 6-16

D latch w/ transmission gates: J.J. Shann 6-17

6-3 Flip-Flops Flip-flop vs. Latch: Latch w/ control input: can change state in response to the inputs anytime the control input is in the active level. The latch is controlled by the level of its control input. Flip-flop: responses only to a transition of a triggering input called the clock. Positive-edge trigger: 0 1 Negative-edge trigger: 1 0 J.J. Shann 6-18

Clock response in latch & flip-flop: J.J. Shann 6-19

Latch Flip-flop: 1. Master-slave flip-flop: pulse-triggered f-f Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing. 2. Edge-triggered flip-flop: Produce a flip-flop that triggers only during a signal transition, and is disabled during the rest of the clock pulse duration. J.J. Shann 6-20

A. Master-Slave Flip-Flops SR master-slave flip-flop: J.J. Shann 6-21

Logic simulation of an SR master-slave flip-flop: J.J. Shann 6-22

Master-slave D f-f Negative edge-triggered D flip-flop Positive edge-triggered D flip-flop J.J. Shann 6-23

B. Edge-Triggered Flip-Flop Master-slave f-f Edge-triggered f-f Negative edge-triggered D flip-flop Positive edge-triggered D flip-flop J.J. Shann 6-24

Timing Setup time: the minimum time for which the D input must be maintained at a constant value prior to the occurrence of the clock transition Hold time: the minimum time for which the D input must not change after the application of the positive transition of the clock Propagation delay time: the time interval b/t the trigger edge and the stabilization of the output to a new state J.J. Shann 6-25

C. Flip-Flop Timing Clock pulse width, t w Setup time, t s Hold time, t h Propagation delay times, t PHL, t PLH, t pd J.J. Shann 6-26

D. Standard Graphics Symbols J.J. Shann 6-27

E. Direct Inputs Direct inputs: asynchronous inputs are used to force the flip-flop to a particular state independent of the clock. When power is turned on in a digital system, the state of the flipflops is unknown. The direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation. Types of direct inputs: Preset: direct set, sets the f-f to 1 Clear: direct reset, sets the f-f to 0 J.J. Shann 6-28

E.g.: D f-f w/ direct set and reset J.J. Shann 6-29

6-6 Other Flip-Flop Types JK flip-flop T flip-flop J.J. Shann 6-30

J-K Flip-Flop JK flip-flop J.J. Shann 6-31

T Flip-Flop J.J. Shann 6-32

Flip-Flop Logic, Characteristic Tables & Equations, and Excitation Tables J.J. Shann 6-33

6-4 (Sync) Sequential Circuit Analysis Synchronous seq ckt: includes f-fs w/ the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt The behavior of a seq ckt is determined from the inputs, outputs, and present state of the ckt. Analysis of a seq ckt: obtain a suitable description that demonstrates the time sequence of inputs, outputs, and states J.J. Shann 6-34

A. Analysis w/ D Flip-Flops E.g. 1: J.J. Shann 6-35

<Analysis> 1. Flip-flop input equations & Output equations: D A = AX + D B = AX Y = (A + B)X BX 2. Next state equation: A( t + 1) = DA = AX + B( t + 1) = D = B AX BX J.J. Shann 6-36

3. State table: Next state equations: Output equations: A ( t + 1) = AX + B ( t + 1) = AX Y = AX + BX BX J.J. Shann 6-37

(One-dimensional) State table Two-dimensional state table 1 J.J. Shann 6-38

input/output 4. State diagram: X/Y 0/0 1/0 1 00 01 0/1 0/1 0/1 1/0 1/0 10 1/0 11 J.J. Shann 6-39

Example 2 E.g. 2: 1. Flip-Flop input equations & Output equations: D A = A X Y Z = A 2. Next-state equation: A + = D A = A X Y J.J. Shann 6-40

3. State table: A + Z = A = A X Y 4. State diagram: 01, 10 00, 11 0/0 1/1 00, 11 01, 10 J.J. Shann 6-41

補充資料 :Analysis w/ JK Flip-Flops Example: J.J. Shann 6-42

1. Flip-flop input equations & Output equations: J A = B K A = B x J B = x K B = A x + A x = A x 2. Next state equations: A + = J A A + K A A = A B + A B + A x B + = J B B + K B B = B x + A B x + A B x J.J. Shann 6-43

3. State table: A + = A B + A B + A x B + = B x + A B x + A B x J.J. Shann 6-44

4. State diagram 00 11 01 10 J.J. Shann 6-45

B. Mealy Model vs. Moore Model Mealy model: is a model of seq ckts in which the outputs depend on both the inputs and the present states. X i Inputs Combinational Logic for Outputs and Next State Z k Outputs State Register Clock State Feedback E.g. 1: J.J. Shann 6-46

E.g. 1: Y = (A + B)X J.J. Shann 6-47

Moore model: is a model of seq ckts in which the outputs depend only on the present states. State Register X Inputs i Combinational Logic for Next State (Flip-flop Inputs) Comb. Logic for Outputs Z k Outputs Clock state feedback E.g. 2: J.J. Shann 6-48

E.g. 2: Z = A J.J. Shann 6-49

Comparison: Moore model: The outputs of the ckt are synchronized w/ the clock. ( the outputs depend on only flip-flop outputs that are synchronized w/ the clock) Mealy model: The outputs may change if the inputs change during the clock cycle. Moore-model State Register Mealy-model X Inputs i Combinational Logic for Next State (Flip-flop Inputs) Comb. Logic for Outputs Z Outputs k X Inputs i Combinational Logic for Outputs and Next State Z Outputs k Clock State Register Clock State Feedback state feedback J.J. Shann 6-50

C. Sequential Circuit Timing Analysis of a seq ckt: analyze the function of the ckt analyze the performance of the ckt max input-to-output delay the max clock frequency, f max, at which the ckt can operate clock frequency f= 1/t p, t p : the clock period f max = 1/t p-min, t p-min : the min allowable clock period J.J. Shann 6-51

Sequential Circuit Timing Parameters Sequential ckt timing parameters: i. f-f propagation delay: t pd,ff ii. comb logic delay through the chain of gates along the path: t pd,comb iii. f-f setup time: t s (iv. slack time, t slack : the extra time allowed in the clock period beyond that required by the path) J.J. Shann 6-52

For edge-triggered flip-flops: determine the longest delay from the triggering edge of the clock to the next triggering edge of the clock. J.J. Shann 6-53

For pulse-triggered flip-flops: J.J. Shann 6-54

Sequential Circuit Timing Paths Sequential ckt timing paths: t i : the latest time that the input changes after the positive clock edge t o : the latest time that the output is permitted to change prior to the next clock edge J.J. Shann 6-55

Propagation delay for a path of type P FF,FF : tp = tslack + (tpd,ff + tpd,comb + t = p max (tpd,ff + tpd,comb + ts ) tp,min t s ) J.J. Shann 6-56

Example 6-1: Clock Period and Frequency Calculations Example 6-1: Suppose that all f-fs used are the same and have t pd = 0.2 ns and t s = 0.1 ns. Then the longest path beginning and ending w/ a f-f will be the path w/ the largest t pd,comb. Further, suppose that the largest t pd,comb is 1.3 ns and that t p has been set to 1.5 ns. <Ans.> 1.5 ns = t + 0.2 + 1.3+ 0.1 = tslack tslack =.1ns (contradiction w/ t p is too small t t 1.6 ns 1.6 ns slack + 0 tslack p p,min = f max = 1/1.6 ns = 625 MHZ 0) J.J. Shann 6-57

Discussion If t p is too large to meet the ckt specifications: employ faster logic cells or change the ckt design to reduce the problematic path delays through the ckt Hold time: t h does not appear in the clock period equation. relates to another timing constraint equation dealing w/ one or both of 2 specific situations: output changes arrive at the inputs of one or more f-fs too soon the clock signals reaching one or more f-f are somehow delayed (clock skew) J.J. Shann 6-58

D. Simulation Sequential ckt simulation: The input patterns must be applied in a sequence. There must be some means to place the ckt in a known state. Observe the state to verify correctness. Deal with the timing of application of inputs and observation of outputs relative to the active clock edge. Function simulation Objective: determination or verification of the function of the ckt Assumption: Ckt components has no delay or a very small delay. Timing simulation Objective: verification of the proper op of the ckt in terms of timing Ckt components has realistic delays. J.J. Shann 6-59

Simulation timing: J.J. Shann 6-60

6-5 (Sync) Sequential Circuit Design Design procedure: 1. Specification: Write a specification for the ckt. 2. Formulation: Obtain either a state diagram or state table from the statement of the problem. (correctness) * State reduction: Reduce the # of states if necessary. 3. State assignment: Assign binary codes to the states and obtain the binary-coded state table. 4. Flip-flop input equation determination: Select the flipflop type or types. Derive the flip-flop input equations from the next-state entries in the encoded state table. 5. Output equation determination: Derive output equations from the output entries in the state table. J.J. Shann 6-61

6. Optimization: Optimize the flip-flop input equations and output equations. 7. Technology mapping: Draw a logic diagram of the ckt using flip-flops, ANDs, ORs, and inverters. Transform the logic diagram to a new diagram using the available flip-flop and gate technology. 8. Verification: Verify the correctness of the final design. J.J. Shann 6-62

Initial State Initial state: Async and sync reset for D flip-flops J.J. Shann 6-63

Example 6-2 E.g.: Sequence recognizer of 1101 Problem description: Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1, regardless of where it occurs in a sequence. Otherwise, Z equals 0. The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros. J.J. Shann 6-64

State diagram: (cont d) J.J. Shann 6-65

State table: J.J. Shann 6-66

Example E.g.: Sequence detector of three or more consecutive 1 s (Moore-type) Design a ckt that detects three or more consecutive 1 s in a string of bits coming through an input line. <Ans> State table: State diagram Present Input Next Output state x state y S 0 0 S 0 0 S 0 1 S 1 0 S 1 0 S 0 0 S 1 1 S 2 0 S 2 0 S 0 0 S 2 1 S 3 0 S 3 0 S 0 1 S 3 1 S 3 1 J.J. Shann 6-67

Example 6-3 E.g.: Finding a state diagram for a BCD-to-excess-3 decoder Formulation: Sequence tables for code converter J.J. Shann 6-68

State diagram: (cont d) J.J. Shann 6-69

Flip-Flop Excitation Tables Select the flip-flop type or types Flip-flop excitation tables: (p.6-51) J.J. Shann 6-70

Designing Using D Flip-Flops Example 6-2: Sequence detector State diagram: State table: J.J. Shann 6-71

State assignment: A = 00, B = 01, C = 11, D = 10 Binary coded state table: J.J. Shann 6-72

Excitation table of D f-f F-F input eqs & output eq: A( t + 1) = DA( A, B, X ) = Σm(3,6,7) B( t + 1) = DB ( A, B, C) = Σm(1,3,5,7) Z( A, B, X ) = Σm(5) J.J. Shann 6-73

Logic diagram: D A = AB + BX D B = X Z = ABX J.J. Shann 6-74

Designing w/ Unused States Example: State table: 3 unused states 000 110 111 J.J. Shann 6-75

Maps for optimizing flip-flop input equations: J.J. Shann 6-76

Logic diagram: D A = AX + BX + B C D B = A C X + A B X D C = X J.J. Shann 6-77

Verification Verification of sync seq ckts: show that the ckt produces the original state diagram or state table used states unused states Manual verification: for small ckts analyze the ckt Verification w/ simulation requires a sequence of input combinations and applied clocks J.J. Shann 6-78

Example 6-4 E.g.: Verifying the sequence recognizer Test generation for simulation J.J. Shann 6-79

Simulation J.J. Shann 6-80