Unit-1 1. Show Karnaugh map for equation Y = F(A,B,C) = S m(1, 2, 3, 6, 7) 2. Show Karnaugh map for equation Y = F(A,B,C,D) = S m(1, 2, 3, 6, 8, 9, 10, 12, 13, 14) 3. Give SOP form of Y = F(A,B,C,D) = M(0, 3, 4, 5, 6, 7, 11, 15) 4. Draw Karnaugh map of Y = F(A,B,C,D) = M(0, 1, 3, 8, 9, 10, 14, 15) 5. Simplify to give POS form by grouping zeros in Karnaugh map for equation given in problem 3. 6. Simplify to give POS form by grouping zeros in Karnaugh map for equation given in problem 4. 7. Get simplified expression of Y = F(A,B,C,D) = S m(1, 2, 8, 9, 10, 12, 13, 14) using Quine- McClusky 8. method. 9. Get simplified expression of Y = F(A,B,C,D,E) = S m(0, 1, 2, 3, 4, 5, 12, 13, 14, 26, 27, 28, 29, 30) using Quine-McClusky method. 10. Prove the following Boolean identities using the laws of Boolean algebra: (i) (A + B)(A + C) = A + BC (ii) ABC + ABC + ABC = A(B + C) 11. Perform the following operations using the 2 s complement method: (i) 23 48 (ii) 48 23 12. Implement the following function using a 3 line to 8 line decoder. S (A,B,C) = m(1,2,4,7) C (A,B,C) = m ( 3,5,6,7) 13. Design a 32:1 multiplexer using two 16:1 multiplexers and a 2:1 multiplexer 14. Reduce the following equation using k-map Y = ABC+ ACD + AB+ ABCD + ABC 15. Minimise the logic function F (A,B,C, D) = Π M ( 9, 8, 3, 2, 1, 10,11,14) + d ( 15 7, ) Use Karnaugh map. Draw the logic circuit for the simplified function using NOR gates only. 16. Prove the following identities using Boolean algebra: (i) (A + B)(A + AB)C + A(B + C) + AB + ABC = C(A + B) + A(B + C). (ii) A( ) A B B( ) A B = A B. 17. Subtract 27 from 68 using 2 s complements. 18. Design a 4 to 1 Multiplexer by using the three variable function given by F(A,B,C) = m (1,3, 5, 6) 19. Minimize the following logic function using K-maps and realize using NAND and NOR gates. F(A,B,C,D) = m( 1, 3,5, 8,9,11,15) + d(2,13) 20. Prove the following equations using the Boolean algebraic theorems: (i) A + A.B + A. B = A + B (ii) ABC + A B C + ABC + ABC = AB + BC + AC 21. Perform the following subtraction using 1 s complement (i) 11001 10110 (ii) 11011 11001 22. Convert (177.25) 10 to octal. 23. Design a BCD to excess 3 code converter using minimum number of NAND gates. Hint: use k map techniques
24. Reduce the following equation using k-map Y = D C B + B A D C + A D C B + D C B A + A D 25. Prove the following identities (i) C B A + C B A + A C B + A C B = C (ii) A B+ A C B + B A + A C B = B+ A C 26. What is code? Explain the types of binary codes. Design a BCD to Excess-3code converter. 27. Implementation the following POS expression using NOR-NOR logic. F = ПM(0,1,2,4,6) 28. Minimize the following using Tabular method f(a, b, c, d, e)= m(0,1,9,15,24,29,30) + d(8,11,31) 29. Minimize the following using K-map method. f(a, b, c, d, e)= m(0,4,8,12,16,18,20,22) + d(24,26,28,30,31)
Unit-2 30. Explain the working of a demultiplexer with the help of an example. 31. Design a BCD to seven segment decoder that accepts a decimal digit in BCS and generates the appropriate output for segments in display indicator 32. With the help of a truth table explain the working of a half subtractor. Draw the logic diagram using gates. 33. Draw the logic diagram of a full subtractor using half subtractors and explain its working with the help of a truth table 34. What is a demultiplexer? Discuss the differences between a demultiplexer and a decoder 35. Explain the operation of octal to binary encoder. 36. Design a 4 : 1 multiplexer with strobe input using NAND gates. 37. What is parity generator and checker? Describe five bit even parity checker 38. What is parallel adder? Draw and explain block diagram for 4 bit parallel adder 39. Explain the operation of 8:1 multiplexer 40. What is meant by a priority encoder? Name the 7400 series TTL chip which is a priority encoder. Write its truth table. Illustrate how it can be used as a decimal-to-bcd encoder. 41. What is a digital multiplexer? Illustrate its functional diagram. Write the scheme of a 4- input multiplexer using basic gates (AND/OR/NOT) and explain its operation. 42. What are the characteristics of digital ICs used to compute their performance? 43. Distinguish between combinational logic circuits and sequential logic circuits. How are the design requirements of combinational circuits specified? 44. Explain the following characteristics for digital IC s. (i) Propagation delay (ii) Power dissipation 45. What is a Decoder? Compare a decoder and a demultiplexer with suitable block diagrams. 46. Draw the logic diagram of 4-bit odd parity checker using EX-NOR gates and explain its operation with the help of Truth table 47. What is a digital comparator. Explain the working of a 2-bit digital comparator with the help of Truth Table 48. Design a circuit that realizes following two functions using a decoder and two OR gates. 49. F1(A,B)=S m(0,3) and F2(A,B)=S m(1,2) 50. What is ripple carry adder? 51. What is look ahead carry adder 52. What is Decimal adder? 53. What is magnitude comparator? 54. Draw the diagram of 4 bit adder/subtractor. 55. What is Multiplexer and Demultiplexer. 56. Explain the working of 4-bit decimal adder. 57. Design the circuit for 4-bit by 3-bit binary multiplier.
Unit-3 58. The clock and the input waveforms shown below are applied to the D input of a positive edge triggered D flipflop. Sketch the output waveforms. 59. The clock and the input waveforms shown below are applied to the D input of a positive edge triggered D flipflop. Sketch the output waveforms. 60. How is it possible to make a modulo 2n counter using N-flipflops? Name the two types of such counters. 61. What is a flip-flop? Write the truth table for a clocked J-K flip-flop that is triggered by the positive-going edge of the clock signal. Explain the operation of this flip-flop for the following conditions. Initially all inputs are zero and assume the Q output to be 1. 62. Draw the logic diagram of 4-bit Twisted Ring counter and explain its operation with the help of timing diagram. 63. What is a Shift Register? What are its various types? List out some applications of Shift Register. 64. Define a register. Construct a shift register from S-R flip-flops. Explain its working. 65. Give the truth table of S-R and D-flipflops. Convert the given S-R flipflop to a D-flipflop. 66. What are synchronous counters? Design a Mod-5 synchronous counter using J-K Flip-Flops. 67. Draw the circuit diagram of a Master-slave J-K flip-flop using NAND gates. What is race around condition? How is it eliminated in a Master-slave J-K flip-flop. 68. What is a flip-flop? What is the difference between a latch and a flip-flop? List out the application of flip-flop. 69. With relevant diagram explain the working of master-slave JK flip flop. 70. Using D-Flip flops and waveforms explain the working of a 4-bit SISO shift register. 71. With the help of clocked JK flip flops and waveforms, explain the working of a three bit binary ripple counter. Write truth table for clock transitions. 72. With the help of a suitable diagram, explain how do you convert a JK flipflop to T type flipflop. 73. Convert T flip-flop to D flip-flop. 74. Convert SR flip-flop to T flip-flop. 75. With the help of a suitable diagram, explain how do you convert a JK flipflop to T type flipflop. 76. Write short note on the following: Johnson counter. 77. Explain how a shift register can be used as a ring counter giving the wave forms at the output of the flipflops. 78. Define a register. Construct a shift register from S-R flip-flops. Explain its working. 79. Design a modulo-3 counter using D flip-flop that counts as 01 10 11. The unused state 00 goes to 01 at next clock trigger.
80. Design a modulo-5 counter using D flip-flop the unused states of which go to one of the valid counting state at next clock trigger. 81. Design a circuit using JK flip-flop that behaves both as a modulo-5 and modulo-3 counter depending on how it I initialized. 82. Design a modulo-8 counter (a) using SR flip-flop and (b) using T flip-flop. 83. 76. Design a sequence generator with minimum number of flip-flops that generates sequence 110001 repetitively. 84. Define Various Types of Operating Modes in Resistor with neat and clean diagram. 85. Define the classification of Memory. 86. What is Lock out condition in counter and how can be overcome 87. Explain the Operating modes of Universal shift register with neat and clean diagram. 88. Explain the working of Ring and Johnson counter with neat and clean diagram. 89. Design a counter using following count sequences (2, 3, 4, 5, 6) and return to two. 90. Design a 3-bit binary up/down counter with a direction control M, use J-K flip-flop and T flip-flop. 91. Design a BCD to Excess-3 code converter and implement it using a suitable PLA. 92. Explain 4-bit Magnitude Comparator with logic diagram. 93. Explain Encoder and Decoder Circuit with any suitable example. 94. Design 16:1 Multiplexer using (i) 4:1 Multiplexer (ii) 8:1 Multiplexer 95. Implement F(A, B, C, D) = m(0, 1, 3, 4, 7, 8, 9, 11, 14, 15) using (i) 8:1 Mux (ii) 4:1 Mux
Unit-4 96. Design a sequence generator with minimum number of flip-flops that generates sequence 10110001 repetitively. 97. The capacity of 2K 16 PROM is to be expanded to 16 K 16. Find the number of PROM chips required and the number of address lines in the expanded memory. 98. Explain briefly, why dynamic RAMs require refreshing? 99. Draw the logic diagram of 16-bit ROM Array and explain its principle of operation. 100. What is ROM? Is the ROM a volatile memory? Explain. 101. Distinguish between ROM, PROM, EPROM, EEPROM 102. Difference between static and dynamic RAM. Draw the circuits of one cell of each and explain its working. 103. Compare the memory devices RAM and ROM. 104. Why data integrity of optical memory is better than magnetic memory? 105. What is the data transfer rate of a 52X CD-ROM drive? 106. Briefly explain Read, Write, Erase process of CD-RW media. 107. What is the data transfer rate of 8X DVD-ROM drive? 108. What is PLA and explain its working. 109. What is PAL and explain its working. 110. What is ASMs and explain the basic elements of ASM.
Unit-5 111. write the difference between synchronous and asynchronous sequential circuit. 112. Draw the circuit diagram of Asynchronous decade counter and explain its working. 113. State the condition of stability in asynchronous sequential logic 114. Draw state transition diagram of synchronous sequential logic circuit using Mealy Model that detects 115. three consecutive zeros from an input data stream, X and signals detection by making output, Y=1. 116. Using Moore Model draw state transition diagram of the circuit that generates a single pulse of width equal to clock period when enabled by E=1. The circuit is reset by E=0 at any stage. 117. Draw state transition diagram of sequence detector circuit that detects 1101 from input data stream using both Mealy and Moore Model. 118. Explain the difference between Mealy and Moore model of sequential circuit. 119. Using Moore Model draw state transition diagram of a serial parity checker circuit. If the number of 1 s received at input X is even, parity checker output, Y=0. If odd number of 1 s are received at X then Y=1. 120. What are races and cycles? 121. Define critical race and non critical race. 122. Write short notes on shared row state assignment 123. Write short notes on one hot state assignment. 124. What is the significance of state assignment? 125. What are the difference between fundamental and pulse mode sequential circuit? 126. What are the conditions for static hazards? 127. Explain hazards asynchronous sequential logic circuit.