High-K K Dielectric Materials In Microelectronics

Similar documents
Implementation Of High-k/Metal Gates In High-Volume Manufacturing

Advanced VLSI Design CMOS Processing Technology

Intel s Revolutionary 22 nm Transistor Technology

Nanotechnologies for the Integrated Circuits

Chapter 7-1. Definition of ALD

Chapter 1 Introduction to The Semiconductor Industry 2005 VLSI TECH. 1

A Study on the Reliability of Metal Gate La2O3 Thin Film Stacked Structures

Unternehmerseminar WS 2009 / 2010

Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics

CONTENTS. Preface Energy bands of a crystal (intuitive approach)

MOS (metal-oxidesemiconductor) 李 2003/12/19

DEVELOPMENTS & TRENDS IN FEOL MATERIALS FOR ADVANCED SEMICONDUCTOR DEVICES Michael Corbett mcorbett@linx-consulting.com Semicon Taiwan2015

Winbond W971GG6JB-25 1 Gbit DDR2 SDRAM 65 nm CMOS DRAM Process

Introduction to VLSI Fabrication Technologies. Emanuele Baravelli

DESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET TRANSISTORS

Class 18: Memories-DRAMs

STMicroelectronics. Deep Sub-Micron Processes 130nm, 65 nm, 40nm, 28nm CMOS, 28nm FDSOI. SOI Processes 130nm, 65nm. SiGe 130nm

EE-612: Nanoscale Transistors (Advanced VLSI Devices) Spring 2005

Modeling the Characteristics of a High-k HfO 2 -Ta 2 O 5 Capacitor in Verilog-A

Evaluating Embedded Non-Volatile Memory for 65nm and Beyond

Lezioni di Tecnologie e Materiali per l Elettronica

ADVANCED WAFER PROCESSING WITH NEW MATERIALS. ASM International Analyst and Investor Technology Seminar Semicon West July 15, 2015

DESIGN CHALLENGES OF TECHNOLOGY SCALING

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

New Ferroelectric Material for Embedded FRAM LSIs

The MOSFET Transistor

Fabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors

Sputtered AlN Thin Films on Si and Electrodes for MEMS Resonators: Relationship Between Surface Quality Microstructure and Film Properties

Flash Memories. João Pela (52270), João Santos (55295) December 22, 2008 IST

CS257 Introduction to Nanocomputing

Metal Gate / High-k Reliability Characterization: From Research to Development and Manufacturing. Andreas Kerber, PhD Technology Research Group

T. Suntola: 30 years of ALD ALD 2004, Aug , 2004, University of Helsinki, Finland. 30 years of ALD Tuomo Suntola

What is optical lithography? The optical system Production process Future and limits of optical lithography References. Optical lithography

Damage-free, All-dry Via Etch Resist and Residue Removal Processes

Ultra-High Density Phase-Change Storage and Memory

1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.

Optical Properties of Sputtered Tantalum Nitride Films Determined by Spectroscopic Ellipsometry

Low Power and Reliable SRAM Memory Cell and Array Design

WŝŽŶĞĞƌŝŶŐ > ĞdžƉĞƌŝĞŶĐĞ ƐŝŶĐĞ ϭϵϳϰ WŝĐŽƐƵŶ ^he > Ρ ZͲƐĞƌŝĞƐ > ƐLJƐƚĞŵƐ ƌŝěőŝŷő ƚśğ ŐĂƉ ďğƚǁğğŷ ƌğɛğăƌđś ĂŶĚ ƉƌŽĚƵĐƟŽŶ d, &hdhz K& d,/e &/>D /^, Z

Picosun World Forum, Espoo years of ALD. Tuomo Suntola, Picosun Oy. Tuomo Suntola, Picosun Oy

Intel Q3GM ES 32 nm CPU (from Core i5 660)

Observation of Long Transients in the Electrical Characterization of Thin Film BST Capacitors

Semiconductor doping. Si solar Cell

VLSI Fabrication Process

Yaffs NAND Flash Failure Mitigation

SLC vs. MLC: An Analysis of Flash Memory

Introduction to CMOS VLSI Design

3D NAND Technology Implications to Enterprise Storage Applications

Mass production, R&D Failure analysis. Fault site pin-pointing (EM, OBIRCH, FIB, etc. ) Bottleneck Physical science analysis (SEM, TEM, Auger, etc.

AN1837. Non-Volatile Memory Technology Overview By Stephen Ledford Non-Volatile Memory Technology Center Austin, Texas.

Solar Photovoltaic (PV) Cells

Types of Epitaxy. Homoepitaxy. Heteroepitaxy

A Plasma Doping Process for 3D FinFET Source/ Drain Extensions

Fabrication and Manufacturing (Basics) Batch processes

Thin Is In, But Not Too Thin!

Conductivity of silicon can be changed several orders of magnitude by introducing impurity atoms in silicon crystal lattice.

Magnetic Data Storage and Nanoparticles Ernie Chang

Al 2 O 3, Its Different Molecular Structures, Atomic Layer Deposition, and Dielectrics

Low-cost Printed Electronic Nose Gas Sensors for Distributed Environmental Monitoring

How To Increase Areal Density For A Year

CRYSTAL DEFECTS: Point defects

Graduate Student Presentations

Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms. SOI Consortium Conference Tokyo 2016

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications

Contamination. Cleanroom. Cleanroom for micro and nano fabrication. Particle Contamination and Yield in Semiconductors.

2. Deposition process

IEEE Milestone Proposal: Creating the Foundation of the Data Storage Flash Memory Industry

State-of-the-Art Flash Memory Technology, Looking into the Future

Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis

Grad Student Presentation Topics PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory

OLED display. Ying Cao

COURSE: PHYSICS DEGREE: COMPUTER ENGINEERING year: 1st SEMESTER: 1st

ISOTROPIC ETCHING OF THE SILICON NITRIDE AFTER FIELD OXIDATION.

Improved Contact Formation for Large Area Solar Cells Using the Alternative Seed Layer (ASL) Process

Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.

Low Power AMD Athlon 64 and AMD Opteron Processors

Preliminary Evaluation of Data Retention Characteristics for Ferroelectric Random Access Memories (FRAMs).

How MOCVD. Works Deposition Technology for Beginners

From sand to circuits How Intel makes integrated circuit chips. Sand with Intel Core 2 Duo processor.

AC coupled pitch adapters for silicon strip detectors

ALD from Lab to Fab Atom Level Control for Industrial Thin Films Kokkola Material Week September 23, 2014

Supercapacitors. Advantages Power density Recycle ability Environmentally friendly Safe Light weight

Study of tungsten oxidation in O 2 /H 2 /N 2 downstream plasma

Simulation of Gate Leakage Currents in UTB MOSFETs and Nanowires Andreas Schenk ETH Zurich

Following a paper that I wrote in 1965 and a speech that I gave in

Ultra Low Profile Silicon Capacitors (down to 80 µm) applied to Decoupling Applications. Results on ESR/ESL.

Dependence of the thickness and composition of the HfO 2 /Si interface layer on annealing

Spectroscopic Ellipsometry:

Chapter 6 Metal Films and Filters

Microstockage d énergie Les dernières avancées. S. Martin (CEA-LITEN / LCMS Grenoble)

Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage

4 th Workshop on Innovative Memory Technologies

MRF175GU MRF175GV The RF MOSFET Line 200/150W, 500MHz, 28V

CHAPTER 10 Fundamentals of the Metal Oxide Semiconductor Field Effect Transistor

Introduction OLEDs OTFTs OPVC Summary. Organic Electronics. Felix Buth. Walter Schottky Institut, TU München. Joint Advanced Student School 2008

Transcription:

High-K K Dielectric Materials In Microelectronics NAME: Neha Tomar IIT GUWAHATI

INTRODUCTION OUTLINE MOORE S S LAW AND TRANSISTOR SCALING WHY HIGH-K K DIELECTRICS? APPLICATIONS IN MICROELECTRONICS HIGH-K K DIELECTRICS IN DRAMS HIGH-K K GATE DIELECTRICS SUMMARY

INTRODUCTION MOORE S S LAW A prediction made by Mr. Gordon Moore that the number of transistors on a chip double every two years.

INTRODUCTION Transistor physical gate length will reach ~15nm before end of this decade, and ~10nm early next decade

INTRODUCTION PROBLEM AS TRANSISTOR IS MADE SMALLER. Gate dielectric,silicon dioxide are only a few atomic layers thick now. Leakage current increases, as thickness decreases. A New dielectric material is needed to reduce leakage current. HIGH-K K DIELECTRICS IN MICROELECTONICS

INTRODUCTION WHAT ARE HIGH-K MATERIALS? Thicker class of material known as High-K is likely to replace Silicon oxide. K stands for dielectric constant, a measure of how much charge a material can hold. HIGH-K K DIELECTRICS IN MICROELECTONICS

INTRODUCTION HIGH-K MATERIAL BENEFITS Sio2 High-k Capacitance 1* 1.6* Leakage 1* < 0.01* HIGH-K K DIELECTRICS IN MICROELECTONICS

HIGH-K GATE STACKS TRANSISTOR A simple switch Current flows source to drain when a certain Voltage is applied on The gate, otherwise Doesn t flow. Schematic of important regions Of field effect transistor gate stack

HIGH-K GATE STACKS Scaling limits for current Gate Dielectrics Silicon dioxide is current gate dielectrics Sio2 thickness can t be decreased less than 1-1.5nm, because leakage current increases So, Continual scaling. will require high-k material for dielectric layer.

HIGH-K GATE STACKS ALTERNATIVE HIGH-K GATE DIELECTRICS Metal oxides of ZrO2, HfO2, Y2O3 and Al2O3 High-K material Dielectric constant Leakage Current reduction Thermal stability Tmax c ZrO2 ~23 *10 4-10 ~900 HfO2 ~20 *10 4-10 5 ~950 Y2O3 ~15 *10 4-10 5 Silicate formation Al2O3 ~10 *10 2-10 3 ~1000

HIGH-K GATE STACKS ALTERNATIVE HIGH-K GATE DIELECTRICS Pseudo binary materials (HfO2) x (SiO2) 1-x and (ZrO2) x (SiO2) 1-x Silicate-Si interface is chemically similar to the SiO2-Si Interface. Low defect densities Hf-silicate between Si layer

HIGH-K GATE STACKS ALTERNATIVE HIGH-K GATE DIELECTRICS Pseudo binary materials (HfO2) x (SiO2) 1-x and (ZrO2) x (SiO2) 1-x Silicate-Si interface is chemically similar to the SiO2-Si Interface. Low defect densities Hf-silicate between Si layer

HIGH-K GATE STACKS KEY GUIDELINES FOR SELECTING AN ALTERNATIVE GATE DIELECTRIC Interface quality Permittivity and band gap Thermodynamic stability Compatibility with the current or expected materials to be used in processing for CMOS devices Reliability

HIGH-K GATE STACKS PROCESS ISSUES THAT AFFECT DEVICE Pre-deposition treatments HF last,o 3 etc. Pre/post-deposition annealing O 2 and N 2 annealing etc. High-k deposition ALD,CVD etc. Gate electrode metal gates, poly-silicon gates etc.

HIGH-K GATE STACKS GATE ELECTRODE PROBLEMS WHEN SiO2 IS REPLACED WITH HIGH-K Problems arise due to interaction with the Poly-Si gate Phonon Scattering electrons slow down Threshold voltage pinning-due to defects that arise at the gate-dielectric/gate electrode

HIGH-K DIELECTRICS IN DRAMS GATE ELECTRODE SOLUTION-METAL GATE

HIGH-K GATE STACKS STATE-OF-THE-ART TRANSISTOR Metal gate and high-k dielectric transistor offer the promise toward CMOS Technology nodes. Other technologies are also emerging for low-power and high-performance logic. For example Nanoelectronic devices, SOI, double gate and tri-gate etc.

HIGH-K DIELECTRICS FOR DRAMS WHAT IS DRAM? DRAM is a type of random access memory that stores each bit of data in a separate capacitor.

HIGH-K DIELECTRICS FOR DRAMS The continuous shrinking technology up to Gbit density exposes many challenges. Sio2 can not be made thinner any more. Alternative dielectric having a substantially higher permittivity is needed for further high density DRAMs.

HIGH-K DIELECTRICS FOR DRAMS ALTERNATIVE HIGH-K DIELECTRICS FOR DRAMS Among this, BST film is the most promising capacitor material in future DRAM applications.

HIGH-K DIELECTRICS FOR DRAMS BST capacitor structure with the stacked barrier scheme. Cross-section TEM Image of a stacked-capacitor Structure with a BST dielectric Pt electrode and a TaSiN barrier layer. Minimum feature size=0.2um Dielectric thickness=27 nm

HIGH-K DIELECTRICS FOR DRAMS Factors that influence BST thin film properties Processing methods Film composition Crystalline structure Microstructure Surface morphology Film thickness

HIGH-K DIELECTRICS FOR DRAMS Process Integration Main Points BST deposition techniques Electrode material & Barriers

HIGH-K DIELECTRICS FOR DRAMS Process Integration BST deposition techniques Main techniques MOCVD rf-sputtering

HIGH-K DIELECTRICS FOR DRAMS Process Integration ELECTRODE MATERIAL Noble metals Exp-Pt, Ru etc Low leakage current Conducting Oxides Exp-Iro 2 etc High leakage current

HIGH-K DIELECTRICS FOR DRAMS Process Integration Various integration schemes for BST capacitor

HIGH-K DIELECTRICS FOR DRAMS Last but not least Reliability Time to breakdown Ba0.47Sr0.53TiO3 at various OMR Time to breakdown Ba 0.47 Sr 0.53 TiO 3 Deposited on various electrodes TDDB for various DRAM dielectrics

HIGH-K DIELECTRICS FOR DRAMS High-k dielectrics (BST film ) has become the dielectric material of choice for cell capacitor of the dynamic random access memory devices (DRAMs) having gigabit densities To continue shrinking technology, BST thin films will be a productive field of research and development.

SUMMARY To continue Moore s law for next decades, New materials are needed. High-k dielectrics may ultimately lead to vaster and enable applications. Industry is seeking for new materials and technologies that can replace SiO2 and scaling remains continue.

References 1. H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A Brown, C.D. Young,P.M. Zeitzoff, J. Gutt, P. Lysaght, M.I. Gardner, R.W. Murto High-k gate stacks for planar, scaled CMOS integrated circuits (2003). 2. Cheol Seong Hwang (Ba,Sr)TiO3 thin films for ultra large scale dynamic random access memory. A review on the process integration.(1998) 3. S. Ezhilvalavan, Tseung-Yuen Tseng Progress in the developments of (Ba,Sr)TiO3 (BST) thin films for Gigabit era DRAMs (2000). 4. G. D. Wilk, R. M. Wallaceb, J. M. Anthony High- kgate dielectrics: Current status and materials properties considerations (2001). 5. Ofer Sneh*, Robert B.Clark-Phelps, Ana R.Londer gan, Jereld Winkler, Thomas E.Seidel Thin film atomic layer deposition equipment for semiconductor processing (2002). 6. E.P. Gusev, E. Cartier, D.A. Buchanan, M. Gribelyuk, M. Copel, a H. Okorn-Schmidt, C. D Emic Ultrathin high-k metal oxides on silicon: processing, characterization and integration issues (2001).

References 7. D. E. Kotecki,J. D. Baniecki,H. Shen,R. B. Laibowitz,K. L. Saenger,J. J. Lian,T. M Shaw,S. D. Athavale,C. Cabral, Jr.,P. R. Duncombe,M. Gutsche,G. Kunkel,Y.- J. Park,Y.-Y. Wang,R. Wise (Ba,Sr)TiO3 dielectrics for future stacked capacitor DRAM (1999). 8.Intel s High Gate k/metal Gate Announcement November 4th, 2003. 9.Wilman Tsai and Robert Chau Integration of Metal gate-high k Dielectrics to Extend Transistor Scaling (2004).