Volterra VT1195SF Synchronous Buck Voltage Regulator Process Review with Supplementary TEM Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Process Review with Supplementary TEM Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package 3 Process Analysis 3.1 General Device Structure 3.2 Dielectrics 3.3 Metallization 3.4 Peripheral MOS Transistors 3.5 Isolation 3.6 Wells and Substrate 4 DMOS Switch Transistors 4.1 Overview and Plan-View Analysis 4.2 Cross-Sectional Analysis (Gate Length Direction) 5 Critical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Top Package View 2.1.2 Bottom Package View 2.1.3 Plan-View Package X-Ray 2.1.4 Die Photograph 2.1.5 Die Photograph DMOS Functional Layout 2.1.6 Die Markings 2.1.7 Annotated Die Photograph 2.1.8 Die Corner 2.1.9 Bond Pads 2.1.10 Standard Logic 3 Process Analysis 3.1.1 General Structure 3.1.2 Die Edge and Seal 3.1.3 Die Seal 3.2.1 Passivation 3.2.2 IMD 2 and IMD 1 3.2.3 Pre-Metal Dielectric 3.3.1 Metal 3 3.3.2 Minimum Width Metal 2 3.3.3 Minimum Width Metal 1 3.3.4 Minimum Pitch Via 2s and Via 1s 3.3.5 Minimum Pitch Contacts to Diffusion 3.3.6 Contact to Poly 3.4.1 Peripheral NMOS Transistor 3.4.2 TEM Peripheral Transistor 3.5.1 Isolation Under Poly 3.5.2 Minimum Width Isolation 3.6.1 SRP P-Well and Substrate 3.6.2 SRP Capacitor N-Well 3.6.3 SRP DMOS Transistor N-Well 4 DMOS Switch Transistors 4.1.1 DMOS Transistors at Metal 2 4.1.2 Middle of DMOS Transistor at Metal 2 4.1.3 DMOS Transistors at Poly 4.1.4 Middle of DMOS Transistor at Poly 4.2.1 Source/Drain Areas and Interconnects 4.2.2 P-Body and Drain Contacts Detail 4.2.3 Source/Drain and P-Body Diffusions 4.2.4 Source/Drain Diffusions Detail 4.2.5 TEM DMOS Gate Oxide
Overview 1-2 4.2.6 TEM DMOS Thick Oxide 4.2.7 Silicon Etch DMOS Transistors 4.2.8 SCM DMOS Transistor 4.2.9 Source Diffusions and P-Body SIMS Profile
Overview 1-3 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Package and Die Dimensions 3 Process Analysis 3.2.1 Dielectric Layer Thicknesses 3.3.1 Metal and Contact Dimensions 3.4.1 Peripheral Transistors 3.6.1 Die Thickness and Well Depths 4 DMOS Switch Transistors 4.1.1 DMOS Transistor Dimensions 5 Critical Dimensions 5.0.1 Package and Die Dimensions 5.0.2 Dielectric Layer Thicknesses 5.0.3 Metal and Contact Dimensions 5.0.4 Peripheral Transistors 5.0.5 Die Thickness and Well Depths 5.0.6 DMOS Transistor Dimensions
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