Nanoelektronik: Von der Realität bis zur Utopie

Transcription

1 LNQE-Kolloquium Nanoelektronik: Von der Realität bis zur Utopie Heinrich Kurz Institut für Halbleitertechnik, RWTH-Aachen AMICA - Advanced Microelectronic Center Aachen, AMO GmbH I. Einleitung II. Realität III. Visionen IV. Utopie composed by Matthias Baus RHEINISCH- WESTFÄLISCHE TECHNISCHE HOCHSCHULE AACHEN

2 Economy of Mainstream SERVICES $ 5000 B ELECTRONICS $ 1100 B SEMICONDUCTORS $ 200 B MATERIALS & EQUIP. $ 50 B USA Korea Japan USA Japan EU EU Ranking Company Intel Samsung Electronics Renesas Technology Texas instruments Toshiba STMircoelectronics Infineon Technologies Japan 8 NEC Electronics Large growing market Strong European position Strategic for application markets USA EU 9 10 Motorola Philips Semiconductors Source: Dataquest March 2004

3 Taxonomy of Basic Principles ITRS ERD-Chapter Realität Vision Utopie?

4 REALITÄT

5 Moore s Law Maciek E. Orczyk, IMEC ARRM, Oct. 18, 2005 Gordon Moore (Intel)

6 Evolution: Transistors shipped per year

7 Dimensionsvergleich:. Transistor und menschliches Haar { Transistor gate Trench capacitor 10 µm

8 Evolution: MOSFET-Scaling Source: Intel

9 Dekade of New Materials Source: Intel

10 Crystalline High-k Gate Dielectric 500 C 3,1nm Gd2O3 Aufnahme von Dr. Bugiel, Uni- Hannover (Mitarbeiter von Prof. Osten) Gd2O3epi La2O3Chin Gd2O3Oshima Yb2O3Ohmi Gd2O3Kwo Er2O3 La2O3Huang La2O3Ng La2O3SiO2Licht November 2005: World's first MOSFETs with epitaxial Gd2O3 (AMO, TU-Darmstadt, Uni-Hannover: KrisMOS Projekt) leakage current [Acm -2 ] KrisMOS 0,0 0,5 1,0 1,5 2,0 2,5 3,0 CET [nm]

11 Further Variations M. Ieong, Science, Vol. 306 (2004)

12 AMO/AMICA Precursor: Triangle-Shaped Nanoscale MOSFET Output characteristics of the fabricated triangle-shaped MOSFETs with 1µm and 2µm gate length (left and right side, respectively). I lost the sense of why this work is interesting. Tell me why I am interested in this device (Reviewer comment, JVST-B, 1996) ITRS roadmap prediction 2001: Non-classical CMOS devices: non planar gate, double & triple gate devices on SOI, FinFET, ultra thin body (fully depleted) SOI, vertical transistor J.Gondermann et al A triangle-shaped nanoscale MOS device, JVST B, 14, 6, (1996) New concept for ultra small N-MOSFETs, Microelectronic Eng. 35, 305 (1997) LNQE-Kolloquium Präsentation H. Kurz, IHT RTWH Aachen/AMO

13 AMO/AMICA Realisation Triple-Gate SOI-MOSFET L G =70nm S BOX Gate Source W M =22nm D BOX Gate t Top-Si = 100nm t BOX = 200nm t Oxide = 8nm N Channel = 3e17/cm³ N S/D/G = 1e20/cm³ LNQE-Kolloquium Präsentation H. Kurz, IHT RTWH Aachen/AMO Drain M. Lemme et al., Solid-State Electronics, Vol. 48, 2004

14 AMO/AMICA Intel Tri-gate Transistor 30-60nm Gate-Length That s the reason while we are searching for smaller devices! R. Chau et al., 2002 International Conference on Solid State Devices and Materials, Nagoya, Japan 2002 LNQE-Kolloquium Präsentation H. Kurz, IHT RTWH Aachen/AMO

15 AMO/AMICA The EJFET- concept on SOI n+ MOSFET Source n+ Drain EJ-MOSFET one gate spacer implantation activation n + BOX Substrate p n + two gates intergate oxide electr. extensions implantation activation Electrically induced S/D extensions: shallow junctions relaxed source/drain implantation LNQE-Kolloquium Investigation of MOSFETs in the deca-nanometer regime Präsentation H. Kurz, IHT RTWH Aachen/AMO W. Henschel et al., Solid-State Electronics, Vol 48 (2004)

16 AMO/AMICA The technological realization of the concept L ug Source upper gate W Drain BOX Mesa upper gate intergate oxide cutting line lower gate lower gate L lg After optimizing the critical processes : Poly-Si SiO 2 LNQE-Kolloquium nm EJFET on SOI material W. Henschel et al., Solid-State Electronics, Vol 48 (2004) Präsentation H. Kurz, IHT RTWH Aachen/AMO L lg = 12nm

17 AMO/AMICA 12 nm fully depleted Electrical characterization triple-gate EJFET 1E-5 8 V lg = 3 V 1E-7 6 V lg = 2 V I DS [A] 1E-9 1E-11 V DS = 0.5 V V DS = 0.1 V I DS [A] 4 V lg = 1 V 1E-13 2 V lg = 0 V 1E Lower Gate Voltage V lg [V] 0 0,0 0,5 1,0 1,5 2,0 2,5 3,0 Source/Drain Voltage V ds [V] Output characteristic (The current is not normalized) Transfer characteristic FD Triple-gate EJFET: lightly doped (N A = 1e15cm -3 ) L lg = 12 nm W = 20 nm Current in the off-state: A Ion/Ioff: 10 8 W. Henschel et al., Solid-State Electronics, Vol 48 (2004) LNQE-Kolloquium Präsentation H. Kurz, IHT RTWH Aachen/AMO

18 VISIONEN

19 Components: Opportunities CMOS PLATFORM To 1 Billion Transistors Advanced Computing Architectures Added functions To 22 nm CMOS Sensors, actuators, wet interface Nano-electromechanics electromechanics,, Bio-Nano, Quantum cryptography Ultimate CMOS e - devices Radically new Bridging Nanoelectronics Molecular, Spin, Quantum,???

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24 ICT & Other Sciences

25 UTOPIE

26 Silizium-X-Chromosom