1 Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p- MOSFETs on Negative-Bias Temperature Instability and Study of Defects A. F. Muhammad Alimin, A. A. Mohd Radzi, N. A. F. Sazali, S. F. Wan Muhamad Hatta, N. Soin & H. Hussin Journal of Electronic Materials ISSN Journal of Elec Materi DOI 1.17/s
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3 Journal of ELECTRONIC MATERIALS DOI: 1.17/s Ó 217 The Minerals, Metals & Materials Society Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p-mosfets on Negative-Bias Temperature Instability and Study of Defects A.F. MUHAMMAD ALIMIN, 1 A.A. MOHD RADZI, 1 N.A.F. SAZALI, 1 S.F. WAN MUHAMAD HATTA, 1,3 N. SOIN, 1 and H. HUSSIN 2 1. Department of Electrical Engineering, Faculty of Engineering, University of Malaya, Kuala Lumpur, Malaysia. 2. Faculty of Electrical Engineering, Universiti Teknologi MARA, Selangor, Malaysia Negative-bias temperature instability (NBTI) has become a prominent factor limiting scaling of complementary metal oxide semiconductor technology. This work presents a comprehensive simulation study on the effects of critical design parameters of 32-nm advanced-process high-k p-channel metal oxide semiconductor field-effect transistors on NBTI. The NBTI mechanism and defects were explored for various geometric and process design parameters over a wide range of values. The NBTI simulation method applied in this work follows the on-the-fly method to capture the mechanisms of fast and slow traps. This work illustrates the dependence of the threshold voltage (V th ) degradation on the stress oxide field and stress temperature as well as investigation of the Arrhenius plot for the devices. The temperature insensitivity during short stress time of 1 ms indicates absence of generated defects and presence of preexisting defects. It is also observed that significant defects are generated in the gate stack subsequent to NBTI. The slope obtained from the V th degradation analysis at 1 ks and 375 C shows that changing the SiO 2 interfacial layer thickness affects the V th degradation by 96.16% more than changing the HfO 2 thickness and by 8.67% more than changing the metal gate thickness. It is also found that the NBTI effect depends on process design considerations, specifically the boron concentration in the highly doped drain, the metal gate work function, and the halo doping concentration; it was observed that higher boron dose and high metal work function may lead to higher V th degradation. However, the halo doping concentration in the advanced 32-nm structure has an insignificant effect on NBTI. Key words: High-k, NBTI, defects, MOSFETs, reliability, degradation INTRODUCTION Over recent decades, miniaturization of metal oxide semiconductor field-effect transistor (MOSFET) devices has revolutionized the semiconductor industry, enabling production of extremely complex devices and systems. Scaling of MOSFET devices is important to achieve greater integration density, as compact transistors result in increased functionality, reduced (Received October 22, 216; accepted May 6, 217) power consumption, and faster switching time at reduced cost. However, such scaling of MOSFETs has been shown to result in short-channel effects that degrade device performance, particularly as the technology moves into the deep-submicron region, as reported by key players in the industry. 1 To mitigate this problem, use of high-k oxide has been introduced. 2,3 High-k material is proven to result in improved device performance as well as good thermal stability. Despite its success in reducing leakage current, significant reliability issues emerge when using high-k dielectric, one of which is
4 Alimin, Radzi, Sazali, Hatta, Soin, and Hussin known as negative-bias temperature instability (NBTI). This degradation mechanism has become one of the most prominent limiting factors and is the key reliability issue when scaling complementary metal oxide semiconductor (CMOS) technology. NBTI results in a threshold voltage shift for either negative gate voltage or elevated temperature. Nowadays, most of the semiconductor industry 4 6 has migrated to use of high-k dielectrics in integrated circuits, thus increasing concerns regarding the reliability of electronic devices. Therefore, understanding device reliability has become crucial for foundries and integrated device manufacturers to enable better yield and more reliable endproducts. The growing number of publications addressing reliability characteristics of high-k dielectrics indicates the increasing interest in this area However, it appears that most attention has been paid to modeling and measurements of NBTI. Meanwhile, there is still a lack of understanding regarding how the parameters and fabrication processes of high-k metal gate stack p-channel MOSFETs affect NBTI for deep-sub-nm devices. Understanding the exact mechanism of the hole trap transformation process in each layer of the gate stack is important as this will help researchers to quantify NBTI defect characteristics in order to assess device reliability. Study of the impact of NBTI as a function of design parameters will also help determine security margins during design optimization. This paper presents a comprehensive simulation study on the effect of geometric and process variables of 32-nm advanced-process high-k p-mos- FETs on NBTI. Although a few previous works reported on the dependence of NBTI on the gate stack and corresponding processes, none of them further investigated the effects of advanced geometric features such as spacer length or SiGe pocket depth on NBTI. Such advanced geometric features are another new aspect that must be explored, notably in terms of reliability. Considering this requirement, this work focuses particularly on the effects of such advanced geometric features and process parameters on NBTI, as well as identifying the layer in the gate stack which contributes most to NBTI threshold voltage degradation. DEVICES AND SIMULATION CONDITIONS 32-nm Advanced-Process High-k p-mosfet The Synopsys TCAD Sentaurus simulator 17 was adopted to simulate a 32-nm hafnium-based high-k dielectric with aluminium nitride (AlN) metal gate p-mosfet, as shown in Fig. 1. The devices used were based on a 32-nm gate-first CMOS process flow, following standard manufacturing trends for such submicron devices. This fabrication process includes shallow trench isolation (STI) formation, high-k gate dielectric and metal gate deposition, stress engineering application, as well as use of laser annealing. Implementation of this gate-first CMOS process scheme helps to suppress leakage current, improve drive current, and overcome process-related problems such as ultrashallow junction formation. The laser annealing process was adopted to suppress transient-enhanced dopant diffusion. Figure 2 compares simulation results for the electrical characteristics with experimental data from Yasutake et al. 18 obtained on devices fabricated using processes similar to those considered herein. The simulated device shows good agreement with the experimental data, providing confidence that the simulation model is credible. To study the impact of NBTI for devices with different structures, a wide range of geometric variation was simulated. The geometric parameters that were varied included the thicknesses of the HfO 2 high-k layer (2 nm to 4 nm), SiO 2 interfacial layer (.5 nm to 1 nm), and AlN metal gate (1.8 nm to 6 nm) as well as additional advanced geometrical features including polypitch, spacer length, and SiGe pocket depth. 13,14,19 22 The effect of a specific design parameter on NBTI was investigated by varying each parameter at a time while keeping the others constant. Regarding the process design, the degradation of the device was studied while varying the boron dose of highly doped drain (HDD), metal gate work function, and halo doping concentration. The geometric structure of the device was fixed in order to study solely the impact of such process variations on NBTI. NBTI Simulation Conditions The TCAD software adopts a set of physical models including a hydrodynamic transport model and enhanced Lombardi model 23 with high-k degradation where remote Coulomb scattering (RCS) and remote phonon scattering (RPS) are taken into account. The threshold voltage (V th ) degradation was extracted from the simulation using the on-the-fly (OTF) method 24 to suppress recovery effects during electrical parameter measurements. Application of prestress voltageisnecessary,asitgovernsthegatebiasin setting the initial conditions before the stress stage of the simulation. The NBTI effect was studied at high stress biases with oxide field (E ox )ofapproximately 8 MV/cmto 12 MV/cm and at stress temperatures ranging from room temperature (RT) to 375 K. This work focuses on the properties of as-grown and generated defects, hence stress times from 1 ms to 1 s were investigated. RESULTS AND DISCUSSION Influence of Geometric Variations on NBTI The effect on NBTI may be different for different geometric variations. The effect of geometric variations on NBTI was investigated by extensively varying the geometric properties of the thicknesses of the HfO 2 high-k layer, SiO 2 interfacial layer (IL),
5 Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p-mosfets on Negative-Bias Temperature Instability and Study of Defects Fig. 1. Cross-sectional structure of high-k gate stack. Id (A/μm) Line + symbol : This work Line : Experimental data from Ref  Vg (V) and metal gate layer as well as additional advanced features at the 32-nm technology node, including polypitch, spacer length, and SiGe pocket depth. Figure 2 shows the threshold voltage degradation for different HfO 2, SiO 2, and metal gate thicknesses for stress time of 1 ms, 1 s, and 1 s and different stress temperatures. It has been reported that, at short stress time, specifically 1 ms, NBTI is dominated by hole trapping at preexisting defects. 28,29 The degradation of the threshold voltage, denoted as DV th, is analyzed here. It is apparent from Fig. 3c, f, and i that the preexisting defects are insensitive to temperature and the level of degradation is consistently small for all thicknesses investigated. At stress time of 1 s and beyond, generated defects start to dominate. 28 Generated defects are prone to increase at high temperature for high stress time when looking at the difference between room temperature and stress temperature of 375 K for stress time of 1 s compared with 1 s. However, this difference is distinctly smaller in the metal gate layer. Figure 3 also suggests that the Vd: -1V -.5V Fig. 2. Comparison of I d V g characteristic between simulated device and experimental data. effect of temperature is more significant for smaller than larger thicknesses for stress time of 1 s and 1 s. This finding is consistent with those of previous studies 3 which concluded that, in thinner oxide, the leakage current mechanism is more temperature dependent due to the higher channel surface current caused by either drain-induced barrier lowering (DIBL) or deep channel punchthrough currents, which are aggravated at high temperature. 31 The dependence of the threshold voltage degradation on the HfO 2 and metal gate thicknesses indicates higher degradation for greater thicknesses, while SiO 2 contradicts this observation, with thinner SiO 2 seeming to have higher degradation compared with thicker material. Greater HfO 2 thickness in Fig. 3a, and b shows higher V th shift due to more trapping in the bulk high-k layer. 32 This supports the finding of a considerable amount of defects in the bulk high-k layer, since the degradation is highly dependent on the thickness of the bulk. On the other hand, a thinner SiO 2 interfacial layer leads to greater Vth degradation, which is in contrast to HfO 2 due to the higher fast transient charging (FTC) effect. 14,32 The FTC effect is more important for thinner equivalent oxide thickness (EOT), notably through scaling of the interfacial layer. 33 The tunneling barrier for holes in the bulk is also reduced as the SiO 2 IL thickness is reduced, increasing the probability of defect generation or hole trapping in the oxide bulk. 34 Figure 3 also shows that the Vth degradation increases as the metal gate thickness is increased, confirming results in earlier literature 25,35 where it was found that increasing the gate thickness enhanced nitrogen diffusion to the silicon interface, consequently increasing degradation. Previously reported chemical analysis by time-of-flight (ToF) secondary-ion mass spectrometry (SIMS) measurements 36 to investigate the nitrogen distribution in
6 Alimin, Radzi, Sazali, Hatta, Soin, and Hussin mV mV 14 Ref  HfO2 thickness Ref  (nm) (b) 12.95mV 29.85mV Stress time: 1s (c) (n =.337) (n =.371) (n =.73) (n =.226) (n =.297) (n =.11) -5 Stress time: 1ms HfO2 thickness (nm) mV mV (d) (e) (f) IL thickness Ref  (nm) mV 12.95mV Stress time: 1s (n = -.343) (n = ) (n = ) Ref  (n = -.178) (n = -.544) (n = -.847) -5-1 Stress time: 1ms SiO2 thickness (nm) MG thickness Ref  (nm) (n =.34) 26.11mV (n =.31) 165 (n =.367) 11.1mV (g) (h) (i) Ref  4.14mV 21.2mV Stress time: 1s Stress time: 1ms MG thickness (nm) Fig. 3. V th degradation (DV th ) after stress time of 1 ms, 1 s, and 1 s at different stress temperatures for various values of (a c) HfO 2 thickness, (d f) SiO 2 thickness, and (g i) metal gate thickness. The trend of the results is in agreement with previous works the high-k metal gate stack showed that nitrogen diffuses from metal nitride into the stack during metal nitride and/or poly-si deposition. Bae et al. 37 reported that thicker metal gate resulted in higher interface trap density due to stress from the metal nitride layer subsequent to high-temperature annealing. High-temperature annealing causes the agglomeration effect, where crystallites of metal nitride films begin to build up. Growth of such crystallites will result in elastic deformation, eventually introducing stress into the metal nitride layer. Thinner metal nitride layer would lead to lesser diffusion of nitrogen due to nitrogen deficiency, as discussed in Ref. 38. The slope obtained from Fig. 3 shows that changing the SiO 2 IL thickness affects the V th degradation by 96.16% more than changing the HfO 2 thickness and by 8.67% more than changing the metal gate thickness, for stress temperature of 375 K and stress time of 1 s. Therefore, it can be summarized that the SiO 2 IL appears to make a prominent contribution to the V th degradation. Figure 4 shows the dependence of the oxide field on the thicknesses of the high-k HfO 2, SiO 2 IL, and metal gate layers for stress time of 1 ms and 1 s. The V th degradation is observed to be highly dependent on the oxide field, but this dependence is not affected by the thickness parameters, particularly at lower oxide field. At higher oxide field, the thicknesses of the SiO 2 and metal gate layers seem to influence the threshold voltage shift such that the V th degradation increases substantially as the SiO 2 thickness is reduced or the metal gate thickness is increased. The oxide field is found to be the cause of creation of interface traps during NBTI degradation of pure oxides, 39 suggesting that, for the result shown in Fig. 4, more interface traps are created in thinner SiO 2 and thicker metal gate at higher compared with lower oxide field. The Arrhenius relations for different HfO 2, SiO 2 IL, and metal gate thicknesses are plotted in Fig. 5 to obtain the activation energy (E a ). Figure 5 suggests that the activation energy tends to reduce as the thickness is increased, in good agreement with earlier work. 42 Previous studies 28,43 found that the overall temperature activation is reduced due to hole trapping. As the gate stack thickness is increased, the hole-trapping volume also increases, leading to lower E a. 44 Figure 6 shows the adjusted V th shift when the fast and slow traps are separated. One has to subtract the fast trap contribution in order to obtain the slope corresponding to the longterm degradation processes. 32 The inset shows that the presence of fast traps reduces the time dependence of the overall NBTI. Not much difference in the adjusted V th degradation can be seen between 2 nm and 3 nm HfO 2 in Fig. 6a. Figure 6b shows the adjusted V th degradation for two different SiO 2 IL thicknesses. The difference in the V th shift between.5 nm and.8 nm SiO 2 seems to be more significant at higher oxide field. A similar observation can be made for the metal gate in Fig. 6c, where the difference in the adjusted V th degradation is more pronounced at higher than lower oxide field. These results clearly demonstrate that more slow traps/interface traps are generated in thinner SiO 2 and thicker metal gate thickness at higher oxide field, supporting the finding discussed for Fig. 4.
7 Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p-mosfets on Negative-Bias Temperature Instability and Study of Defects 2. HfO2 thickness: nm 2.2nm 2.5nm 3nm 1.4 4nm Stress time: 1ms. Stress temp: SiO2 thickness: 1.8.5nm 1.6.6nm.7nm 1.4.8nm 1.nm Stress temp: (c) -.2 Stress time: 1ms MG thickness: 1.8 nm 2 nm 3 nm 5 nm 6 nm Stress time: 1ms Stress temp: (e) (b) 4 Stress temp: Additional Advanced Geometrical Features To further investigate the influence of the geometry on NBTI, additional advanced features including polypitch, spacer length, and SiGe pocket depth were varied. Figure 7 shows the stress temperature dependence for different polypitch, spacer length, and SiGe pocket depth parameters. Smaller polypitch and spacer length resulted in greater sensitivity to temperature, in contrast with SiGe pocket depth, as greater SiGe pocket depth seemed to correspond to greater temperature susceptibility. In literature, it is reported that channel stress is enhanced with polypitch scaling. 21 Scaling the spacer length as well as SiGe pocket depth could also contribute to channel stress. Reducing the HfO2 thickness: 2nm 2.2nm 2.5nm 3nm 4nm Ref  SiO2 thickness:.5nm.6nm.7nm.8nm 1.nm 4 Ref  Stress temp: (d) MG thickness: 1.8 nm 2 nm 3 nm 5 nm 6 nm Ref  4 (f) Stress temp: Fig. 4. Oxide field dependence at stress time of 1 ms and 1 s for stress temperature of 375 K with different values of (a, b) HfO 2 thickness, (c, d) SiO 2 thickness, and (e, f) metal gate thickness. The trend of the results is in agreement with previous works. 25,4, Ref  3nm HfO2 HfO2 thickness: 2nm; Ea 36.1 mev 2.2nm; Ea mev 3nm; Ea mev (b).6 nm Ea mev (c).8 nm Ea.27 mev Ref  2nm HfO2 SiO2 thickness:.5nm.6nm.5 nm.8nm Ea mev 5 nm Ea mev 3 nm Ea mev nm Ea 59.9 mev /kT (ev -1 ) MG thickness: 1.8nm 3nm 5nm Fig. 5. Arrhenius plots for various thicknesses of HfO 2, (b) SiO 2, and (c) metal gate in order to obtain the activation energy (E a ). spacer length will result in higher channel stress, 45 while reducing the SiGe pocket depth will lead to reduced stress in the channel. 46 Channel stress enhances the hole tunneling probability, thus facilitating breakage of Si H bonds at the Si SiO 2 interface, which creates more interface traps. 47,48 Interface traps are sensitive to temperature; 49,5 the temperature sensitivity is seen in the plots in Fig. 7. Influence of Process Variations on NBTI In addition to the geometric parameters, the influence of process design variations on NBTI was also investigated by varying the boron dose of the highly doped drain (HDD), the metal gate work function of the device, and the halo doping concentration. Boron is widely known to enhance NBTI degradation due to boron penetration into the gate oxide. 51 Boron diffusion from the HDD region into the gate oxide can result in higher initial density of electrically activated defects at Si SiO 2 near channel edges. 52 The threshold voltage degradation over
8 Alimin, Radzi, Sazali, Hatta, Soin, and Hussin DVth - DVth (1s) DVth - DVth (1s) DVth - DVth (1s) nm HfO2 Stress temp: DVth (V): DVth - DVth (1s) : -8MV/cm -8MV/cm Stress temp: 1 3 DVth (mv) 1 3.5nm SiO2 Stress temp: DVth : DVth - DVth (1s) : -8MV/cm -8MV/cm Stress temp: 2nm HfO2: -8MV/cm 3nm HfO2: -8MV/cm.5nm SiO2: -8MV/cm.8nm SiO2: -8MV/cm (b) DVth (mv) 1 3 5nm MG Stress temp: DVth : DVth - DVth (1s) : -8 MV/cm -8 MV/cm -12 MV/cm -12 MV/cm nm MG: -8 MV/cm -12 MV/cm 5nm MG: -8 MV/cm -12 MV/cm Stress temp: (c) Fig. 6. Adjusted DV th for 2 nm and 3 nm HfO 2, (b).5 nm and.8 nm SiO 2 IL, and (c) 2 nm and 5 nm metal gate thickness. Insets show the total DV th compared with DV th DV th (1 s). stress time at 3 K, 35 K, and 375 K for different HDD boron doses is shown in Fig. 8, in agreement with previous study where higher boron dose was observed to cause higher V th degradation. 53 Figure 9 shows the total current density of a device with metal gate work function of 3. ev stressed under oxide field of 12 MV/cm at stress temperature of 375 K. It is clear that the total current density shows degradation after the device was stressed for 1 s. The total current density in the channel was reduced by 64.15% after stress. The threshold voltage degradation obtained when varying the metal gate work function is shown in Fig. 1. It is observed that higher metal gate work DVth (V) DVth (V) DVth (V) nm Polypitch: 6nm Polypitch: (b) 14nm Spacer length: 4nm Spacer length: (c) 3nm Pocket: 5nm Pocket: 1 3 Fig. 7. V th degradation (DV th ) for polypitch of nm and 6 nm, (b) spacer length of 14 nm and 4 nm, and (c) SiGe pocket depth of 3 nm and 5 nm for stress temperature of 3 K, 35 K, and 375 K. function resulted in higher V th degradation. The high V th degradation is caused by trapped electrons in HfO 2 that discharge to the substrate when the IL is thin, and this problem is aggravated for high metal gate work function, for which more trapped electrons are at energies above the equilibrium Fermi level and are therefore free to discharge to the substrate. 54 Figure 11 shows the V th degradation of a PMOS device with halo doping of cm 3 and cm 3 for stress temperature of 4 K for 1 s. These results reveal no significant change in the threshold voltage degradation when varying the halo doping. This may be due to the halo structure, which is slightly further from the SiO 2 bulk interface, where most of the defects are located according to Ref. 55.
9 Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p-mosfets on Negative-Bias Temperature Instability and Study of Defects (b) 1 Oxide field, Eox: -1MV/cm -14MV/cm Halo doping: 8.5 x 2 cm -3 Stress temp: 4K 1 Oxide field, Eox: -1MV/cm -14MV/cm Halo doping: 5 x 6 cm -3 Stress temp: 4K 3.2 x 1 cm -3 Boron: 9 x 5 cm -3 Boron: 1 3 Fig. 8. V th degradation (DV th ) for different HDD boron doses for stress temperatures of 3 K, 35 K, and 375 K. Higher HDD boron dose corresponds to higher DV th. Fig. 9. Total current density at stress temperature of 375 K for a device with metal gate work function of 3. ev (left: prestress 2.5 MV/cm; right: stress at 12 MV/cm) eV 4.eV Stress temp: 3.eV Oxide field, Eox: -8MV/cm -9MV/cm -1MV/cm -11MV/cm Fig. 1. V th degradation (DV th ) at stress temperature of 375 K with oxide field of 12 MV/cm for device with metal gate work function of 3. ev, 4. ev, and 5. ev. Higher metal gate work function results in higher threshold voltage shift. CONCLUSIONS We present analysis of the effects of geometric and process parameters of advanced-process 32-nm PMOS devices on NBTI. The threshold voltage degradation is observed to increase considerably when the high-k layer or metal gate layer thickness is increased, whereas increasing the SiO 2 interfacial layer thickness results in reduced threshold voltage Fig. 11. V th degradation (DV th ) of PMOS device with different halo doping of cm 3 and (b) cm 3 for stress temperature of 4 K for 1 s. shift. It is found that the V th degradation shows the strongest dependence on the SiO 2 IL thickness, compared with the HfO 2 high-k or metal gate thickness. Changing the SiO 2 IL thickness is shown to affect the V th degradation by 96.16% more than changing the HfO 2 thickness and by 8.67% more than changing the metal gate, at stress temperature of 375 K for stress time of 1 s. The temperature insensitivity during short stress time of 1 s indicates absence of generated defects and presence of preexisting defects, as generated defects show strong temperature dependence. At high oxide field, more generated traps are observed for thinner SiO 2 IL and thicker metal gate thickness. This indicates that inclusion of the metal gate after integration of high-k technology can result in substantial BTI effects. Regarding the process design, higher HDD boron dose is shown to deteriorate the threshold voltage due to penetration of boron into the gate oxide. Our results also show that higher metal gate work function exacerbates trapped carriers in HfO 2, leading to attenuation of the threshold voltage. NBTI is found to be independent of the halo doping concentration, which may be due to the location of the halo structure slightly farther from the SiO 2 bulk interface of the device. ACKNOWLEDGEMENTS The authors are grateful for financial support provided by the Ministry of Higher Education (MOHE) for FRGS: FP45-214B, 6-RMI/FRGS 5/3 (31/215) and the University of Malaya for Postgraduate Research Fund (PPP): PG A. REFERENCES 1. M. Bohr, in Intel Developer Forum 214 (Intel Corporation, 214). 2. S. Hall, O. Buiu, I.Z. Mitrovic, Y. Lu, and W.M. Davey, J. Telecommun. Inf. Technol. 33 (27). 3. G.D. Wilk, R.M. Wallace, and J. Anthony, J. Appl. Phys. 89, 5243 (21). 4. Samsung, 32/28 nm Low-Power High-K Metal Gate Logic Process and Design Ecosystem (Samsung Semiconductor Inc, San Jose, CA, 211). 5. Global Foundries, Low Power High-k Metal Gate 28 nm CMOS Solutions for Mobile High Performance Applications (Global Foundries Inc., 211).
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