Simulation of Gate Leakage Currents in UTB MOSFETs and Nanowires Andreas Schenk ETH Zurich

Transcription

1 Simulation of Gate Leakage Currents in UTB MOSFETs and Nanowires Andreas Schenk ETH Zurich

2 Outline Introduction Simulation approaches EMA-based methods Ab-initio methods Model calibration using capacitors and FETs Results for nanowires and DG-UTB FETs Conclusion SINANO/NANOSIL 2009 Athens A.Schenk 2

3 Introduction High-K oxides, such as HfO 2, are now incorporated into the gate stacks of silicon-based MOSFETs (INTEL). High-K gate stacks typically contain interfacial SiO x and are contacted by a metal electrode. TCAD simulation of gate leakage requires parameter set (permittivities, band offsets, tunneling masses). Extracted parameters depend on physical model (1D 2D, classical density quantummechanical density). INTEL Penryn, 45nm, picture from HR-TEM of a MOSCAP with interfacial SiO x thickness of 6 Å and an HfO 2 thickness of 37 Å. P. Hurley et al., TYNDALL SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 3

4 Simulation approaches EMA-based methods Sentaurus-Device: Nonlocal Barrier Tunneling, if WKB 1D tunneling along non-local lines. Various assumptions (no k -conservation, plane waves outside, etc.). Fully coupled to DD, EB, QDD, 1D-SP, trapping. WKB or Scattering Matrix Approach, two-band model. DG-correction for quantization, interface transmission model T CC for Γ CC. Different pre-factors for different valley pairs (2D eff. masses) needed! SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 4

5 EMA-based methods (2) For comparison: WKB transmission through rectangular barrier: -2d 2m ox (E-E B ) /ħ (E) = e Critical parameters are E B and m ox (exponential), all others pre-exponential SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 5

6 EMA-based methods (3) Gamov s method 1D tunneling based on Gamov s picture of nuclear decay (1928). i ( ) resonance lifetime of a quasi-bound state in the channel leaking into the gate. Resonance width i ( ) found numerically by solving the 1D Schrödinger equation in a domain that covers substrate, insulator, and gate. Precondition: i ( ) << E i ( ) range of deep inversion only. Numerical expensive to trace peak position and spectral width. Less suited for integration into TCAD packages SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 6

7 EMA-based methods (4) Density-gradient method Non-perturbative formulation with smoothed potential Quantum potential Λ has to be fitted for each material (by comparison with Schrödinger). Additional coupled equation for Λ. Multi-dimensional per se. Tunnel barriers strongly reduced by quantum potential. Barrier regions treated as wide-gap semiconductors with oxide parameters. Tunnel current becomes a drift-diffusion current in the barrier a mobility has to be faked for the oxides, i.e. calibration needed. Method seems appealing for TCAD, but many problems SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 7

8 EMA-based methods (5) Wave function (WF) or ballistic NEGF method (GreenSolver) Missing or bad TB parametrization for gate stacks EMA. Popular mode-space approx. not suited multi-terminal real space simulator needed. 2D/3D Schrödinger equation H ψ E > = E ψ E > Finite difference discretization of the wave function <r ψ E > = Φ(x i,y j ;E) δ(r -R ij ) ij Scattering Boundary Conditions => ordinary eigenvalue problem!! M Φ B = 2 cos(k B ) Φ B Sparse linear problem Ax=b: (E-H-Σ S -Σ D -Σ G ) Φ = S Inj +D Inj +G Inj A SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 8

9 EMA-based methods (6) Σ G models the injection mechanism from the gate contact and destroys the block tri-diagonal structure of the matrix A. A can be symmetrized by a basis transformation LU factorization. All elements of Σ G can be taken into account in contrast to NEGF formalism. Carrier and current density Compared to Landauer-Büttiker formula this formulation allows to check current conservation. Final quantities result from self-consistency iteration with Poisson equation SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 9

10 Ab-initio methods Semi-empirical TB scattering method Städele et al simulation of Si[100]-SiO 2 -Si[100] sandwich with crystalline layers of tridymite and β-quartz different sizes of 2D elementary cell (band folding) and periodic perpendicular BCs in-plane lattice matching to a Si, relaxation of atom positions computed with VASP sp 3 bulk TB parameters for Si, O, Si-Si, Si-O, O-O band offset (barrier height) = input (3.1eV) elastic scattering theory for T(E) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 10

11 Ab-initio methods (2) fitted energy-dependent effective mass m tunn for oxide m CB (tridymite) = 0.41m 0 m CB (β-quartz) = 0.62m 0 Städele et al m ox (tridymite) = 0.25m 0 m ox (β-quartz) = 0.38m SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 11

12 Ab-initio methods (3) Städele et al fitted thickness-dependent effective mass m tunn for oxide claim: nonparabolicity of imaginary bands in the oxide gap + linearly graded potential in transition regions lead to strong thickness dependence of fitted m ox However, in tunnel current simulations, a constant mass yields good agreement Data: Toshiba (Momose et al. 1996) Sim: DESSIS (Schenk et al. 1996) m ox = 0.42 m 0 E B = 3.15 ev no k -conservation image force incl SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 12

13 Sacconi et al Ab-initio methods (3) simulation of Si[100]-HfO 2 -Si[100] sandwich with crystalline layers of cubic HfO 2 different sizes of 2D elementary cell (band folding) and periodic perpendicular BCs sp 3 d 5 s* bulk TB parameters band offset (barrier height) = input (1.54eV) elastic scattering theory for T(E) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 13

14 Model calibration using capacitors and FETs n-si(100)/sio x /HfO 2 /Ni MOS capacitors. Samples with FGA at 400 C for 30 min low D it. HR-TEM determination of SiO x and HfO 2 thicknesses (accurate to ±2 Å). HfO 2 ~ 35 Å, SiO x ~ 6 Å. MOSFETs on Si(100) and ALD HfO 2 /TiN gate stacks (D it ~4x10 10 cm -2 from charge pumping). Gate dimensions 10 m x 10 m. Parameter fit for all devices (see table). M. A. Negara et al., Microelectronic Eng. 84, 1874 (2007). Wafer A B C D t-hfo 2 [Å] t-siox [Å] Cox eff [F/cm 2 ] 2.43x x x x10-6 VFB [V] EOT [Å] Na [x /cm 3 ] µ peak [cm 2 /V.s] SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 14

15 HfO 2 gate stack capacitors Model: Non-local barrier tunneling (Sentaurus-Device) without DG correction. Good fits for V s < -0.7 ev. Direct tunnelling is the dominant leakage mechanism. The best lower fit (solid line) has an electron tunneling mass and electron affinity for HfO 2 of m HfO2 = 0.11m 0 and χ HfO2 = 1.75 ev. The best upper fit (dashed line) has an electron effective mass and electron affinity for HfO 2 of m HfO2 = 0.135m 0 and χ HfO2 = 2.0 ev. t HfO2 = 3.5 nm. ε HfO2 = 23. t SiOx = 0.6 nm. ε SiOx = 4.4. χ SiOx = 1.4 ev. m SiOx = 0.5m 0. χ Si = 4.05 ev. Ni gate work function = 4.71 ev SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 15

16 LaLuO and GdScO 3 gate stack capacitors (CV) Effective gate work functions Φ M,eff fitted neglecting any oxide charges. To reproduce C max, the interlayer capacitance had to be changed. Two limiting cases result in the black curves: For LaLuO: t SiOx =1nm, ε SiOx = 5.6 or t SiOx =0.7nm, ε SiOx = 3.9. For GdScO 3 : t SiOx =1nm, ε SiOx = 7.8 or t SiOx =0.5nm, ε SiOx = 3.9. The two limiting cases are used for the gate tunneling computation. The measured CV curves are stretched out compared to the simulated, which is probably due to charging/discharging of the stack during sweep. Data provided by Jürgen Schubert, FZ Jülich GmbH SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 16

17 LaLuO and GdScO 3 gate stack capacitors (IV) Dashed blue curves are the simulations with reduced interlayer thickness, black curves with increased permittivity. The difference is small showing that the current is mainly blocked by the high-k layer. To reproduce the gate currents at large negative bias, the tunneling mass in the high-k layer was fitted (assuming the band offsets as given and using m SiOx =0.5 m 0 ). For LaLuO: m LaLuO =0.0306m 0 with t SiOx =1.0nm and m LaLuO =0.0475m 0 with t SiOx =0.7nm. For GdScO 3 : m GdScO3 =0.084m 0 with t SiOx =1.0nm and m GdScO3 =0.155m 0 with t SiOx =0.5nm. Tunneling masses for LaLuO extremely small, those for GdScO 3 comparable to HfO 2. Data provided by Jürgen Schubert, FZ Jülich GmbH SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 17

18 MOSFETs with ALD HfO 2 /TiN gate stacks Series of simulations: (i) varying t HfO2 ; (ii) varying t SiOx ; (iii) varying tunneling masses and affinities. Device A t HfO2 = 1.6nm t SiOx = 1.0nm Simulation results are compared to measurements and best fits are determined over voltage range 0.5 V V. Experimental (circles) and simulated (solid) gate and drain currents for devices A, B, C, and D (V ds = 10 mv) are shown. The best fits for HfO 2 are m HfO2 = (0.11±0.03)m 0, χ HfO2 = (2.0±0.25) ev. The equivalent SiO x parameters are m SiOx = 0.5m 0, χ SiOx = 1.4 ev. Sign changes in I d : 1 st is at 10 mv drain bias before onset r Ch > r TB in sub-v th regime; 2 nd is at V th (when channel conductivity > tunnel barrier); 3 rd is when r Ch > r TB. Device B t HfO2 = 2.0nm t SiOx = 0.92nm S. Monaghan et al., SSE 53(4), 438 (2009) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 18

19 MOSFETs with ALD HfO 2 /TiN gate stacks (2) Device C Best I-V fits requires that t SiOx reduces (1 nm to 0.77 nm) as t HfO2 increases (1.6 nm to 3 nm), which is indicative of a stoichiometric change in the SiO x layer as t HfO2 increases. t HfO2 = 2.4nm t SiOx = 0.92nm Accurate simulation for V g less than ~0.6 V not possible due to doping profile variations under gate corners and unknown gate overlap conditions. Device D The TiN gate work function is 4.6 ev, with a negligible change of ±0.03 ev over all devices. t HfO2 = 3.0nm t SiOx = 0.77nm S. Monaghan et al., SSE 53(4), 438 (2009) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 19

20 Results for nanowires and DG-UTB FETs Isosurfaces of the gate current for a triple-gate structure SiO 2 dielectric layer + TiN metal contact Current strongly concentrated at the gate corners V gs =-0.2 V, V ds =0.05 V V gs =0.0 V, V ds =0.60 V L g =10 nm t Si =3nm 3D WF method, GreenSolver (ETH) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 20

21 Nanowires (2) Gate stack: SiO 2 (0.5 nm) + HfO 2 (3.5 nm, m* = 0.2 m 0, ε R = 25) Performance: Good threshold voltage V th, low off-current I OFF Dielectric + Contact Structure Transfer Characteristics SiO ev HfO 2 HfO 2 TiN Si 3.5 nm TiN 3D WF method, GreenSolver (ETH) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 21

22 Nanowires (3) Stack reduces gate current by 7 orders of magnitude at low V gs, off-current by a factor of 40, and keeps the same on-current V DD = 0.6 V and EOT = 1 nm 1e7 40 Comparison of V th, I ON, and I OFF poly-si + TiN + TiN + SiO 2 SiO 2 Stack V th (V) I ON (μa) I OFF (na) 6.7 / 447x 0.63 / 42x / 1x 3D WF method, GreenSolver (ETH) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 22

23 DG-UTB FETs 22nm DG n-fet with high-k gate stack Doping profile optimized by PULLNANO consortium to meet IRTS off-leakage requirements for LSTP (without GIDL) SiO 2 L g =22nm t HfO2 =2.4nm t SiOx =0.8nm 2.0 ev HfO 2 HfO 2 t Si =10nm TiN Si TiN (0,0) 2.4 nm Gate stack (calibrated in PULLNANO): SiO 2 (0.8 nm, m tunn = 0.5 m 0, ε SiO2 = 3.9) + HfO 2 (2.4 nm, m tunn = 0.11 m 0, ε HfO2 = 23) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 23

24 DG-UTB FETs (2) Gate current characteristics for low and high V ds V ds = 0.1 V V ds = 1.0 V net intunneling net outtunneling net intunneling net outtunneling offstate onstate 2D: GreenSolver (ETH), 1D: S-Device (Synopsys) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 24

25 DG-UTB FETs (3) Gate currents for stack compared to pure SiO 2 with the same EOT V ds = 1.0 V D: GreenSolver (ETH), 1D: S-Device (Synopsys) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 25

26 DG-UTB FETs (4) Transfer characteristics for stack compared to pure SiO 2 with the same EOT (based on a gate work function of 4.6 ev) V ds = 1.0 V SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 26

27 DG-UTB FETs (5) Explanation of difference between 1D and 2D out-tunneling (ON-state) in-tunneling (OFF-state) spacer effect (b and c) cannot explain difference between 1D and 2D at low V gs the potential barrier in Si increases the tunnel length (a) compared to (d), but doping level at starting point of (a) is much higher compared to (d) at high drain bias the potential drops rapidly in the pinch-off region electrons arriving at a final state on (f) have a much larger velocity compared to (e). This explains the higher current SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 27

28 DG-UTB FETs (6) Electron diffraction in the case of a high-k stack obvious similarity with light diffraction (refraction) in a thin film wave number of the matter wave depends on work function SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 28

29 Conclusion TCAD simulation of gate tunneling only practical with EMA-based approach. VASP + TB might yield m tunn parameters for other materials in the future. Band offsets are crucial. 1D tunneling remains the workhorse. The more accurate 2D treatment of gate leakage always results in a larger tunnel current compared to the 1D case. This is due to electron diffraction at the gate corners. WF formalism has a much better numerical efficiency than NEGF for coherent transport like gate tunneling. The actual off-state leakage is determined by in-tunneling electrons at the drain-side gate corner. By diffraction they can arrive at points with a high energetic distance to the CB (pinch-off) high carrier velocity higher current. For a 22nm DG-UTB FET this increases the off-current by a factor of 3 (high-k stack) and 7 (SiO 2 ) SINANO/NANOSIL 2009 Athens A.Schenk schenk@iis.ee.ethz.ch 29

30 Acknowledgement The author would like to thank Dr. Andreas Wettstein (Synopsys Zurich) for fruitful discussions and Swiss National Science Foundation ( /1) EU IST IP-PULLNANO EU IST NANOSIL for financial support SINANO/NANOSIL 2009 Athens A.Schenk 30