Metal Gate / High-k Reliability Characterization: From Research to Development and Manufacturing. Andreas Kerber, PhD Technology Research Group

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1 Metal Gate / High-k Reliability Characterization: From Research to Development and Manufacturing Andreas Kerber, PhD Technology Research Group

2 Acknowledgement Colleagues at GLOBALFOUNDRIES, IBM, and research partners E. Cartier, T. Nigam, W. McMahon, T. Cahyadi, G. Krause, D. Lipp, D. Rudolph, B.P. Linder, K. Zhao, S. Zafar, M. Wang, S.A. Krishnan, F. Monsieur, K. Maitra, M. Hargrove, R.J. Carter, J. Stathis, V. Narayanan, A. Marathe, GLOBALFOUNDRIES management support J. Iacoponi, M.-R. Lin, This work was partially performed by the Research Alliance Teams at various IBM Research and Development facilities SEMATECH AGST Symposium

3 Motivation Metal gate / high-k MOS process and device research has emerged in the past decade and is used in CMOS technologies since the 45nm technology node To further increase the confidence in the use of MG / HK it is important to address reliability issues both from scientific and engineering perspectives Generate fundamental understanding about defect generation and its implication on reliability projection (BTI, TDDB, hot carrier degradation, ) Introduce novel characterization procedures that properly capture the degradation processes SEMATECH AGST Symposium

4 Outline Introduction Metal Gate / High-k (MG/HK) background Bias temperature instability (NBTI, PBTI) Stress-induced leakage current (SILC) in nfet devices Dielectric breakdown Summary Outlook SEMATECH AGST Symposium

5 Introduction The use of MG HK presents the biggest change in gate stack in the last decade and thus requires thorough reliability investigations Conventional Gate-first MG / HK Poly-Si Poly-Si Metal gate S SiO 2, SiON Si D S High-k Interfacial layer Si D SEMATECH AGST Symposium

6 Introduction (cont) Substantial learning in electrical characterization and reliability has been made for MG HK devices throughout the years: Negative bias temperature instability (NBTI) remains a reliability challenge for pfet devices Positive bias temperature instability (PBTI) emerged as reliability challenge for nfet devices Stress-induced leakage current increase reported for nfet devices Time dependent dielectric breakdown (TDDB) complicated by the dual-layer nature of the gate dielectric stacks Further reliability topics remain important for MG HK CMOS technologies (e.g., hot carrier degradation, low frequency noise, ) SEMATECH AGST Symposium

7 MG HK background: Integration Approaches K. Mistry et al., p.247, IEDM 2007 M. Chudzik et al., p.194, VLSI 2007 TEM of Intel high-k + metal gate 45 nm PMOS transistor High-k-first / metal-gate-last process flow quasi replacement TEM of IBM high-k + metal gate 45 nm NMOS transistor Gate-first integration scheme with high-k/metal gate electrodes SEMATECH AGST Symposium

8 MG HK background: Gate Stack and nfet Band Diagram Gate stack structure Band diagrams (nfet) Poly-Si a) S Metal Gate High-ε Interfacial layer D Si SiO 2 HfO 2 TiN E F b) c) Vg>0 Vg<0 Substrate d) Basic gate stack structure contains interlayer, high-k dielectric, and metal electrode To meet band-edge work function either metal electrode tuning, capping layers, or substrate engineering are typically employed SEMATECH AGST Symposium

9 MG HK background: Gate Tunneling Currents / Carrier Separation A. Kerber and E. Cartier. IEEE TDMR, Vol. 9, No. 2, pp , a) pfet inversion b) 10 0 nfet inversion I sub /I sd I sd :Holen tunneling (Inversion layer to gate) I sub : Electron tunneling 10-5 (Gate to Si conduction band) V t p I sd :Electron tunneling Gate Voltage(V) For nfets, inversion layer electrons are the dominant contributor to the tunneling current at operation and stress condition For pfets, hole and electron tunneling become comparable at stress condition V t n (Inversion layer to gate) I sub : Electron tunneling (Si valace band to gate) SEMATECH AGST Symposium

10 MG HK background: NBTI / PBTI comparison MG HK versus Poly-Si / SiON A. Kerber et al. IEEE TED, Vol. 55, No. 11, pp , NBTI for MG HK comparable to conventional poly-si / SiON stacks PBTI emerged as reliability challenge for MG HK nfet devices SEMATECH AGST Symposium

11 NBTI & PBTI Time Evolution A. Kerber et al., IEEE EDL, Vol. 30, No. 12, pp , fit range 0.1 fit range NBTI V T (V) V -1.5 V T=125 O V C -2.0 V t delay =1ms V -2.5 V 1E-3 1E Time (s) V T (V) V 1.6V T=125 O C 1.4V t delay =1ms 1.2V 1E-3 1E Stress Time (s) PBTI Power law time exponent, n Gate Voltage (V) Power law time exponent, n Gate Voltage (V) Similar time evolution for MG / HK NBTI and PBTI Power law time exponents ranging between 0.18 and 0.13, which are comparable to conventional poly-si / SiON stacks Note the gradual change in slope saturation behavior SEMATECH AGST Symposium

12 PBTI Time Evolution versus Sense Delay V t (V) E-3 2.2nm HfO 2 / TiN 2V 125 O C, V Sense =0.6V 1.75V 1.5V 1.25V Stress time (s) measurement delay: ~30µs 100µs 1ms 10ms 100ms 1s 1s + 1s at 0V A. Kerber et al., IEEE TED, Vol. 55, No. 11, pg. 3175, Power law exponent, n T=125 O C HfO 2 thickness: slow (1s) fast (30µs) 1.7nm 2.2nm Stress voltage (V) Significant impact of sense delay on PBTI shift and time evolution fast measurement techniques essential to capture worst-case shift and to improve projection model SEMATECH AGST Symposium

13 PBTI Relaxation (1 of 2) V t (V) A. Kerber et al., IEEE TED, Vol. 55, No. 11, pg. 3175, V 2V 1.75V V 2.2nm HfO 2 / TiN 0.02 Stress at 125 O C for 10s E-5 1E Relaxation time (s) V α (mv/dec) t = V 1.7 nm HfO 2, T= 125 O C: t ( 1s) α log( t) 1.5 V < Vg < 2.25 V, t stress = 100 s 1 < t stress < s, Vg = 1.75 V 1.3 nm SiON, T= 125 O C: -1.5 V > Vg > -2.5 V, t stress = 1000 s To first order, the V t recovery can be modeled by a log(t) dependence Linear relation between V t (1s) and α for short stress and low shifts 4 2 V t (1s) (mv) SEMATECH AGST Symposium

14 PBTI Relaxation (2 of 2) d( V t )/dt (V/s) 10 3 V stress = 125O C: A. Kerber et al., IEEE TED, Vol. 55, No. 11, pp. 3175, nm SiON, 1000 s 2.2 nm HfO 2, 10 s 1.7 nm HfO 2, 100 s Relaxation time (s) Log(t) recovery corresponds to 1/t recovery rate charge removal by tunneling the likely cause Striking similarities between conventional poly-si / SiON and MG HK stacks SEMATECH AGST Symposium

15 Impact of Stress Mode on PBTI Relaxation V tlin (a.u) DC stress AC 50% duty cycle T s = s 1000 s 100 s 0.2 T = 50 o C 10 s V 1 s 0.0 stress = 1.5 V Relaxation time (sec) V V tlin (a.u) Relaxation after AC stress shows shallower slope at short times and merges with DC relaxation at longer times Relaxation modulated by stress time and duty cycle K. Zhao et al., IRPS, pp , DC AC 99% AC 90% AC 50% AC 10% AC 1% 0.2 T = 50 o C V stress = 1.5 V Trap occupancy F Relaxation Time (sec) DC stress Ts increase Et, X E t,, X SEMATECH AGST Symposium Trap occupancy F AC stress shallow traps modulation

16 Impact of Stress Mode on PBTI degradation recovery A. Kerber and E. Cartier. IEEE EDL, Vol. 31, No. 9, pp , stress 1:1 unipolar bipolar AC Gate V Idlin (V) bipolar AC unipolar Voltage (au) O C V tlin (V) Drain Time (ms) Unipolar PBTI stress leads only to a shift in transistor characteristics bulk trapping Bipolar PBTI stress leads to shift and degradation of transistor characteristics bulk trapping and interface degradation Time (ms) Bulk trapping shows transient nature whereas interface degradation is permanent SEMATECH AGST Symposium

17 SILC Polarity Dependence (poly-si / HfO 2 nfet devices) F. Crupi, et al., IRPS, pp. 181, Strong polarity dependence in SILC formation for substrate injection one-to-one correlation between HfO 2 trap density and SILC SILC traps believed to be different from preexisting defects responsible for hysteresis J stress = n = 0.65 Vg B e B t n SEMATECH AGST Symposium

18 nfet SILC Formation and Reversibility (TiN / HfO 2 nfet devices) Gate Current (A) V st = 1.6 V 10 4 s a) Afer stress 1 s increasing stress time down-sweep T = 195 o C WxL = 100x10 µm 2 up-sweep b) After -1 V discharge Gate Voltage (V) Dramatic SILC reductions after negative bias discharge SILC ( Ig / Ig) shows single broad peak and is attributed to electron traps in HfO 2 Gate Voltage (V) I g /I g E. Cartier et al., IRPS, pg. 486, t t t s 3 s 1 s 2 V s V d 5x10 2 4x10 2 3x10 2 2x10 2 1x10 2 τ d τ r Stress Sense (I d -V g ) Time (arb. units) T = 195 o C V s = 1.6 V Electron traps in HfO Gate Voltage (V) Increasing stress time SEMATECH AGST Symposium

19 nfet SILC Formation and Reversibility: (TiN / HfO 2 nfet devices) e trapping e e detrapping - V Ō E. Cartier et al., IRPS, pg. 486, A. Kerber et al., IRPS, pg. 505, A. Kerber et al., IRPS, pg. 369, e trapping - - V O TAT V O TAT e Oxygen vacancies charged during positive gate stress resulting in TAT sites SEMATECH AGST Symposium

20 SILC Behavior for HfSiOx / TaN nfet Devices S. Sahhaf et al., IRPS, pg. 493, Double peak observed in SILC when stress at high temperature Deeper energy level, P1, defect either generated in the interlayer or in the HfSiOx Shallower energy level, P2, only generated during high-temperature stress and attributed to a defect in the HfSiOx layer SEMATECH AGST Symposium

21 Alternative Interpretation of SILC ( SEMATECH view ) G. Bersuker et al., IEDM, pg. 791, 2008 C.D. Young et al., IEEE TDMR, Vol. 6, No. 2, pg. 123, 2006 Strong correlation between charge pumping and SILC If CP only probes the interlayer, SILC is caused by interlayer defects!?! SEMATECH AGST Symposium

22 SILC Improvement by Process Optimization S. Pae et al., IRPS, pg. 499, SILC improvements feasible by process optimization Layer thickness engineering or change in materials property?? SEMATECH AGST Symposium

23 TDDB Figure of Merit (nfet & pfet) 1E6 A. Kerber et al., IRPS, pg. 505, t63% for 1µm 2 at +/-2.5V (s) 1E nfet, 125 O C pfet, 125 O C Leakage at reference bias (A/cm 2 ) Strong correlation between t63% and gate leakage current for both nfet and pfet devices SEMATECH AGST Symposium

24 MG HK TDDB failure distributions ln (-ln(1-f))-ln(ai/1µm 2 ) 7 6 nfet, 125 O C β=0.8 5 Vstress=2.5V Area ranging from -5 β= to 0.6µm 2-6 1E-4 1E TBD (s) ln(-ln(1-f))-ln(ai/1µm 2 ) A. Kerber et al., IRPS, pg. 505, solid symbols: measured 4 open symbols: scaled 3 β= pfet, 125 O C V V Area (µm 2 ): , β=1.1 15, 30, E TBD (s) Change in Weibull slope clearly evident for nfets For pfet devices, change in slope only obvious when distribution is extended using larger areas Poisson scaling / vertical area scaling remains valid SEMATECH AGST Symposium

25 Implication of Gradual Change in Failure Distribution nfet pfet t63% A. Kerber et al., IRPS, pg. 505, Area 1 β const t63% (s) E Area (µm 2 ) Area-to-time transformation fails because the underlying distribution is not standard Weibull F( t) 1 exp t t63% β SEMATECH AGST Symposium

26 Explanation for Change in Failure Distribution with Gate Area Competing degradation of a dual layer gate stack Failure distribution well described by applying the percolation concept with the assumption of different defect generation rates for interface and high-k layer T. Nigam et al., IRPS, pg. 523, Progressive failure Because failure distributions are comparable to ultra-thin SiON / poly-si stacks; it is also feasible that a similar concept may also apply to MG HK Current time traces, however, do not support a very significant contribution to the change in failure distribution SEMATECH AGST Symposium

27 BTI Screening and Monitoring of MG HK (Voltage ramp stress) 0.1 T=125 O C t delay =1ms A. Kerber and E. Cartier. IEEE TDMR, Vol. 9, No. 2, pp , A. Kerber et al., IEEE EDL, Vol. 30, No. 12, pp , V Conventional CVS V V T (V) V/s 1 V/s 0.1 V/s 0.01 V/s V/s 1E Stress Voltage (V) Voltage shift based on VRS and CVS are well correlated preferred screening procedure because limited knowledge about the gate stack is required V t = 0 t V t = 0 V T V ( t, Vg) = T VRS At 1 ( RRVg, ) = A RR n n Vg time m Vg time m+ n ( m ) n + 1 n SEMATECH AGST Symposium

28 TDDB Screening and Monitoring of MG HK (Voltage Ramp Stress) ln(-ln(1-f))-ln(a i /A 0 ) ln(-ln(1-f)) V slope = β µm µm 2 1 µm µm 2 10 µm 2 based on CVS µm µm µm 2 based on CVS slope = β (n+1) Ramp rate = 0.1V/s n-fet acc 2 CVS ref data: n=43 0 β=0.8 V Stress = t63%=9.5-4 TBD (s) 0.01 Ramp rate = Area=0.09µm V/s VBD (-V) VBD (V) V A. Kerber et al., presented at WoDIM, 2006, published in Microelectronics Reliability Volume 47, Issue 4-5, pp , V t = 0 Conventional CVS t t = 0 VRS time Good quantitative agreement between CVS and VRS breakdown data SEMATECH AGST Symposium V TBD = 1 RR 1 Veff n time n VBD n

29 Summary Compared to conventional CMOS technologies, PBTI and SILC in nfet devices are confirmed as emerging technology challenges for MG HK PBTI shows similar magnitude and kinetics as NBTI and also comparable recovery behavior SILC remains controversial because it is attributed to trap-assisted tunneling through either HfO 2 defects or inter-layer defects MG HK TDDB shows strong correlation with gate leakage current and thus serves as figure of merit for process development Change in failure distribution is observed towards large areas / low failure percentiles dual layer percolation model was introduced for MG HK For monitoring and process screening, Voltage ramp stress is proposed, which is in good quantitative agreement with the CVS method SEMATECH AGST Symposium

30 Outlook Attempts have been made to demonstrate defect generation and identify the defect nature in MG HK stacks, but the literature still remains controversial Some of the open questions are: Trap filling versus trap generation during PBTI?? Why are NBTI and PBTI kinetics, including recovery, so similar?? Can MG HK provide a better inside-into reaction-diffusion versus hole trapping?? What are the controlling parameters for SILC?? Material property or just thickness engineering Is it of concern for higher temperature applications?? (e.g., automotive & industrial) Where does defect generation occur?? Interlayer, high-k layer, or both?? What is the correlation between SILC defects and TDDB??. SEMATECH AGST Symposium

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